arch/arm/dts/stm32f469-disco-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <dt-bindings/memory/stm32-sdram.h>
   8 /{
   9         clocks {
  10                 u-boot,dm-pre-reloc;
  11         };
  12
  13         aliases {
  14                 /* Aliases for gpios so as to use sequence */
  15                 gpio0 = &gpioa;
  16                 gpio1 = &gpiob;
  17                 gpio2 = &gpioc;
  18                 gpio3 = &gpiod;
  19                 gpio4 = &gpioe;
  20                 gpio5 = &gpiof;
  21                 gpio6 = &gpiog;
  22                 gpio7 = &gpioh;
  23                 gpio8 = &gpioi;
  24                 gpio9 = &gpioj;
  25                 gpio10 = &gpiok;
  26         };
  27
  28         soc {
  29                 u-boot,dm-pre-reloc;
  30                 pin-controller {
  31                         u-boot,dm-pre-reloc;
  32                 };
  33
  34                 fmc: fmc@A0000000 {
  35                         compatible = "st,stm32-fmc";
  36                         reg = <0xA0000000 0x1000>;
  37                         clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
  38                         st,syscfg = <&syscfg>;
  39                         pinctrl-0 = <&fmc_pins_d32>;
  40                         pinctrl-names = "default";
  41                         st,mem_remap = <4>;
  42                         u-boot,dm-pre-reloc;
  43
  44                         /*
  45                          * Memory configuration from sdram
  46                          * MICRON MT48LC4M32B2B5-6A
  47                          */
  48                         bank0: bank@0 {
  49                                st,sdram-control = /bits/ 8 <NO_COL_8
  50                                                             NO_ROW_12
  51                                                             MWIDTH_32
  52                                                             BANKS_4
  53                                                             CAS_3
  54                                                             SDCLK_2
  55                                                             RD_BURST_EN
  56                                                             RD_PIPE_DL_0>;
  57                                st,sdram-timing = /bits/ 8 <TMRD_2
  58                                                            TXSR_6
  59                                                            TRAS_4
  60                                                            TRC_6
  61                                                            TWR_2
  62                                                            TRP_2
  63                                                            TRCD_2>;
  64                                st,sdram-refcount = < 1292 >;
  65                        };
  66                 };
  67         };
  68 };
  69
  70 &clk_hse {
  71         u-boot,dm-pre-reloc;
  72 };
  73
  74 &clk_i2s_ckin {
  75         u-boot,dm-pre-reloc;
  76 };
  77
  78 &clk_lse {
  79         u-boot,dm-pre-reloc;
  80 };
  81
  82 &gpioa {
  83         compatible = "st,stm32-gpio";
  84         u-boot,dm-pre-reloc;
  85 };
  86
  87 &gpiob {
  88         compatible = "st,stm32-gpio";
  89         u-boot,dm-pre-reloc;
  90 };
  91
  92 &gpioc {
  93         compatible = "st,stm32-gpio";
  94         u-boot,dm-pre-reloc;
  95 };
  96
  97 &gpiod {
  98         compatible = "st,stm32-gpio";
  99         u-boot,dm-pre-reloc;
 100 };
 101
 102 &gpioe {
 103         compatible = "st,stm32-gpio";
 104         u-boot,dm-pre-reloc;
 105 };
 106
 107 &gpiof {
 108         compatible = "st,stm32-gpio";
 109         u-boot,dm-pre-reloc;
 110 };
 111
 112 &gpiog {
 113         compatible = "st,stm32-gpio";
 114         u-boot,dm-pre-reloc;
 115 };
 116
 117 &gpioh {
 118         compatible = "st,stm32-gpio";
 119         u-boot,dm-pre-reloc;
 120 };
 121
 122 &gpioi {
 123         compatible = "st,stm32-gpio";
 124         u-boot,dm-pre-reloc;
 125 };
 126
 127 &gpioj {
 128         compatible = "st,stm32-gpio";
 129         u-boot,dm-pre-reloc;
 130 };
 131
 132 &gpiok {
 133         compatible = "st,stm32-gpio";
 134         u-boot,dm-pre-reloc;
 135 };
 136
 137 &pinctrl {
 138         fmc_pins_d32: fmc_d32@0 {
 139                 u-boot,dm-pre-reloc;
 140                 pins
 141                 {
 142                         pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
 143                                  <STM32_PINMUX('I', 9, AF12)>, /* D30 */
 144                                  <STM32_PINMUX('I', 7, AF12)>, /* D29 */
 145                                  <STM32_PINMUX('I', 6, AF12)>, /* D28 */
 146                                  <STM32_PINMUX('I', 3, AF12)>, /* D27 */
 147                                  <STM32_PINMUX('I', 2, AF12)>, /* D26 */
 148                                  <STM32_PINMUX('I', 1, AF12)>, /* D25 */
 149                                  <STM32_PINMUX('I', 0, AF12)>, /* D24 */
 150                                  <STM32_PINMUX('H',15, AF12)>, /* D23 */
 151                                  <STM32_PINMUX('H',14, AF12)>, /* D22 */
 152                                  <STM32_PINMUX('H',13, AF12)>, /* D21 */
 153                                  <STM32_PINMUX('H',12, AF12)>, /* D20 */
 154                                  <STM32_PINMUX('H',11, AF12)>, /* D19 */
 155                                  <STM32_PINMUX('H',10, AF12)>, /* D18 */
 156                                  <STM32_PINMUX('H', 9, AF12)>, /* D17 */
 157                                  <STM32_PINMUX('H', 8, AF12)>, /* D16 */
 158
 159                                  <STM32_PINMUX('D',10, AF12)>, /* D15 */
 160                                  <STM32_PINMUX('D', 9, AF12)>, /* D14 */
 161                                  <STM32_PINMUX('D', 8, AF12)>, /* D13 */
 162                                  <STM32_PINMUX('E',15, AF12)>, /* D12 */
 163                                  <STM32_PINMUX('E',14, AF12)>, /* D11 */
 164                                  <STM32_PINMUX('E',13, AF12)>, /* D10 */
 165                                  <STM32_PINMUX('E',12, AF12)>, /* D09 */
 166                                  <STM32_PINMUX('E',11, AF12)>, /* D08 */
 167                                  <STM32_PINMUX('E',10, AF12)>, /* D07 */
 168                                  <STM32_PINMUX('E', 9, AF12)>, /* D06 */
 169                                  <STM32_PINMUX('E', 8, AF12)>, /* D05 */
 170                                  <STM32_PINMUX('E', 7, AF12)>, /* D04 */
 171                                  <STM32_PINMUX('D', 1, AF12)>, /* D03 */
 172                                  <STM32_PINMUX('D', 0, AF12)>, /* D02 */
 173                                  <STM32_PINMUX('D',15, AF12)>, /* D01 */
 174                                  <STM32_PINMUX('D',14, AF12)>, /* D00 */
 175
 176                                  <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
 177                                  <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
 178                                  <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
 179                                  <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
 180
 181                                  <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
 182                                  <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
 183
 184                                  <STM32_PINMUX('G', 1, AF12)>, /* A11 */
 185                                  <STM32_PINMUX('G', 0, AF12)>, /* A10 */
 186                                  <STM32_PINMUX('F',15, AF12)>, /* A09 */
 187                                  <STM32_PINMUX('F',14, AF12)>, /* A08 */
 188                                  <STM32_PINMUX('F',13, AF12)>, /* A07 */
 189                                  <STM32_PINMUX('F',12, AF12)>, /* A06 */
 190                                  <STM32_PINMUX('F', 5, AF12)>, /* A05 */
 191                                  <STM32_PINMUX('F', 4, AF12)>, /* A04 */
 192                                  <STM32_PINMUX('F', 3, AF12)>, /* A03 */
 193                                  <STM32_PINMUX('F', 2, AF12)>, /* A02 */
 194                                  <STM32_PINMUX('F', 1, AF12)>, /* A01 */
 195                                  <STM32_PINMUX('F', 0, AF12)>, /* A00 */
 196
 197                                  <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
 198                                  <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
 199                                  <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
 200                                  <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
 201                                  <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
 202                                  <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
 203                         slew-rate = <2>;
 204                         u-boot,dm-pre-reloc;
 205                 };
 206         };
 207
 208         usart3_pins_a: usart3@0 {
 209                 u-boot,dm-pre-reloc;
 210                 pins1 {
 211                         u-boot,dm-pre-reloc;
 212                 };
 213                 pins2 {
 214                         u-boot,dm-pre-reloc;
 215                 };
 216         };
 217 };
 218
 219 &pwrcfg {
 220         u-boot,dm-pre-reloc;
 221 };
 222
 223 &rcc {
 224         u-boot,dm-pre-reloc;
 225 };
 226
 227 &syscfg {
 228         u-boot,dm-pre-reloc;
 229 };