arch/arm/dts/stm32f429.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   4  *
   5  */
   6
   7 #include "armv7-m.dtsi"
   8 #include <dt-bindings/clock/stm32fx-clock.h>
   9 #include <dt-bindings/mfd/stm32f4-rcc.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         clocks {
  16                 clk_hse: clk-hse {
  17                         #clock-cells = <0>;
  18                         compatible = "fixed-clock";
  19                         clock-frequency = <0>;
  20                 };
  21
  22                 clk_lse: clk-lse {
  23                         #clock-cells = <0>;
  24                         compatible = "fixed-clock";
  25                         clock-frequency = <32768>;
  26                 };
  27
  28                 clk_lsi: clk-lsi {
  29                         #clock-cells = <0>;
  30                         compatible = "fixed-clock";
  31                         clock-frequency = <32000>;
  32                 };
  33
  34                 clk_i2s_ckin: i2s-ckin {
  35                         #clock-cells = <0>;
  36                         compatible = "fixed-clock";
  37                         clock-frequency = <0>;
  38                 };
  39         };
  40
  41         soc {
  42                 romem: nvmem@1fff7800 {
  43                         compatible = "st,stm32f4-otp";
  44                         reg = <0x1fff7800 0x400>;
  45                         #address-cells = <1>;
  46                         #size-cells = <1>;
  47                         ts_cal1: calib@22c {
  48                                 reg = <0x22c 0x2>;
  49                         };
  50                         ts_cal2: calib@22e {
  51                                 reg = <0x22e 0x2>;
  52                         };
  53                 };
  54
  55                 timer2: timer@40000000 {
  56                         compatible = "st,stm32-timer";
  57                         reg = <0x40000000 0x400>;
  58                         interrupts = <28>;
  59                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  60                         status = "disabled";
  61                 };
  62
  63                 timers2: timers@40000000 {
  64                         #address-cells = <1>;
  65                         #size-cells = <0>;
  66                         compatible = "st,stm32-timers";
  67                         reg = <0x40000000 0x400>;
  68                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  69                         clock-names = "int";
  70                         status = "disabled";
  71
  72                         pwm {
  73                                 compatible = "st,stm32-pwm";
  74                                 status = "disabled";
  75                         };
  76
  77                         timer@1 {
  78                                 compatible = "st,stm32-timer-trigger";
  79                                 reg = <1>;
  80                                 status = "disabled";
  81                         };
  82                 };
  83
  84                 timer3: timer@40000400 {
  85                         compatible = "st,stm32-timer";
  86                         reg = <0x40000400 0x400>;
  87                         interrupts = <29>;
  88                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
  89                         status = "disabled";
  90                 };
  91
  92                 timers3: timers@40000400 {
  93                         #address-cells = <1>;
  94                         #size-cells = <0>;
  95                         compatible = "st,stm32-timers";
  96                         reg = <0x40000400 0x400>;
  97                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
  98                         clock-names = "int";
  99                         status = "disabled";
 100
 101                         pwm {
 102                                 compatible = "st,stm32-pwm";
 103                                 status = "disabled";
 104                         };
 105
 106                         timer@2 {
 107                                 compatible = "st,stm32-timer-trigger";
 108                                 reg = <2>;
 109                                 status = "disabled";
 110                         };
 111                 };
 112
 113                 timer4: timer@40000800 {
 114                         compatible = "st,stm32-timer";
 115                         reg = <0x40000800 0x400>;
 116                         interrupts = <30>;
 117                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 118                         status = "disabled";
 119                 };
 120
 121                 timers4: timers@40000800 {
 122                         #address-cells = <1>;
 123                         #size-cells = <0>;
 124                         compatible = "st,stm32-timers";
 125                         reg = <0x40000800 0x400>;
 126                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 127                         clock-names = "int";
 128                         status = "disabled";
 129
 130                         pwm {
 131                                 compatible = "st,stm32-pwm";
 132                                 status = "disabled";
 133                         };
 134
 135                         timer@3 {
 136                                 compatible = "st,stm32-timer-trigger";
 137                                 reg = <3>;
 138                                 status = "disabled";
 139                         };
 140                 };
 141
 142                 timer5: timer@40000c00 {
 143                         compatible = "st,stm32-timer";
 144                         reg = <0x40000c00 0x400>;
 145                         interrupts = <50>;
 146                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 147                 };
 148
 149                 timers5: timers@40000c00 {
 150                         #address-cells = <1>;
 151                         #size-cells = <0>;
 152                         compatible = "st,stm32-timers";
 153                         reg = <0x40000C00 0x400>;
 154                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 155                         clock-names = "int";
 156                         status = "disabled";
 157
 158                         pwm {
 159                                 compatible = "st,stm32-pwm";
 160                                 status = "disabled";
 161                         };
 162
 163                         timer@4 {
 164                                 compatible = "st,stm32-timer-trigger";
 165                                 reg = <4>;
 166                                 status = "disabled";
 167                         };
 168                 };
 169
 170                 timer6: timer@40001000 {
 171                         compatible = "st,stm32-timer";
 172                         reg = <0x40001000 0x400>;
 173                         interrupts = <54>;
 174                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 175                         status = "disabled";
 176                 };
 177
 178                 timers6: timers@40001000 {
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181                         compatible = "st,stm32-timers";
 182                         reg = <0x40001000 0x400>;
 183                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 184                         clock-names = "int";
 185                         status = "disabled";
 186
 187                         timer@5 {
 188                                 compatible = "st,stm32-timer-trigger";
 189                                 reg = <5>;
 190                                 status = "disabled";
 191                         };
 192                 };
 193
 194                 timer7: timer@40001400 {
 195                         compatible = "st,stm32-timer";
 196                         reg = <0x40001400 0x400>;
 197                         interrupts = <55>;
 198                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 199                         status = "disabled";
 200                 };
 201
 202                 timers7: timers@40001400 {
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                         compatible = "st,stm32-timers";
 206                         reg = <0x40001400 0x400>;
 207                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 208                         clock-names = "int";
 209                         status = "disabled";
 210
 211                         timer@6 {
 212                                 compatible = "st,stm32-timer-trigger";
 213                                 reg = <6>;
 214                                 status = "disabled";
 215                         };
 216                 };
 217
 218                 timers12: timers@40001800 {
 219                         #address-cells = <1>;
 220                         #size-cells = <0>;
 221                         compatible = "st,stm32-timers";
 222                         reg = <0x40001800 0x400>;
 223                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
 224                         clock-names = "int";
 225                         status = "disabled";
 226
 227                         pwm {
 228                                 compatible = "st,stm32-pwm";
 229                                 status = "disabled";
 230                         };
 231
 232                         timer@11 {
 233                                 compatible = "st,stm32-timer-trigger";
 234                                 reg = <11>;
 235                                 status = "disabled";
 236                         };
 237                 };
 238
 239                 timers13: timers@40001c00 {
 240                         #address-cells = <1>;
 241                         #size-cells = <0>;
 242                         compatible = "st,stm32-timers";
 243                         reg = <0x40001C00 0x400>;
 244                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
 245                         clock-names = "int";
 246                         status = "disabled";
 247
 248                         pwm {
 249                                 compatible = "st,stm32-pwm";
 250                                 status = "disabled";
 251                         };
 252                 };
 253
 254                 timers14: timers@40002000 {
 255                         #address-cells = <1>;
 256                         #size-cells = <0>;
 257                         compatible = "st,stm32-timers";
 258                         reg = <0x40002000 0x400>;
 259                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
 260                         clock-names = "int";
 261                         status = "disabled";
 262
 263                         pwm {
 264                                 compatible = "st,stm32-pwm";
 265                                 status = "disabled";
 266                         };
 267                 };
 268
 269                 rtc: rtc@40002800 {
 270                         compatible = "st,stm32-rtc";
 271                         reg = <0x40002800 0x400>;
 272                         clocks = <&rcc 1 CLK_RTC>;
 273                         clock-names = "ck_rtc";
 274                         assigned-clocks = <&rcc 1 CLK_RTC>;
 275                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 276                         interrupt-parent = <&exti>;
 277                         interrupts = <17 1>;
 278                         interrupt-names = "alarm";
 279                         st,syscfg = <&pwrcfg 0x00 0x100>;
 280                         status = "disabled";
 281                 };
 282
 283                 iwdg: watchdog@40003000 {
 284                         compatible = "st,stm32-iwdg";
 285                         reg = <0x40003000 0x400>;
 286                         clocks = <&clk_lsi>;
 287                         clock-names = "lsi";
 288                         status = "disabled";
 289                 };
 290
 291                 spi2: spi@40003800 {
 292                         #address-cells = <1>;
 293                         #size-cells = <0>;
 294                         compatible = "st,stm32f4-spi";
 295                         reg = <0x40003800 0x400>;
 296                         interrupts = <36>;
 297                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
 298                         status = "disabled";
 299                 };
 300
 301                 spi3: spi@40003c00 {
 302                         #address-cells = <1>;
 303                         #size-cells = <0>;
 304                         compatible = "st,stm32f4-spi";
 305                         reg = <0x40003c00 0x400>;
 306                         interrupts = <51>;
 307                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
 308                         status = "disabled";
 309                 };
 310
 311                 usart2: serial@40004400 {
 312                         compatible = "st,stm32-uart";
 313                         reg = <0x40004400 0x400>;
 314                         interrupts = <38>;
 315                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
 316                         status = "disabled";
 317                 };
 318
 319                 usart3: serial@40004800 {
 320                         compatible = "st,stm32-uart";
 321                         reg = <0x40004800 0x400>;
 322                         interrupts = <39>;
 323                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
 324                         status = "disabled";
 325                         dmas = <&dma1 1 4 0x400 0x0>,
 326                                <&dma1 3 4 0x400 0x0>;
 327                         dma-names = "rx", "tx";
 328                 };
 329
 330                 usart4: serial@40004c00 {
 331                         compatible = "st,stm32-uart";
 332                         reg = <0x40004c00 0x400>;
 333                         interrupts = <52>;
 334                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
 335                         status = "disabled";
 336                 };
 337
 338                 usart5: serial@40005000 {
 339                         compatible = "st,stm32-uart";
 340                         reg = <0x40005000 0x400>;
 341                         interrupts = <53>;
 342                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
 343                         status = "disabled";
 344                 };
 345
 346                 i2c1: i2c@40005400 {
 347                         compatible = "st,stm32f4-i2c";
 348                         reg = <0x40005400 0x400>;
 349                         interrupts = <31>,
 350                                      <32>;
 351                         resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
 352                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355                         status = "disabled";
 356                 };
 357
 358                 dac: dac@40007400 {
 359                         compatible = "st,stm32f4-dac-core";
 360                         reg = <0x40007400 0x400>;
 361                         resets = <&rcc STM32F4_APB1_RESET(DAC)>;
 362                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
 363                         clock-names = "pclk";
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                         status = "disabled";
 367
 368                         dac1: dac@1 {
 369                                 compatible = "st,stm32-dac";
 370                                 #io-channels-cells = <1>;
 371                                 reg = <1>;
 372                                 status = "disabled";
 373                         };
 374
 375                         dac2: dac@2 {
 376                                 compatible = "st,stm32-dac";
 377                                 #io-channels-cells = <1>;
 378                                 reg = <2>;
 379                                 status = "disabled";
 380                         };
 381                 };
 382
 383                 usart7: serial@40007800 {
 384                         compatible = "st,stm32-uart";
 385                         reg = <0x40007800 0x400>;
 386                         interrupts = <82>;
 387                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
 388                         status = "disabled";
 389                 };
 390
 391                 usart8: serial@40007c00 {
 392                         compatible = "st,stm32-uart";
 393                         reg = <0x40007c00 0x400>;
 394                         interrupts = <83>;
 395                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
 396                         status = "disabled";
 397                 };
 398
 399                 timers1: timers@40010000 {
 400                         #address-cells = <1>;
 401                         #size-cells = <0>;
 402                         compatible = "st,stm32-timers";
 403                         reg = <0x40010000 0x400>;
 404                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
 405                         clock-names = "int";
 406                         status = "disabled";
 407
 408                         pwm {
 409                                 compatible = "st,stm32-pwm";
 410                                 status = "disabled";
 411                         };
 412
 413                         timer@0 {
 414                                 compatible = "st,stm32-timer-trigger";
 415                                 reg = <0>;
 416                                 status = "disabled";
 417                         };
 418                 };
 419
 420                 timers8: timers@40010400 {
 421                         #address-cells = <1>;
 422                         #size-cells = <0>;
 423                         compatible = "st,stm32-timers";
 424                         reg = <0x40010400 0x400>;
 425                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
 426                         clock-names = "int";
 427                         status = "disabled";
 428
 429                         pwm {
 430                                 compatible = "st,stm32-pwm";
 431                                 status = "disabled";
 432                         };
 433
 434                         timer@7 {
 435                                 compatible = "st,stm32-timer-trigger";
 436                                 reg = <7>;
 437                                 status = "disabled";
 438                         };
 439                 };
 440
 441                 usart1: serial@40011000 {
 442                         compatible = "st,stm32-uart";
 443                         reg = <0x40011000 0x400>;
 444                         interrupts = <37>;
 445                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
 446                         status = "disabled";
 447                         dmas = <&dma2 2 4 0x400 0x0>,
 448                                <&dma2 7 4 0x400 0x0>;
 449                         dma-names = "rx", "tx";
 450                 };
 451
 452                 usart6: serial@40011400 {
 453                         compatible = "st,stm32-uart";
 454                         reg = <0x40011400 0x400>;
 455                         interrupts = <71>;
 456                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
 457                         status = "disabled";
 458                 };
 459
 460                 adc: adc@40012000 {
 461                         compatible = "st,stm32f4-adc-core";
 462                         reg = <0x40012000 0x400>;
 463                         interrupts = <18>;
 464                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 465                         clock-names = "adc";
 466                         interrupt-controller;
 467                         #interrupt-cells = <1>;
 468                         #address-cells = <1>;
 469                         #size-cells = <0>;
 470                         status = "disabled";
 471
 472                         adc1: adc@0 {
 473                                 compatible = "st,stm32f4-adc";
 474                                 #io-channel-cells = <1>;
 475                                 reg = <0x0>;
 476                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 477                                 interrupt-parent = <&adc>;
 478                                 interrupts = <0>;
 479                                 dmas = <&dma2 0 0 0x400 0x0>;
 480                                 dma-names = "rx";
 481                                 status = "disabled";
 482                         };
 483
 484                         adc2: adc@100 {
 485                                 compatible = "st,stm32f4-adc";
 486                                 #io-channel-cells = <1>;
 487                                 reg = <0x100>;
 488                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
 489                                 interrupt-parent = <&adc>;
 490                                 interrupts = <1>;
 491                                 dmas = <&dma2 3 1 0x400 0x0>;
 492                                 dma-names = "rx";
 493                                 status = "disabled";
 494                         };
 495
 496                         adc3: adc@200 {
 497                                 compatible = "st,stm32f4-adc";
 498                                 #io-channel-cells = <1>;
 499                                 reg = <0x200>;
 500                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
 501                                 interrupt-parent = <&adc>;
 502                                 interrupts = <2>;
 503                                 dmas = <&dma2 1 2 0x400 0x0>;
 504                                 dma-names = "rx";
 505                                 status = "disabled";
 506                         };
 507                 };
 508
 509                 sdio: sdio@40012c00 {
 510                         compatible = "arm,pl180", "arm,primecell";
 511                         arm,primecell-periphid = <0x00880180>;
 512                         reg = <0x40012c00 0x400>;
 513                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
 514                         clock-names = "apb_pclk";
 515                         interrupts = <49>;
 516                         max-frequency = <48000000>;
 517                         status = "disabled";
 518                 };
 519
 520                 spi1: spi@40013000 {
 521                         #address-cells = <1>;
 522                         #size-cells = <0>;
 523                         compatible = "st,stm32f4-spi";
 524                         reg = <0x40013000 0x400>;
 525                         interrupts = <35>;
 526                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
 527                         status = "disabled";
 528                 };
 529
 530                 spi4: spi@40013400 {
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                         compatible = "st,stm32f4-spi";
 534                         reg = <0x40013400 0x400>;
 535                         interrupts = <84>;
 536                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
 537                         status = "disabled";
 538                 };
 539
 540                 syscfg: system-config@40013800 {
 541                         compatible = "syscon";
 542                         reg = <0x40013800 0x400>;
 543                 };
 544
 545                 exti: interrupt-controller@40013c00 {
 546                         compatible = "st,stm32-exti";
 547                         interrupt-controller;
 548                         #interrupt-cells = <2>;
 549                         reg = <0x40013C00 0x400>;
 550                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 551                 };
 552
 553                 timers9: timers@40014000 {
 554                         #address-cells = <1>;
 555                         #size-cells = <0>;
 556                         compatible = "st,stm32-timers";
 557                         reg = <0x40014000 0x400>;
 558                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
 559                         clock-names = "int";
 560                         status = "disabled";
 561
 562                         pwm {
 563                                 compatible = "st,stm32-pwm";
 564                                 status = "disabled";
 565                         };
 566
 567                         timer@8 {
 568                                 compatible = "st,stm32-timer-trigger";
 569                                 reg = <8>;
 570                                 status = "disabled";
 571                         };
 572                 };
 573
 574                 timers10: timers@40014400 {
 575                         #address-cells = <1>;
 576                         #size-cells = <0>;
 577                         compatible = "st,stm32-timers";
 578                         reg = <0x40014400 0x400>;
 579                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
 580                         clock-names = "int";
 581                         status = "disabled";
 582
 583                         pwm {
 584                                 compatible = "st,stm32-pwm";
 585                                 status = "disabled";
 586                         };
 587                 };
 588
 589                 timers11: timers@40014800 {
 590                         #address-cells = <1>;
 591                         #size-cells = <0>;
 592                         compatible = "st,stm32-timers";
 593                         reg = <0x40014800 0x400>;
 594                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
 595                         clock-names = "int";
 596                         status = "disabled";
 597
 598                         pwm {
 599                                 compatible = "st,stm32-pwm";
 600                                 status = "disabled";
 601                         };
 602                 };
 603
 604                 spi5: spi@40015000 {
 605                         #address-cells = <1>;
 606                         #size-cells = <0>;
 607                         compatible = "st,stm32f4-spi";
 608                         reg = <0x40015000 0x400>;
 609                         interrupts = <85>;
 610                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
 611                         status = "disabled";
 612                 };
 613
 614                 spi6: spi@40015400 {
 615                         #address-cells = <1>;
 616                         #size-cells = <0>;
 617                         compatible = "st,stm32f4-spi";
 618                         reg = <0x40015400 0x400>;
 619                         interrupts = <86>;
 620                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
 621                         status = "disabled";
 622                 };
 623
 624                 pwrcfg: power-config@40007000 {
 625                         compatible = "syscon";
 626                         reg = <0x40007000 0x400>;
 627                 };
 628
 629                 ltdc: display-controller@40016800 {
 630                         compatible = "st,stm32-ltdc";
 631                         reg = <0x40016800 0x200>;
 632                         interrupts = <88>, <89>;
 633                         resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
 634                         clocks = <&rcc 1 CLK_LCD>;
 635                         clock-names = "lcd";
 636                         status = "disabled";
 637                 };
 638
 639                 crc: crc@40023000 {
 640                         compatible = "st,stm32f4-crc";
 641                         reg = <0x40023000 0x400>;
 642                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
 643                         status = "disabled";
 644                 };
 645
 646                 rcc: rcc@40023810 {
 647                         #reset-cells = <1>;
 648                         #clock-cells = <2>;
 649                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 650                         reg = <0x40023800 0x400>;
 651                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 652                         st,syscfg = <&pwrcfg>;
 653                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 654                         assigned-clock-rates = <1000000>;
 655                 };
 656
 657                 dma1: dma-controller@40026000 {
 658                         compatible = "st,stm32-dma";
 659                         reg = <0x40026000 0x400>;
 660                         interrupts = <11>,
 661                                      <12>,
 662                                      <13>,
 663                                      <14>,
 664                                      <15>,
 665                                      <16>,
 666                                      <17>,
 667                                      <47>;
 668                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
 669                         #dma-cells = <4>;
 670                 };
 671
 672                 dma2: dma-controller@40026400 {
 673                         compatible = "st,stm32-dma";
 674                         reg = <0x40026400 0x400>;
 675                         interrupts = <56>,
 676                                      <57>,
 677                                      <58>,
 678                                      <59>,
 679                                      <60>,
 680                                      <68>,
 681                                      <69>,
 682                                      <70>;
 683                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
 684                         #dma-cells = <4>;
 685                         st,mem2mem;
 686                 };
 687
 688                 mac: ethernet@40028000 {
 689                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 690                         reg = <0x40028000 0x8000>;
 691                         reg-names = "stmmaceth";
 692                         interrupts = <61>;
 693                         interrupt-names = "macirq";
 694                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 695                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
 696                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
 697                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
 698                         st,syscon = <&syscfg 0x4>;
 699                         snps,pbl = <8>;
 700                         snps,mixed-burst;
 701                         status = "disabled";
 702                 };
 703
 704                 usbotg_hs: usb@40040000 {
 705                         compatible = "snps,dwc2";
 706                         reg = <0x40040000 0x40000>;
 707                         interrupts = <77>;
 708                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
 709                         clock-names = "otg";
 710                         status = "disabled";
 711                 };
 712
 713                 usbotg_fs: usb@50000000 {
 714                         compatible = "st,stm32f4x9-fsotg";
 715                         reg = <0x50000000 0x40000>;
 716                         interrupts = <67>;
 717                         clocks = <&rcc 0 39>;
 718                         clock-names = "otg";
 719                         status = "disabled";
 720                 };
 721
 722                 dcmi: dcmi@50050000 {
 723                         compatible = "st,stm32-dcmi";
 724                         reg = <0x50050000 0x400>;
 725                         interrupts = <78>;
 726                         resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
 727                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
 728                         clock-names = "mclk";
 729                         pinctrl-names = "default";
 730                         pinctrl-0 = <&dcmi_pins>;
 731                         dmas = <&dma2 1 1 0x414 0x3>;
 732                         dma-names = "tx";
 733                         status = "disabled";
 734                 };
 735
 736                 rng: rng@50060800 {
 737                         compatible = "st,stm32-rng";
 738                         reg = <0x50060800 0x400>;
 739                         interrupts = <80>;
 740                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
 741
 742                 };
 743         };
 744 };
 745
 746 &systick {
 747         clocks = <&rcc 1 SYSTICK>;
 748         status = "okay";
 749 };