arch/arm/dts/stm32f429.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   4  *
   5  */
   6
   7 #include "armv7-m.dtsi"
   8 #include <dt-bindings/clock/stm32fx-clock.h>
   9 #include <dt-bindings/mfd/stm32f4-rcc.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         clocks {
  16                 clk_hse: clk-hse {
  17                         #clock-cells = <0>;
  18                         compatible = "fixed-clock";
  19                         clock-frequency = <0>;
  20                 };
  21
  22                 clk_lse: clk-lse {
  23                         #clock-cells = <0>;
  24                         compatible = "fixed-clock";
  25                         clock-frequency = <32768>;
  26                 };
  27
  28                 clk_lsi: clk-lsi {
  29                         #clock-cells = <0>;
  30                         compatible = "fixed-clock";
  31                         clock-frequency = <32000>;
  32                 };
  33
  34                 clk_i2s_ckin: i2s-ckin {
  35                         #clock-cells = <0>;
  36                         compatible = "fixed-clock";
  37                         clock-frequency = <0>;
  38                 };
  39         };
  40
  41         soc {
  42                 romem: efuse@1fff7800 {
  43                         compatible = "st,stm32f4-otp";
  44                         reg = <0x1fff7800 0x400>;
  45                         #address-cells = <1>;
  46                         #size-cells = <1>;
  47                         ts_cal1: calib@22c {
  48                                 reg = <0x22c 0x2>;
  49                         };
  50                         ts_cal2: calib@22e {
  51                                 reg = <0x22e 0x2>;
  52                         };
  53                 };
  54
  55                 timers2: timers@40000000 {
  56                         #address-cells = <1>;
  57                         #size-cells = <0>;
  58                         compatible = "st,stm32-timers";
  59                         reg = <0x40000000 0x400>;
  60                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  61                         clock-names = "int";
  62                         status = "disabled";
  63
  64                         pwm {
  65                                 compatible = "st,stm32-pwm";
  66                                 #pwm-cells = <3>;
  67                                 status = "disabled";
  68                         };
  69
  70                         timer@1 {
  71                                 compatible = "st,stm32-timer-trigger";
  72                                 reg = <1>;
  73                                 status = "disabled";
  74                         };
  75                 };
  76
  77                 timers3: timers@40000400 {
  78                         #address-cells = <1>;
  79                         #size-cells = <0>;
  80                         compatible = "st,stm32-timers";
  81                         reg = <0x40000400 0x400>;
  82                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
  83                         clock-names = "int";
  84                         status = "disabled";
  85
  86                         pwm {
  87                                 compatible = "st,stm32-pwm";
  88                                 #pwm-cells = <3>;
  89                                 status = "disabled";
  90                         };
  91
  92                         timer@2 {
  93                                 compatible = "st,stm32-timer-trigger";
  94                                 reg = <2>;
  95                                 status = "disabled";
  96                         };
  97                 };
  98
  99                 timers4: timers@40000800 {
 100                         #address-cells = <1>;
 101                         #size-cells = <0>;
 102                         compatible = "st,stm32-timers";
 103                         reg = <0x40000800 0x400>;
 104                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 105                         clock-names = "int";
 106                         status = "disabled";
 107
 108                         pwm {
 109                                 compatible = "st,stm32-pwm";
 110                                 #pwm-cells = <3>;
 111                                 status = "disabled";
 112                         };
 113
 114                         timer@3 {
 115                                 compatible = "st,stm32-timer-trigger";
 116                                 reg = <3>;
 117                                 status = "disabled";
 118                         };
 119                 };
 120
 121                 timers5: timers@40000c00 {
 122                         #address-cells = <1>;
 123                         #size-cells = <0>;
 124                         compatible = "st,stm32-timers";
 125                         reg = <0x40000C00 0x400>;
 126                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 127                         clock-names = "int";
 128                         status = "disabled";
 129
 130                         pwm {
 131                                 compatible = "st,stm32-pwm";
 132                                 #pwm-cells = <3>;
 133                                 status = "disabled";
 134                         };
 135
 136                         timer@4 {
 137                                 compatible = "st,stm32-timer-trigger";
 138                                 reg = <4>;
 139                                 status = "disabled";
 140                         };
 141                 };
 142
 143                 timers6: timers@40001000 {
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         compatible = "st,stm32-timers";
 147                         reg = <0x40001000 0x400>;
 148                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 149                         clock-names = "int";
 150                         status = "disabled";
 151
 152                         timer@5 {
 153                                 compatible = "st,stm32-timer-trigger";
 154                                 reg = <5>;
 155                                 status = "disabled";
 156                         };
 157                 };
 158
 159                 timers7: timers@40001400 {
 160                         #address-cells = <1>;
 161                         #size-cells = <0>;
 162                         compatible = "st,stm32-timers";
 163                         reg = <0x40001400 0x400>;
 164                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 165                         clock-names = "int";
 166                         status = "disabled";
 167
 168                         timer@6 {
 169                                 compatible = "st,stm32-timer-trigger";
 170                                 reg = <6>;
 171                                 status = "disabled";
 172                         };
 173                 };
 174
 175                 timers12: timers@40001800 {
 176                         #address-cells = <1>;
 177                         #size-cells = <0>;
 178                         compatible = "st,stm32-timers";
 179                         reg = <0x40001800 0x400>;
 180                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
 181                         clock-names = "int";
 182                         status = "disabled";
 183
 184                         pwm {
 185                                 compatible = "st,stm32-pwm";
 186                                 #pwm-cells = <3>;
 187                                 status = "disabled";
 188                         };
 189
 190                         timer@11 {
 191                                 compatible = "st,stm32-timer-trigger";
 192                                 reg = <11>;
 193                                 status = "disabled";
 194                         };
 195                 };
 196
 197                 timers13: timers@40001c00 {
 198                         compatible = "st,stm32-timers";
 199                         reg = <0x40001C00 0x400>;
 200                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
 201                         clock-names = "int";
 202                         status = "disabled";
 203
 204                         pwm {
 205                                 compatible = "st,stm32-pwm";
 206                                 #pwm-cells = <3>;
 207                                 status = "disabled";
 208                         };
 209                 };
 210
 211                 timers14: timers@40002000 {
 212                         compatible = "st,stm32-timers";
 213                         reg = <0x40002000 0x400>;
 214                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
 215                         clock-names = "int";
 216                         status = "disabled";
 217
 218                         pwm {
 219                                 compatible = "st,stm32-pwm";
 220                                 #pwm-cells = <3>;
 221                                 status = "disabled";
 222                         };
 223                 };
 224
 225                 rtc: rtc@40002800 {
 226                         compatible = "st,stm32-rtc";
 227                         reg = <0x40002800 0x400>;
 228                         clocks = <&rcc 1 CLK_RTC>;
 229                         assigned-clocks = <&rcc 1 CLK_RTC>;
 230                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 231                         interrupt-parent = <&exti>;
 232                         interrupts = <17 1>;
 233                         st,syscfg = <&pwrcfg 0x00 0x100>;
 234                         status = "disabled";
 235                 };
 236
 237                 iwdg: watchdog@40003000 {
 238                         compatible = "st,stm32-iwdg";
 239                         reg = <0x40003000 0x400>;
 240                         clocks = <&clk_lsi>;
 241                         clock-names = "lsi";
 242                         status = "disabled";
 243                 };
 244
 245                 spi2: spi@40003800 {
 246                         #address-cells = <1>;
 247                         #size-cells = <0>;
 248                         compatible = "st,stm32f4-spi";
 249                         reg = <0x40003800 0x400>;
 250                         interrupts = <36>;
 251                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
 252                         status = "disabled";
 253                 };
 254
 255                 spi3: spi@40003c00 {
 256                         #address-cells = <1>;
 257                         #size-cells = <0>;
 258                         compatible = "st,stm32f4-spi";
 259                         reg = <0x40003c00 0x400>;
 260                         interrupts = <51>;
 261                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
 262                         status = "disabled";
 263                 };
 264
 265                 usart2: serial@40004400 {
 266                         compatible = "st,stm32-uart";
 267                         reg = <0x40004400 0x400>;
 268                         interrupts = <38>;
 269                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
 270                         status = "disabled";
 271                 };
 272
 273                 usart3: serial@40004800 {
 274                         compatible = "st,stm32-uart";
 275                         reg = <0x40004800 0x400>;
 276                         interrupts = <39>;
 277                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
 278                         status = "disabled";
 279                         dmas = <&dma1 1 4 0x400 0x0>,
 280                                <&dma1 3 4 0x400 0x0>;
 281                         dma-names = "rx", "tx";
 282                 };
 283
 284                 usart4: serial@40004c00 {
 285                         compatible = "st,stm32-uart";
 286                         reg = <0x40004c00 0x400>;
 287                         interrupts = <52>;
 288                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
 289                         status = "disabled";
 290                 };
 291
 292                 usart5: serial@40005000 {
 293                         compatible = "st,stm32-uart";
 294                         reg = <0x40005000 0x400>;
 295                         interrupts = <53>;
 296                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
 297                         status = "disabled";
 298                 };
 299
 300                 i2c1: i2c@40005400 {
 301                         compatible = "st,stm32f4-i2c";
 302                         reg = <0x40005400 0x400>;
 303                         interrupts = <31>,
 304                                      <32>;
 305                         resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
 306                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
 307                         #address-cells = <1>;
 308                         #size-cells = <0>;
 309                         status = "disabled";
 310                 };
 311
 312                 i2c3: i2c@40005c00 {
 313                         compatible = "st,stm32f4-i2c";
 314                         reg = <0x40005c00 0x400>;
 315                         interrupts = <72>,
 316                                      <73>;
 317                         resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
 318                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
 319                         #address-cells = <1>;
 320                         #size-cells = <0>;
 321                         status = "disabled";
 322                 };
 323
 324                 dac: dac@40007400 {
 325                         compatible = "st,stm32f4-dac-core";
 326                         reg = <0x40007400 0x400>;
 327                         resets = <&rcc STM32F4_APB1_RESET(DAC)>;
 328                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
 329                         clock-names = "pclk";
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         status = "disabled";
 333
 334                         dac1: dac@1 {
 335                                 compatible = "st,stm32-dac";
 336                                 #io-channel-cells = <1>;
 337                                 reg = <1>;
 338                                 status = "disabled";
 339                         };
 340
 341                         dac2: dac@2 {
 342                                 compatible = "st,stm32-dac";
 343                                 #io-channel-cells = <1>;
 344                                 reg = <2>;
 345                                 status = "disabled";
 346                         };
 347                 };
 348
 349                 usart7: serial@40007800 {
 350                         compatible = "st,stm32-uart";
 351                         reg = <0x40007800 0x400>;
 352                         interrupts = <82>;
 353                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
 354                         status = "disabled";
 355                 };
 356
 357                 usart8: serial@40007c00 {
 358                         compatible = "st,stm32-uart";
 359                         reg = <0x40007c00 0x400>;
 360                         interrupts = <83>;
 361                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
 362                         status = "disabled";
 363                 };
 364
 365                 timers1: timers@40010000 {
 366                         #address-cells = <1>;
 367                         #size-cells = <0>;
 368                         compatible = "st,stm32-timers";
 369                         reg = <0x40010000 0x400>;
 370                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
 371                         clock-names = "int";
 372                         status = "disabled";
 373
 374                         pwm {
 375                                 compatible = "st,stm32-pwm";
 376                                 #pwm-cells = <3>;
 377                                 status = "disabled";
 378                         };
 379
 380                         timer@0 {
 381                                 compatible = "st,stm32-timer-trigger";
 382                                 reg = <0>;
 383                                 status = "disabled";
 384                         };
 385                 };
 386
 387                 timers8: timers@40010400 {
 388                         #address-cells = <1>;
 389                         #size-cells = <0>;
 390                         compatible = "st,stm32-timers";
 391                         reg = <0x40010400 0x400>;
 392                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
 393                         clock-names = "int";
 394                         status = "disabled";
 395
 396                         pwm {
 397                                 compatible = "st,stm32-pwm";
 398                                 #pwm-cells = <3>;
 399                                 status = "disabled";
 400                         };
 401
 402                         timer@7 {
 403                                 compatible = "st,stm32-timer-trigger";
 404                                 reg = <7>;
 405                                 status = "disabled";
 406                         };
 407                 };
 408
 409                 usart1: serial@40011000 {
 410                         compatible = "st,stm32-uart";
 411                         reg = <0x40011000 0x400>;
 412                         interrupts = <37>;
 413                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
 414                         status = "disabled";
 415                         dmas = <&dma2 2 4 0x400 0x0>,
 416                                <&dma2 7 4 0x400 0x0>;
 417                         dma-names = "rx", "tx";
 418                 };
 419
 420                 usart6: serial@40011400 {
 421                         compatible = "st,stm32-uart";
 422                         reg = <0x40011400 0x400>;
 423                         interrupts = <71>;
 424                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
 425                         status = "disabled";
 426                 };
 427
 428                 adc: adc@40012000 {
 429                         compatible = "st,stm32f4-adc-core";
 430                         reg = <0x40012000 0x400>;
 431                         interrupts = <18>;
 432                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 433                         clock-names = "adc";
 434                         interrupt-controller;
 435                         #interrupt-cells = <1>;
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438                         status = "disabled";
 439
 440                         adc1: adc@0 {
 441                                 compatible = "st,stm32f4-adc";
 442                                 #io-channel-cells = <1>;
 443                                 reg = <0x0>;
 444                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 445                                 interrupt-parent = <&adc>;
 446                                 interrupts = <0>;
 447                                 dmas = <&dma2 0 0 0x400 0x0>;
 448                                 dma-names = "rx";
 449                                 status = "disabled";
 450                         };
 451
 452                         adc2: adc@100 {
 453                                 compatible = "st,stm32f4-adc";
 454                                 #io-channel-cells = <1>;
 455                                 reg = <0x100>;
 456                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
 457                                 interrupt-parent = <&adc>;
 458                                 interrupts = <1>;
 459                                 dmas = <&dma2 3 1 0x400 0x0>;
 460                                 dma-names = "rx";
 461                                 status = "disabled";
 462                         };
 463
 464                         adc3: adc@200 {
 465                                 compatible = "st,stm32f4-adc";
 466                                 #io-channel-cells = <1>;
 467                                 reg = <0x200>;
 468                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
 469                                 interrupt-parent = <&adc>;
 470                                 interrupts = <2>;
 471                                 dmas = <&dma2 1 2 0x400 0x0>;
 472                                 dma-names = "rx";
 473                                 status = "disabled";
 474                         };
 475                 };
 476
 477                 sdio: mmc@40012c00 {
 478                         compatible = "arm,pl180", "arm,primecell";
 479                         arm,primecell-periphid = <0x00880180>;
 480                         reg = <0x40012c00 0x400>;
 481                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
 482                         clock-names = "apb_pclk";
 483                         interrupts = <49>;
 484                         max-frequency = <48000000>;
 485                         status = "disabled";
 486                 };
 487
 488                 spi1: spi@40013000 {
 489                         #address-cells = <1>;
 490                         #size-cells = <0>;
 491                         compatible = "st,stm32f4-spi";
 492                         reg = <0x40013000 0x400>;
 493                         interrupts = <35>;
 494                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
 495                         status = "disabled";
 496                 };
 497
 498                 spi4: spi@40013400 {
 499                         #address-cells = <1>;
 500                         #size-cells = <0>;
 501                         compatible = "st,stm32f4-spi";
 502                         reg = <0x40013400 0x400>;
 503                         interrupts = <84>;
 504                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
 505                         status = "disabled";
 506                 };
 507
 508                 syscfg: syscon@40013800 {
 509                         compatible = "st,stm32-syscfg", "syscon";
 510                         reg = <0x40013800 0x400>;
 511                 };
 512
 513                 exti: interrupt-controller@40013c00 {
 514                         compatible = "st,stm32-exti";
 515                         interrupt-controller;
 516                         #interrupt-cells = <2>;
 517                         reg = <0x40013C00 0x400>;
 518                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 519                 };
 520
 521                 timers9: timers@40014000 {
 522                         #address-cells = <1>;
 523                         #size-cells = <0>;
 524                         compatible = "st,stm32-timers";
 525                         reg = <0x40014000 0x400>;
 526                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
 527                         clock-names = "int";
 528                         status = "disabled";
 529
 530                         pwm {
 531                                 compatible = "st,stm32-pwm";
 532                                 #pwm-cells = <3>;
 533                                 status = "disabled";
 534                         };
 535
 536                         timer@8 {
 537                                 compatible = "st,stm32-timer-trigger";
 538                                 reg = <8>;
 539                                 status = "disabled";
 540                         };
 541                 };
 542
 543                 timers10: timers@40014400 {
 544                         compatible = "st,stm32-timers";
 545                         reg = <0x40014400 0x400>;
 546                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
 547                         clock-names = "int";
 548                         status = "disabled";
 549
 550                         pwm {
 551                                 compatible = "st,stm32-pwm";
 552                                 #pwm-cells = <3>;
 553                                 status = "disabled";
 554                         };
 555                 };
 556
 557                 timers11: timers@40014800 {
 558                         compatible = "st,stm32-timers";
 559                         reg = <0x40014800 0x400>;
 560                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
 561                         clock-names = "int";
 562                         status = "disabled";
 563
 564                         pwm {
 565                                 compatible = "st,stm32-pwm";
 566                                 #pwm-cells = <3>;
 567                                 status = "disabled";
 568                         };
 569                 };
 570
 571                 spi5: spi@40015000 {
 572                         #address-cells = <1>;
 573                         #size-cells = <0>;
 574                         compatible = "st,stm32f4-spi";
 575                         reg = <0x40015000 0x400>;
 576                         interrupts = <85>;
 577                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
 578                         dmas = <&dma2 3 2 0x400 0x0>,
 579                                 <&dma2 4 2 0x400 0x0>;
 580                         dma-names = "rx", "tx";
 581                         status = "disabled";
 582                 };
 583
 584                 spi6: spi@40015400 {
 585                         #address-cells = <1>;
 586                         #size-cells = <0>;
 587                         compatible = "st,stm32f4-spi";
 588                         reg = <0x40015400 0x400>;
 589                         interrupts = <86>;
 590                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
 591                         status = "disabled";
 592                 };
 593
 594                 pwrcfg: power-config@40007000 {
 595                         compatible = "st,stm32-power-config", "syscon";
 596                         reg = <0x40007000 0x400>;
 597                 };
 598
 599                 ltdc: display-controller@40016800 {
 600                         compatible = "st,stm32-ltdc";
 601                         reg = <0x40016800 0x200>;
 602                         interrupts = <88>, <89>;
 603                         resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
 604                         clocks = <&rcc 1 CLK_LCD>;
 605                         clock-names = "lcd";
 606                         status = "disabled";
 607                 };
 608
 609                 crc: crc@40023000 {
 610                         compatible = "st,stm32f4-crc";
 611                         reg = <0x40023000 0x400>;
 612                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
 613                         status = "disabled";
 614                 };
 615
 616                 rcc: rcc@40023800 {
 617                         #reset-cells = <1>;
 618                         #clock-cells = <2>;
 619                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 620                         reg = <0x40023800 0x400>;
 621                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 622                         st,syscfg = <&pwrcfg>;
 623                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 624                         assigned-clock-rates = <1000000>;
 625                 };
 626
 627                 dma1: dma-controller@40026000 {
 628                         compatible = "st,stm32-dma";
 629                         reg = <0x40026000 0x400>;
 630                         interrupts = <11>,
 631                                      <12>,
 632                                      <13>,
 633                                      <14>,
 634                                      <15>,
 635                                      <16>,
 636                                      <17>,
 637                                      <47>;
 638                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
 639                         #dma-cells = <4>;
 640                 };
 641
 642                 dma2: dma-controller@40026400 {
 643                         compatible = "st,stm32-dma";
 644                         reg = <0x40026400 0x400>;
 645                         interrupts = <56>,
 646                                      <57>,
 647                                      <58>,
 648                                      <59>,
 649                                      <60>,
 650                                      <68>,
 651                                      <69>,
 652                                      <70>;
 653                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
 654                         #dma-cells = <4>;
 655                         st,mem2mem;
 656                 };
 657
 658                 mac: ethernet@40028000 {
 659                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 660                         reg = <0x40028000 0x8000>;
 661                         reg-names = "stmmaceth";
 662                         interrupts = <61>;
 663                         interrupt-names = "macirq";
 664                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 665                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
 666                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
 667                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
 668                         st,syscon = <&syscfg 0x4>;
 669                         snps,pbl = <8>;
 670                         snps,mixed-burst;
 671                         status = "disabled";
 672                 };
 673
 674                 dma2d: dma2d@4002b000 {
 675                         compatible = "st,stm32-dma2d";
 676                         reg = <0x4002b000 0xc00>;
 677                         interrupts = <90>;
 678                         resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
 679                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
 680                         clock-names = "dma2d";
 681                         status = "disabled";
 682                 };
 683
 684                 usbotg_hs: usb@40040000 {
 685                         compatible = "snps,dwc2";
 686                         reg = <0x40040000 0x40000>;
 687                         interrupts = <77>;
 688                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
 689                         clock-names = "otg";
 690                         status = "disabled";
 691                 };
 692
 693                 usbotg_fs: usb@50000000 {
 694                         compatible = "st,stm32f4x9-fsotg";
 695                         reg = <0x50000000 0x40000>;
 696                         interrupts = <67>;
 697                         clocks = <&rcc 0 39>;
 698                         clock-names = "otg";
 699                         status = "disabled";
 700                 };
 701
 702                 dcmi: dcmi@50050000 {
 703                         compatible = "st,stm32-dcmi";
 704                         reg = <0x50050000 0x400>;
 705                         interrupts = <78>;
 706                         resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
 707                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
 708                         clock-names = "mclk";
 709                         pinctrl-names = "default";
 710                         pinctrl-0 = <&dcmi_pins>;
 711                         dmas = <&dma2 1 1 0x414 0x3>;
 712                         dma-names = "tx";
 713                         status = "disabled";
 714                 };
 715
 716                 rng: rng@50060800 {
 717                         compatible = "st,stm32-rng";
 718                         reg = <0x50060800 0x400>;
 719                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
 720
 721                 };
 722         };
 723 };
 724
 725 &systick {
 726         clocks = <&rcc 1 SYSTICK>;
 727         status = "okay";
 728 };