arch/arm/dts/stm32f429.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   4  *
   5  */
   6
   7 #include "armv7-m.dtsi"
   8 #include <dt-bindings/clock/stm32fx-clock.h>
   9 #include <dt-bindings/mfd/stm32f4-rcc.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         clocks {
  16                 clk_hse: clk-hse {
  17                         #clock-cells = <0>;
  18                         compatible = "fixed-clock";
  19                         clock-frequency = <0>;
  20                 };
  21
  22                 clk_lse: clk-lse {
  23                         #clock-cells = <0>;
  24                         compatible = "fixed-clock";
  25                         clock-frequency = <32768>;
  26                 };
  27
  28                 clk_lsi: clk-lsi {
  29                         #clock-cells = <0>;
  30                         compatible = "fixed-clock";
  31                         clock-frequency = <32000>;
  32                 };
  33
  34                 clk_i2s_ckin: i2s-ckin {
  35                         #clock-cells = <0>;
  36                         compatible = "fixed-clock";
  37                         clock-frequency = <0>;
  38                 };
  39         };
  40
  41         soc {
  42                 romem: nvmem@1fff7800 {
  43                         compatible = "st,stm32f4-otp";
  44                         reg = <0x1fff7800 0x400>;
  45                         #address-cells = <1>;
  46                         #size-cells = <1>;
  47                         ts_cal1: calib@22c {
  48                                 reg = <0x22c 0x2>;
  49                         };
  50                         ts_cal2: calib@22e {
  51                                 reg = <0x22e 0x2>;
  52                         };
  53                 };
  54
  55                 timer2: timer@40000000 {
  56                         compatible = "st,stm32-timer";
  57                         reg = <0x40000000 0x400>;
  58                         interrupts = <28>;
  59                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  60                         status = "disabled";
  61                 };
  62
  63                 timers2: timers@40000000 {
  64                         #address-cells = <1>;
  65                         #size-cells = <0>;
  66                         compatible = "st,stm32-timers";
  67                         reg = <0x40000000 0x400>;
  68                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  69                         clock-names = "int";
  70                         status = "disabled";
  71
  72                         pwm {
  73                                 compatible = "st,stm32-pwm";
  74                                 #pwm-cells = <3>;
  75                                 status = "disabled";
  76                         };
  77
  78                         timer@1 {
  79                                 compatible = "st,stm32-timer-trigger";
  80                                 reg = <1>;
  81                                 status = "disabled";
  82                         };
  83                 };
  84
  85                 timer3: timer@40000400 {
  86                         compatible = "st,stm32-timer";
  87                         reg = <0x40000400 0x400>;
  88                         interrupts = <29>;
  89                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
  90                         status = "disabled";
  91                 };
  92
  93                 timers3: timers@40000400 {
  94                         #address-cells = <1>;
  95                         #size-cells = <0>;
  96                         compatible = "st,stm32-timers";
  97                         reg = <0x40000400 0x400>;
  98                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
  99                         clock-names = "int";
 100                         status = "disabled";
 101
 102                         pwm {
 103                                 compatible = "st,stm32-pwm";
 104                                 #pwm-cells = <3>;
 105                                 status = "disabled";
 106                         };
 107
 108                         timer@2 {
 109                                 compatible = "st,stm32-timer-trigger";
 110                                 reg = <2>;
 111                                 status = "disabled";
 112                         };
 113                 };
 114
 115                 timer4: timer@40000800 {
 116                         compatible = "st,stm32-timer";
 117                         reg = <0x40000800 0x400>;
 118                         interrupts = <30>;
 119                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 120                         status = "disabled";
 121                 };
 122
 123                 timers4: timers@40000800 {
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         compatible = "st,stm32-timers";
 127                         reg = <0x40000800 0x400>;
 128                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 129                         clock-names = "int";
 130                         status = "disabled";
 131
 132                         pwm {
 133                                 compatible = "st,stm32-pwm";
 134                                 #pwm-cells = <3>;
 135                                 status = "disabled";
 136                         };
 137
 138                         timer@3 {
 139                                 compatible = "st,stm32-timer-trigger";
 140                                 reg = <3>;
 141                                 status = "disabled";
 142                         };
 143                 };
 144
 145                 timer5: timer@40000c00 {
 146                         compatible = "st,stm32-timer";
 147                         reg = <0x40000c00 0x400>;
 148                         interrupts = <50>;
 149                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 150                 };
 151
 152                 timers5: timers@40000c00 {
 153                         #address-cells = <1>;
 154                         #size-cells = <0>;
 155                         compatible = "st,stm32-timers";
 156                         reg = <0x40000C00 0x400>;
 157                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 158                         clock-names = "int";
 159                         status = "disabled";
 160
 161                         pwm {
 162                                 compatible = "st,stm32-pwm";
 163                                 #pwm-cells = <3>;
 164                                 status = "disabled";
 165                         };
 166
 167                         timer@4 {
 168                                 compatible = "st,stm32-timer-trigger";
 169                                 reg = <4>;
 170                                 status = "disabled";
 171                         };
 172                 };
 173
 174                 timer6: timer@40001000 {
 175                         compatible = "st,stm32-timer";
 176                         reg = <0x40001000 0x400>;
 177                         interrupts = <54>;
 178                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 179                         status = "disabled";
 180                 };
 181
 182                 timers6: timers@40001000 {
 183                         #address-cells = <1>;
 184                         #size-cells = <0>;
 185                         compatible = "st,stm32-timers";
 186                         reg = <0x40001000 0x400>;
 187                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 188                         clock-names = "int";
 189                         status = "disabled";
 190
 191                         timer@5 {
 192                                 compatible = "st,stm32-timer-trigger";
 193                                 reg = <5>;
 194                                 status = "disabled";
 195                         };
 196                 };
 197
 198                 timer7: timer@40001400 {
 199                         compatible = "st,stm32-timer";
 200                         reg = <0x40001400 0x400>;
 201                         interrupts = <55>;
 202                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 203                         status = "disabled";
 204                 };
 205
 206                 timers7: timers@40001400 {
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                         compatible = "st,stm32-timers";
 210                         reg = <0x40001400 0x400>;
 211                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 212                         clock-names = "int";
 213                         status = "disabled";
 214
 215                         timer@6 {
 216                                 compatible = "st,stm32-timer-trigger";
 217                                 reg = <6>;
 218                                 status = "disabled";
 219                         };
 220                 };
 221
 222                 timers12: timers@40001800 {
 223                         #address-cells = <1>;
 224                         #size-cells = <0>;
 225                         compatible = "st,stm32-timers";
 226                         reg = <0x40001800 0x400>;
 227                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
 228                         clock-names = "int";
 229                         status = "disabled";
 230
 231                         pwm {
 232                                 compatible = "st,stm32-pwm";
 233                                 #pwm-cells = <3>;
 234                                 status = "disabled";
 235                         };
 236
 237                         timer@11 {
 238                                 compatible = "st,stm32-timer-trigger";
 239                                 reg = <11>;
 240                                 status = "disabled";
 241                         };
 242                 };
 243
 244                 timers13: timers@40001c00 {
 245                         #address-cells = <1>;
 246                         #size-cells = <0>;
 247                         compatible = "st,stm32-timers";
 248                         reg = <0x40001C00 0x400>;
 249                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
 250                         clock-names = "int";
 251                         status = "disabled";
 252
 253                         pwm {
 254                                 compatible = "st,stm32-pwm";
 255                                 #pwm-cells = <3>;
 256                                 status = "disabled";
 257                         };
 258                 };
 259
 260                 timers14: timers@40002000 {
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263                         compatible = "st,stm32-timers";
 264                         reg = <0x40002000 0x400>;
 265                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
 266                         clock-names = "int";
 267                         status = "disabled";
 268
 269                         pwm {
 270                                 compatible = "st,stm32-pwm";
 271                                 #pwm-cells = <3>;
 272                                 status = "disabled";
 273                         };
 274                 };
 275
 276                 rtc: rtc@40002800 {
 277                         compatible = "st,stm32-rtc";
 278                         reg = <0x40002800 0x400>;
 279                         clocks = <&rcc 1 CLK_RTC>;
 280                         clock-names = "ck_rtc";
 281                         assigned-clocks = <&rcc 1 CLK_RTC>;
 282                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 283                         interrupt-parent = <&exti>;
 284                         interrupts = <17 1>;
 285                         interrupt-names = "alarm";
 286                         st,syscfg = <&pwrcfg 0x00 0x100>;
 287                         status = "disabled";
 288                 };
 289
 290                 iwdg: watchdog@40003000 {
 291                         compatible = "st,stm32-iwdg";
 292                         reg = <0x40003000 0x400>;
 293                         clocks = <&clk_lsi>;
 294                         clock-names = "lsi";
 295                         status = "disabled";
 296                 };
 297
 298                 spi2: spi@40003800 {
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                         compatible = "st,stm32f4-spi";
 302                         reg = <0x40003800 0x400>;
 303                         interrupts = <36>;
 304                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
 305                         status = "disabled";
 306                 };
 307
 308                 spi3: spi@40003c00 {
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311                         compatible = "st,stm32f4-spi";
 312                         reg = <0x40003c00 0x400>;
 313                         interrupts = <51>;
 314                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
 315                         status = "disabled";
 316                 };
 317
 318                 usart2: serial@40004400 {
 319                         compatible = "st,stm32-uart";
 320                         reg = <0x40004400 0x400>;
 321                         interrupts = <38>;
 322                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
 323                         status = "disabled";
 324                 };
 325
 326                 usart3: serial@40004800 {
 327                         compatible = "st,stm32-uart";
 328                         reg = <0x40004800 0x400>;
 329                         interrupts = <39>;
 330                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
 331                         status = "disabled";
 332                         dmas = <&dma1 1 4 0x400 0x0>,
 333                                <&dma1 3 4 0x400 0x0>;
 334                         dma-names = "rx", "tx";
 335                 };
 336
 337                 usart4: serial@40004c00 {
 338                         compatible = "st,stm32-uart";
 339                         reg = <0x40004c00 0x400>;
 340                         interrupts = <52>;
 341                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
 342                         status = "disabled";
 343                 };
 344
 345                 usart5: serial@40005000 {
 346                         compatible = "st,stm32-uart";
 347                         reg = <0x40005000 0x400>;
 348                         interrupts = <53>;
 349                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
 350                         status = "disabled";
 351                 };
 352
 353                 i2c1: i2c@40005400 {
 354                         compatible = "st,stm32f4-i2c";
 355                         reg = <0x40005400 0x400>;
 356                         interrupts = <31>,
 357                                      <32>;
 358                         resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
 359                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
 360                         #address-cells = <1>;
 361                         #size-cells = <0>;
 362                         status = "disabled";
 363                 };
 364
 365                 dac: dac@40007400 {
 366                         compatible = "st,stm32f4-dac-core";
 367                         reg = <0x40007400 0x400>;
 368                         resets = <&rcc STM32F4_APB1_RESET(DAC)>;
 369                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
 370                         clock-names = "pclk";
 371                         #address-cells = <1>;
 372                         #size-cells = <0>;
 373                         status = "disabled";
 374
 375                         dac1: dac@1 {
 376                                 compatible = "st,stm32-dac";
 377                                 #io-channels-cells = <1>;
 378                                 reg = <1>;
 379                                 status = "disabled";
 380                         };
 381
 382                         dac2: dac@2 {
 383                                 compatible = "st,stm32-dac";
 384                                 #io-channels-cells = <1>;
 385                                 reg = <2>;
 386                                 status = "disabled";
 387                         };
 388                 };
 389
 390                 usart7: serial@40007800 {
 391                         compatible = "st,stm32-uart";
 392                         reg = <0x40007800 0x400>;
 393                         interrupts = <82>;
 394                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
 395                         status = "disabled";
 396                 };
 397
 398                 usart8: serial@40007c00 {
 399                         compatible = "st,stm32-uart";
 400                         reg = <0x40007c00 0x400>;
 401                         interrupts = <83>;
 402                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
 403                         status = "disabled";
 404                 };
 405
 406                 timers1: timers@40010000 {
 407                         #address-cells = <1>;
 408                         #size-cells = <0>;
 409                         compatible = "st,stm32-timers";
 410                         reg = <0x40010000 0x400>;
 411                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
 412                         clock-names = "int";
 413                         status = "disabled";
 414
 415                         pwm {
 416                                 compatible = "st,stm32-pwm";
 417                                 #pwm-cells = <3>;
 418                                 status = "disabled";
 419                         };
 420
 421                         timer@0 {
 422                                 compatible = "st,stm32-timer-trigger";
 423                                 reg = <0>;
 424                                 status = "disabled";
 425                         };
 426                 };
 427
 428                 timers8: timers@40010400 {
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                         compatible = "st,stm32-timers";
 432                         reg = <0x40010400 0x400>;
 433                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
 434                         clock-names = "int";
 435                         status = "disabled";
 436
 437                         pwm {
 438                                 compatible = "st,stm32-pwm";
 439                                 #pwm-cells = <3>;
 440                                 status = "disabled";
 441                         };
 442
 443                         timer@7 {
 444                                 compatible = "st,stm32-timer-trigger";
 445                                 reg = <7>;
 446                                 status = "disabled";
 447                         };
 448                 };
 449
 450                 usart1: serial@40011000 {
 451                         compatible = "st,stm32-uart";
 452                         reg = <0x40011000 0x400>;
 453                         interrupts = <37>;
 454                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
 455                         status = "disabled";
 456                         dmas = <&dma2 2 4 0x400 0x0>,
 457                                <&dma2 7 4 0x400 0x0>;
 458                         dma-names = "rx", "tx";
 459                 };
 460
 461                 usart6: serial@40011400 {
 462                         compatible = "st,stm32-uart";
 463                         reg = <0x40011400 0x400>;
 464                         interrupts = <71>;
 465                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
 466                         status = "disabled";
 467                 };
 468
 469                 adc: adc@40012000 {
 470                         compatible = "st,stm32f4-adc-core";
 471                         reg = <0x40012000 0x400>;
 472                         interrupts = <18>;
 473                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 474                         clock-names = "adc";
 475                         interrupt-controller;
 476                         #interrupt-cells = <1>;
 477                         #address-cells = <1>;
 478                         #size-cells = <0>;
 479                         status = "disabled";
 480
 481                         adc1: adc@0 {
 482                                 compatible = "st,stm32f4-adc";
 483                                 #io-channel-cells = <1>;
 484                                 reg = <0x0>;
 485                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 486                                 interrupt-parent = <&adc>;
 487                                 interrupts = <0>;
 488                                 dmas = <&dma2 0 0 0x400 0x0>;
 489                                 dma-names = "rx";
 490                                 status = "disabled";
 491                         };
 492
 493                         adc2: adc@100 {
 494                                 compatible = "st,stm32f4-adc";
 495                                 #io-channel-cells = <1>;
 496                                 reg = <0x100>;
 497                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
 498                                 interrupt-parent = <&adc>;
 499                                 interrupts = <1>;
 500                                 dmas = <&dma2 3 1 0x400 0x0>;
 501                                 dma-names = "rx";
 502                                 status = "disabled";
 503                         };
 504
 505                         adc3: adc@200 {
 506                                 compatible = "st,stm32f4-adc";
 507                                 #io-channel-cells = <1>;
 508                                 reg = <0x200>;
 509                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
 510                                 interrupt-parent = <&adc>;
 511                                 interrupts = <2>;
 512                                 dmas = <&dma2 1 2 0x400 0x0>;
 513                                 dma-names = "rx";
 514                                 status = "disabled";
 515                         };
 516                 };
 517
 518                 sdio: sdio@40012c00 {
 519                         compatible = "arm,pl180", "arm,primecell";
 520                         arm,primecell-periphid = <0x00880180>;
 521                         reg = <0x40012c00 0x400>;
 522                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
 523                         clock-names = "apb_pclk";
 524                         interrupts = <49>;
 525                         max-frequency = <48000000>;
 526                         status = "disabled";
 527                 };
 528
 529                 spi1: spi@40013000 {
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                         compatible = "st,stm32f4-spi";
 533                         reg = <0x40013000 0x400>;
 534                         interrupts = <35>;
 535                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
 536                         status = "disabled";
 537                 };
 538
 539                 spi4: spi@40013400 {
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                         compatible = "st,stm32f4-spi";
 543                         reg = <0x40013400 0x400>;
 544                         interrupts = <84>;
 545                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
 546                         status = "disabled";
 547                 };
 548
 549                 syscfg: system-config@40013800 {
 550                         compatible = "syscon";
 551                         reg = <0x40013800 0x400>;
 552                 };
 553
 554                 exti: interrupt-controller@40013c00 {
 555                         compatible = "st,stm32-exti";
 556                         interrupt-controller;
 557                         #interrupt-cells = <2>;
 558                         reg = <0x40013C00 0x400>;
 559                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 560                 };
 561
 562                 timers9: timers@40014000 {
 563                         #address-cells = <1>;
 564                         #size-cells = <0>;
 565                         compatible = "st,stm32-timers";
 566                         reg = <0x40014000 0x400>;
 567                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
 568                         clock-names = "int";
 569                         status = "disabled";
 570
 571                         pwm {
 572                                 compatible = "st,stm32-pwm";
 573                                 #pwm-cells = <3>;
 574                                 status = "disabled";
 575                         };
 576
 577                         timer@8 {
 578                                 compatible = "st,stm32-timer-trigger";
 579                                 reg = <8>;
 580                                 status = "disabled";
 581                         };
 582                 };
 583
 584                 timers10: timers@40014400 {
 585                         #address-cells = <1>;
 586                         #size-cells = <0>;
 587                         compatible = "st,stm32-timers";
 588                         reg = <0x40014400 0x400>;
 589                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
 590                         clock-names = "int";
 591                         status = "disabled";
 592
 593                         pwm {
 594                                 compatible = "st,stm32-pwm";
 595                                 #pwm-cells = <3>;
 596                                 status = "disabled";
 597                         };
 598                 };
 599
 600                 timers11: timers@40014800 {
 601                         #address-cells = <1>;
 602                         #size-cells = <0>;
 603                         compatible = "st,stm32-timers";
 604                         reg = <0x40014800 0x400>;
 605                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
 606                         clock-names = "int";
 607                         status = "disabled";
 608
 609                         pwm {
 610                                 compatible = "st,stm32-pwm";
 611                                 #pwm-cells = <3>;
 612                                 status = "disabled";
 613                         };
 614                 };
 615
 616                 spi5: spi@40015000 {
 617                         #address-cells = <1>;
 618                         #size-cells = <0>;
 619                         compatible = "st,stm32f4-spi";
 620                         reg = <0x40015000 0x400>;
 621                         interrupts = <85>;
 622                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
 623                         status = "disabled";
 624                 };
 625
 626                 spi6: spi@40015400 {
 627                         #address-cells = <1>;
 628                         #size-cells = <0>;
 629                         compatible = "st,stm32f4-spi";
 630                         reg = <0x40015400 0x400>;
 631                         interrupts = <86>;
 632                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
 633                         status = "disabled";
 634                 };
 635
 636                 pwrcfg: power-config@40007000 {
 637                         compatible = "syscon";
 638                         reg = <0x40007000 0x400>;
 639                 };
 640
 641                 ltdc: display-controller@40016800 {
 642                         compatible = "st,stm32-ltdc";
 643                         reg = <0x40016800 0x200>;
 644                         interrupts = <88>, <89>;
 645                         resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
 646                         clocks = <&rcc 1 CLK_LCD>;
 647                         clock-names = "lcd";
 648                         status = "disabled";
 649                 };
 650
 651                 crc: crc@40023000 {
 652                         compatible = "st,stm32f4-crc";
 653                         reg = <0x40023000 0x400>;
 654                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
 655                         status = "disabled";
 656                 };
 657
 658                 rcc: rcc@40023810 {
 659                         #reset-cells = <1>;
 660                         #clock-cells = <2>;
 661                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 662                         reg = <0x40023800 0x400>;
 663                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 664                         st,syscfg = <&pwrcfg>;
 665                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 666                         assigned-clock-rates = <1000000>;
 667                 };
 668
 669                 dma1: dma-controller@40026000 {
 670                         compatible = "st,stm32-dma";
 671                         reg = <0x40026000 0x400>;
 672                         interrupts = <11>,
 673                                      <12>,
 674                                      <13>,
 675                                      <14>,
 676                                      <15>,
 677                                      <16>,
 678                                      <17>,
 679                                      <47>;
 680                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
 681                         #dma-cells = <4>;
 682                 };
 683
 684                 dma2: dma-controller@40026400 {
 685                         compatible = "st,stm32-dma";
 686                         reg = <0x40026400 0x400>;
 687                         interrupts = <56>,
 688                                      <57>,
 689                                      <58>,
 690                                      <59>,
 691                                      <60>,
 692                                      <68>,
 693                                      <69>,
 694                                      <70>;
 695                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
 696                         #dma-cells = <4>;
 697                         st,mem2mem;
 698                 };
 699
 700                 mac: ethernet@40028000 {
 701                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 702                         reg = <0x40028000 0x8000>;
 703                         reg-names = "stmmaceth";
 704                         interrupts = <61>;
 705                         interrupt-names = "macirq";
 706                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 707                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
 708                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
 709                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
 710                         st,syscon = <&syscfg 0x4>;
 711                         snps,pbl = <8>;
 712                         snps,mixed-burst;
 713                         status = "disabled";
 714                 };
 715
 716                 usbotg_hs: usb@40040000 {
 717                         compatible = "snps,dwc2";
 718                         reg = <0x40040000 0x40000>;
 719                         interrupts = <77>;
 720                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
 721                         clock-names = "otg";
 722                         status = "disabled";
 723                 };
 724
 725                 usbotg_fs: usb@50000000 {
 726                         compatible = "st,stm32f4x9-fsotg";
 727                         reg = <0x50000000 0x40000>;
 728                         interrupts = <67>;
 729                         clocks = <&rcc 0 39>;
 730                         clock-names = "otg";
 731                         status = "disabled";
 732                 };
 733
 734                 dcmi: dcmi@50050000 {
 735                         compatible = "st,stm32-dcmi";
 736                         reg = <0x50050000 0x400>;
 737                         interrupts = <78>;
 738                         resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
 739                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
 740                         clock-names = "mclk";
 741                         pinctrl-names = "default";
 742                         pinctrl-0 = <&dcmi_pins>;
 743                         dmas = <&dma2 1 1 0x414 0x3>;
 744                         dma-names = "tx";
 745                         status = "disabled";
 746                 };
 747
 748                 rng: rng@50060800 {
 749                         compatible = "st,stm32-rng";
 750                         reg = <0x50060800 0x400>;
 751                         interrupts = <80>;
 752                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
 753
 754                 };
 755         };
 756 };
 757
 758 &systick {
 759         clocks = <&rcc 1 SYSTICK>;
 760         status = "okay";
 761 };