arch/arm/dts/stm32f429.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   4  *
   5  */
   6
   7 #include "armv7-m.dtsi"
   8 #include <dt-bindings/clock/stm32fx-clock.h>
   9 #include <dt-bindings/mfd/stm32f4-rcc.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         clocks {
  16                 clk_hse: clk-hse {
  17                         #clock-cells = <0>;
  18                         compatible = "fixed-clock";
  19                         clock-frequency = <0>;
  20                 };
  21
  22                 clk_lse: clk-lse {
  23                         #clock-cells = <0>;
  24                         compatible = "fixed-clock";
  25                         clock-frequency = <32768>;
  26                 };
  27
  28                 clk_lsi: clk-lsi {
  29                         #clock-cells = <0>;
  30                         compatible = "fixed-clock";
  31                         clock-frequency = <32000>;
  32                 };
  33
  34                 clk_i2s_ckin: i2s-ckin {
  35                         #clock-cells = <0>;
  36                         compatible = "fixed-clock";
  37                         clock-frequency = <0>;
  38                 };
  39         };
  40
  41         soc {
  42                 romem: efuse@1fff7800 {
  43                         compatible = "st,stm32f4-otp";
  44                         reg = <0x1fff7800 0x400>;
  45                         #address-cells = <1>;
  46                         #size-cells = <1>;
  47                         ts_cal1: calib@22c {
  48                                 reg = <0x22c 0x2>;
  49                         };
  50                         ts_cal2: calib@22e {
  51                                 reg = <0x22e 0x2>;
  52                         };
  53                 };
  54
  55                 timer2: timer@40000000 {
  56                         compatible = "st,stm32-timer";
  57                         reg = <0x40000000 0x400>;
  58                         interrupts = <28>;
  59                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  60                         status = "disabled";
  61                 };
  62
  63                 timers2: timers@40000000 {
  64                         #address-cells = <1>;
  65                         #size-cells = <0>;
  66                         compatible = "st,stm32-timers";
  67                         reg = <0x40000000 0x400>;
  68                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  69                         clock-names = "int";
  70                         status = "disabled";
  71
  72                         pwm {
  73                                 compatible = "st,stm32-pwm";
  74                                 #pwm-cells = <3>;
  75                                 status = "disabled";
  76                         };
  77
  78                         timer@1 {
  79                                 compatible = "st,stm32-timer-trigger";
  80                                 reg = <1>;
  81                                 status = "disabled";
  82                         };
  83                 };
  84
  85                 timer3: timer@40000400 {
  86                         compatible = "st,stm32-timer";
  87                         reg = <0x40000400 0x400>;
  88                         interrupts = <29>;
  89                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
  90                         status = "disabled";
  91                 };
  92
  93                 timers3: timers@40000400 {
  94                         #address-cells = <1>;
  95                         #size-cells = <0>;
  96                         compatible = "st,stm32-timers";
  97                         reg = <0x40000400 0x400>;
  98                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
  99                         clock-names = "int";
 100                         status = "disabled";
 101
 102                         pwm {
 103                                 compatible = "st,stm32-pwm";
 104                                 #pwm-cells = <3>;
 105                                 status = "disabled";
 106                         };
 107
 108                         timer@2 {
 109                                 compatible = "st,stm32-timer-trigger";
 110                                 reg = <2>;
 111                                 status = "disabled";
 112                         };
 113                 };
 114
 115                 timer4: timer@40000800 {
 116                         compatible = "st,stm32-timer";
 117                         reg = <0x40000800 0x400>;
 118                         interrupts = <30>;
 119                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 120                         status = "disabled";
 121                 };
 122
 123                 timers4: timers@40000800 {
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         compatible = "st,stm32-timers";
 127                         reg = <0x40000800 0x400>;
 128                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 129                         clock-names = "int";
 130                         status = "disabled";
 131
 132                         pwm {
 133                                 compatible = "st,stm32-pwm";
 134                                 #pwm-cells = <3>;
 135                                 status = "disabled";
 136                         };
 137
 138                         timer@3 {
 139                                 compatible = "st,stm32-timer-trigger";
 140                                 reg = <3>;
 141                                 status = "disabled";
 142                         };
 143                 };
 144
 145                 timer5: timer@40000c00 {
 146                         compatible = "st,stm32-timer";
 147                         reg = <0x40000c00 0x400>;
 148                         interrupts = <50>;
 149                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 150                 };
 151
 152                 timers5: timers@40000c00 {
 153                         #address-cells = <1>;
 154                         #size-cells = <0>;
 155                         compatible = "st,stm32-timers";
 156                         reg = <0x40000C00 0x400>;
 157                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 158                         clock-names = "int";
 159                         status = "disabled";
 160
 161                         pwm {
 162                                 compatible = "st,stm32-pwm";
 163                                 #pwm-cells = <3>;
 164                                 status = "disabled";
 165                         };
 166
 167                         timer@4 {
 168                                 compatible = "st,stm32-timer-trigger";
 169                                 reg = <4>;
 170                                 status = "disabled";
 171                         };
 172                 };
 173
 174                 timer6: timer@40001000 {
 175                         compatible = "st,stm32-timer";
 176                         reg = <0x40001000 0x400>;
 177                         interrupts = <54>;
 178                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 179                         status = "disabled";
 180                 };
 181
 182                 timers6: timers@40001000 {
 183                         #address-cells = <1>;
 184                         #size-cells = <0>;
 185                         compatible = "st,stm32-timers";
 186                         reg = <0x40001000 0x400>;
 187                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 188                         clock-names = "int";
 189                         status = "disabled";
 190
 191                         timer@5 {
 192                                 compatible = "st,stm32-timer-trigger";
 193                                 reg = <5>;
 194                                 status = "disabled";
 195                         };
 196                 };
 197
 198                 timer7: timer@40001400 {
 199                         compatible = "st,stm32-timer";
 200                         reg = <0x40001400 0x400>;
 201                         interrupts = <55>;
 202                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 203                         status = "disabled";
 204                 };
 205
 206                 timers7: timers@40001400 {
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                         compatible = "st,stm32-timers";
 210                         reg = <0x40001400 0x400>;
 211                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 212                         clock-names = "int";
 213                         status = "disabled";
 214
 215                         timer@6 {
 216                                 compatible = "st,stm32-timer-trigger";
 217                                 reg = <6>;
 218                                 status = "disabled";
 219                         };
 220                 };
 221
 222                 timers12: timers@40001800 {
 223                         #address-cells = <1>;
 224                         #size-cells = <0>;
 225                         compatible = "st,stm32-timers";
 226                         reg = <0x40001800 0x400>;
 227                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
 228                         clock-names = "int";
 229                         status = "disabled";
 230
 231                         pwm {
 232                                 compatible = "st,stm32-pwm";
 233                                 #pwm-cells = <3>;
 234                                 status = "disabled";
 235                         };
 236
 237                         timer@11 {
 238                                 compatible = "st,stm32-timer-trigger";
 239                                 reg = <11>;
 240                                 status = "disabled";
 241                         };
 242                 };
 243
 244                 timers13: timers@40001c00 {
 245                         #address-cells = <1>;
 246                         #size-cells = <0>;
 247                         compatible = "st,stm32-timers";
 248                         reg = <0x40001C00 0x400>;
 249                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
 250                         clock-names = "int";
 251                         status = "disabled";
 252
 253                         pwm {
 254                                 compatible = "st,stm32-pwm";
 255                                 #pwm-cells = <3>;
 256                                 status = "disabled";
 257                         };
 258                 };
 259
 260                 timers14: timers@40002000 {
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263                         compatible = "st,stm32-timers";
 264                         reg = <0x40002000 0x400>;
 265                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
 266                         clock-names = "int";
 267                         status = "disabled";
 268
 269                         pwm {
 270                                 compatible = "st,stm32-pwm";
 271                                 #pwm-cells = <3>;
 272                                 status = "disabled";
 273                         };
 274                 };
 275
 276                 rtc: rtc@40002800 {
 277                         compatible = "st,stm32-rtc";
 278                         reg = <0x40002800 0x400>;
 279                         clocks = <&rcc 1 CLK_RTC>;
 280                         assigned-clocks = <&rcc 1 CLK_RTC>;
 281                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 282                         interrupt-parent = <&exti>;
 283                         interrupts = <17 1>;
 284                         st,syscfg = <&pwrcfg 0x00 0x100>;
 285                         status = "disabled";
 286                 };
 287
 288                 iwdg: watchdog@40003000 {
 289                         compatible = "st,stm32-iwdg";
 290                         reg = <0x40003000 0x400>;
 291                         clocks = <&clk_lsi>;
 292                         clock-names = "lsi";
 293                         status = "disabled";
 294                 };
 295
 296                 spi2: spi@40003800 {
 297                         #address-cells = <1>;
 298                         #size-cells = <0>;
 299                         compatible = "st,stm32f4-spi";
 300                         reg = <0x40003800 0x400>;
 301                         interrupts = <36>;
 302                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
 303                         status = "disabled";
 304                 };
 305
 306                 spi3: spi@40003c00 {
 307                         #address-cells = <1>;
 308                         #size-cells = <0>;
 309                         compatible = "st,stm32f4-spi";
 310                         reg = <0x40003c00 0x400>;
 311                         interrupts = <51>;
 312                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
 313                         status = "disabled";
 314                 };
 315
 316                 usart2: serial@40004400 {
 317                         compatible = "st,stm32-uart";
 318                         reg = <0x40004400 0x400>;
 319                         interrupts = <38>;
 320                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
 321                         status = "disabled";
 322                 };
 323
 324                 usart3: serial@40004800 {
 325                         compatible = "st,stm32-uart";
 326                         reg = <0x40004800 0x400>;
 327                         interrupts = <39>;
 328                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
 329                         status = "disabled";
 330                         dmas = <&dma1 1 4 0x400 0x0>,
 331                                <&dma1 3 4 0x400 0x0>;
 332                         dma-names = "rx", "tx";
 333                 };
 334
 335                 usart4: serial@40004c00 {
 336                         compatible = "st,stm32-uart";
 337                         reg = <0x40004c00 0x400>;
 338                         interrupts = <52>;
 339                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
 340                         status = "disabled";
 341                 };
 342
 343                 usart5: serial@40005000 {
 344                         compatible = "st,stm32-uart";
 345                         reg = <0x40005000 0x400>;
 346                         interrupts = <53>;
 347                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
 348                         status = "disabled";
 349                 };
 350
 351                 i2c1: i2c@40005400 {
 352                         compatible = "st,stm32f4-i2c";
 353                         reg = <0x40005400 0x400>;
 354                         interrupts = <31>,
 355                                      <32>;
 356                         resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
 357                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         status = "disabled";
 361                 };
 362
 363                 i2c3: i2c@40005c00 {
 364                         compatible = "st,stm32f4-i2c";
 365                         reg = <0x40005c00 0x400>;
 366                         interrupts = <72>,
 367                                      <73>;
 368                         resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
 369                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         status = "disabled";
 373                 };
 374
 375                 dac: dac@40007400 {
 376                         compatible = "st,stm32f4-dac-core";
 377                         reg = <0x40007400 0x400>;
 378                         resets = <&rcc STM32F4_APB1_RESET(DAC)>;
 379                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
 380                         clock-names = "pclk";
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                         status = "disabled";
 384
 385                         dac1: dac@1 {
 386                                 compatible = "st,stm32-dac";
 387                                 #io-channel-cells = <1>;
 388                                 reg = <1>;
 389                                 status = "disabled";
 390                         };
 391
 392                         dac2: dac@2 {
 393                                 compatible = "st,stm32-dac";
 394                                 #io-channel-cells = <1>;
 395                                 reg = <2>;
 396                                 status = "disabled";
 397                         };
 398                 };
 399
 400                 usart7: serial@40007800 {
 401                         compatible = "st,stm32-uart";
 402                         reg = <0x40007800 0x400>;
 403                         interrupts = <82>;
 404                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
 405                         status = "disabled";
 406                 };
 407
 408                 usart8: serial@40007c00 {
 409                         compatible = "st,stm32-uart";
 410                         reg = <0x40007c00 0x400>;
 411                         interrupts = <83>;
 412                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
 413                         status = "disabled";
 414                 };
 415
 416                 timers1: timers@40010000 {
 417                         #address-cells = <1>;
 418                         #size-cells = <0>;
 419                         compatible = "st,stm32-timers";
 420                         reg = <0x40010000 0x400>;
 421                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
 422                         clock-names = "int";
 423                         status = "disabled";
 424
 425                         pwm {
 426                                 compatible = "st,stm32-pwm";
 427                                 #pwm-cells = <3>;
 428                                 status = "disabled";
 429                         };
 430
 431                         timer@0 {
 432                                 compatible = "st,stm32-timer-trigger";
 433                                 reg = <0>;
 434                                 status = "disabled";
 435                         };
 436                 };
 437
 438                 timers8: timers@40010400 {
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         compatible = "st,stm32-timers";
 442                         reg = <0x40010400 0x400>;
 443                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
 444                         clock-names = "int";
 445                         status = "disabled";
 446
 447                         pwm {
 448                                 compatible = "st,stm32-pwm";
 449                                 #pwm-cells = <3>;
 450                                 status = "disabled";
 451                         };
 452
 453                         timer@7 {
 454                                 compatible = "st,stm32-timer-trigger";
 455                                 reg = <7>;
 456                                 status = "disabled";
 457                         };
 458                 };
 459
 460                 usart1: serial@40011000 {
 461                         compatible = "st,stm32-uart";
 462                         reg = <0x40011000 0x400>;
 463                         interrupts = <37>;
 464                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
 465                         status = "disabled";
 466                         dmas = <&dma2 2 4 0x400 0x0>,
 467                                <&dma2 7 4 0x400 0x0>;
 468                         dma-names = "rx", "tx";
 469                 };
 470
 471                 usart6: serial@40011400 {
 472                         compatible = "st,stm32-uart";
 473                         reg = <0x40011400 0x400>;
 474                         interrupts = <71>;
 475                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
 476                         status = "disabled";
 477                 };
 478
 479                 adc: adc@40012000 {
 480                         compatible = "st,stm32f4-adc-core";
 481                         reg = <0x40012000 0x400>;
 482                         interrupts = <18>;
 483                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 484                         clock-names = "adc";
 485                         interrupt-controller;
 486                         #interrupt-cells = <1>;
 487                         #address-cells = <1>;
 488                         #size-cells = <0>;
 489                         status = "disabled";
 490
 491                         adc1: adc@0 {
 492                                 compatible = "st,stm32f4-adc";
 493                                 #io-channel-cells = <1>;
 494                                 reg = <0x0>;
 495                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 496                                 interrupt-parent = <&adc>;
 497                                 interrupts = <0>;
 498                                 dmas = <&dma2 0 0 0x400 0x0>;
 499                                 dma-names = "rx";
 500                                 status = "disabled";
 501                         };
 502
 503                         adc2: adc@100 {
 504                                 compatible = "st,stm32f4-adc";
 505                                 #io-channel-cells = <1>;
 506                                 reg = <0x100>;
 507                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
 508                                 interrupt-parent = <&adc>;
 509                                 interrupts = <1>;
 510                                 dmas = <&dma2 3 1 0x400 0x0>;
 511                                 dma-names = "rx";
 512                                 status = "disabled";
 513                         };
 514
 515                         adc3: adc@200 {
 516                                 compatible = "st,stm32f4-adc";
 517                                 #io-channel-cells = <1>;
 518                                 reg = <0x200>;
 519                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
 520                                 interrupt-parent = <&adc>;
 521                                 interrupts = <2>;
 522                                 dmas = <&dma2 1 2 0x400 0x0>;
 523                                 dma-names = "rx";
 524                                 status = "disabled";
 525                         };
 526                 };
 527
 528                 sdio: sdio@40012c00 {
 529                         compatible = "arm,pl180", "arm,primecell";
 530                         arm,primecell-periphid = <0x00880180>;
 531                         reg = <0x40012c00 0x400>;
 532                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
 533                         clock-names = "apb_pclk";
 534                         interrupts = <49>;
 535                         max-frequency = <48000000>;
 536                         status = "disabled";
 537                 };
 538
 539                 spi1: spi@40013000 {
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                         compatible = "st,stm32f4-spi";
 543                         reg = <0x40013000 0x400>;
 544                         interrupts = <35>;
 545                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
 546                         status = "disabled";
 547                 };
 548
 549                 spi4: spi@40013400 {
 550                         #address-cells = <1>;
 551                         #size-cells = <0>;
 552                         compatible = "st,stm32f4-spi";
 553                         reg = <0x40013400 0x400>;
 554                         interrupts = <84>;
 555                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
 556                         status = "disabled";
 557                 };
 558
 559                 syscfg: syscon@40013800 {
 560                         compatible = "st,stm32-syscfg", "syscon";
 561                         reg = <0x40013800 0x400>;
 562                 };
 563
 564                 exti: interrupt-controller@40013c00 {
 565                         compatible = "st,stm32-exti";
 566                         interrupt-controller;
 567                         #interrupt-cells = <2>;
 568                         reg = <0x40013C00 0x400>;
 569                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 570                 };
 571
 572                 timers9: timers@40014000 {
 573                         #address-cells = <1>;
 574                         #size-cells = <0>;
 575                         compatible = "st,stm32-timers";
 576                         reg = <0x40014000 0x400>;
 577                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
 578                         clock-names = "int";
 579                         status = "disabled";
 580
 581                         pwm {
 582                                 compatible = "st,stm32-pwm";
 583                                 #pwm-cells = <3>;
 584                                 status = "disabled";
 585                         };
 586
 587                         timer@8 {
 588                                 compatible = "st,stm32-timer-trigger";
 589                                 reg = <8>;
 590                                 status = "disabled";
 591                         };
 592                 };
 593
 594                 timers10: timers@40014400 {
 595                         #address-cells = <1>;
 596                         #size-cells = <0>;
 597                         compatible = "st,stm32-timers";
 598                         reg = <0x40014400 0x400>;
 599                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
 600                         clock-names = "int";
 601                         status = "disabled";
 602
 603                         pwm {
 604                                 compatible = "st,stm32-pwm";
 605                                 #pwm-cells = <3>;
 606                                 status = "disabled";
 607                         };
 608                 };
 609
 610                 timers11: timers@40014800 {
 611                         #address-cells = <1>;
 612                         #size-cells = <0>;
 613                         compatible = "st,stm32-timers";
 614                         reg = <0x40014800 0x400>;
 615                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
 616                         clock-names = "int";
 617                         status = "disabled";
 618
 619                         pwm {
 620                                 compatible = "st,stm32-pwm";
 621                                 #pwm-cells = <3>;
 622                                 status = "disabled";
 623                         };
 624                 };
 625
 626                 spi5: spi@40015000 {
 627                         #address-cells = <1>;
 628                         #size-cells = <0>;
 629                         compatible = "st,stm32f4-spi";
 630                         reg = <0x40015000 0x400>;
 631                         interrupts = <85>;
 632                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
 633                         dmas = <&dma2 3 2 0x400 0x0>,
 634                                 <&dma2 4 2 0x400 0x0>;
 635                         dma-names = "rx", "tx";
 636                         status = "disabled";
 637                 };
 638
 639                 spi6: spi@40015400 {
 640                         #address-cells = <1>;
 641                         #size-cells = <0>;
 642                         compatible = "st,stm32f4-spi";
 643                         reg = <0x40015400 0x400>;
 644                         interrupts = <86>;
 645                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
 646                         status = "disabled";
 647                 };
 648
 649                 pwrcfg: power-config@40007000 {
 650                         compatible = "st,stm32-power-config", "syscon";
 651                         reg = <0x40007000 0x400>;
 652                 };
 653
 654                 ltdc: display-controller@40016800 {
 655                         compatible = "st,stm32-ltdc";
 656                         reg = <0x40016800 0x200>;
 657                         interrupts = <88>, <89>;
 658                         resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
 659                         clocks = <&rcc 1 CLK_LCD>;
 660                         clock-names = "lcd";
 661                         status = "disabled";
 662                 };
 663
 664                 crc: crc@40023000 {
 665                         compatible = "st,stm32f4-crc";
 666                         reg = <0x40023000 0x400>;
 667                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
 668                         status = "disabled";
 669                 };
 670
 671                 rcc: rcc@40023810 {
 672                         #reset-cells = <1>;
 673                         #clock-cells = <2>;
 674                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 675                         reg = <0x40023800 0x400>;
 676                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 677                         st,syscfg = <&pwrcfg>;
 678                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 679                         assigned-clock-rates = <1000000>;
 680                 };
 681
 682                 dma1: dma-controller@40026000 {
 683                         compatible = "st,stm32-dma";
 684                         reg = <0x40026000 0x400>;
 685                         interrupts = <11>,
 686                                      <12>,
 687                                      <13>,
 688                                      <14>,
 689                                      <15>,
 690                                      <16>,
 691                                      <17>,
 692                                      <47>;
 693                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
 694                         #dma-cells = <4>;
 695                 };
 696
 697                 dma2: dma-controller@40026400 {
 698                         compatible = "st,stm32-dma";
 699                         reg = <0x40026400 0x400>;
 700                         interrupts = <56>,
 701                                      <57>,
 702                                      <58>,
 703                                      <59>,
 704                                      <60>,
 705                                      <68>,
 706                                      <69>,
 707                                      <70>;
 708                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
 709                         #dma-cells = <4>;
 710                         st,mem2mem;
 711                 };
 712
 713                 mac: ethernet@40028000 {
 714                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 715                         reg = <0x40028000 0x8000>;
 716                         reg-names = "stmmaceth";
 717                         interrupts = <61>;
 718                         interrupt-names = "macirq";
 719                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 720                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
 721                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
 722                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
 723                         st,syscon = <&syscfg 0x4>;
 724                         snps,pbl = <8>;
 725                         snps,mixed-burst;
 726                         status = "disabled";
 727                 };
 728
 729                 usbotg_hs: usb@40040000 {
 730                         compatible = "snps,dwc2";
 731                         reg = <0x40040000 0x40000>;
 732                         interrupts = <77>;
 733                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
 734                         clock-names = "otg";
 735                         status = "disabled";
 736                 };
 737
 738                 usbotg_fs: usb@50000000 {
 739                         compatible = "st,stm32f4x9-fsotg";
 740                         reg = <0x50000000 0x40000>;
 741                         interrupts = <67>;
 742                         clocks = <&rcc 0 39>;
 743                         clock-names = "otg";
 744                         status = "disabled";
 745                 };
 746
 747                 dcmi: dcmi@50050000 {
 748                         compatible = "st,stm32-dcmi";
 749                         reg = <0x50050000 0x400>;
 750                         interrupts = <78>;
 751                         resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
 752                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
 753                         clock-names = "mclk";
 754                         pinctrl-names = "default";
 755                         pinctrl-0 = <&dcmi_pins>;
 756                         dmas = <&dma2 1 1 0x414 0x3>;
 757                         dma-names = "tx";
 758                         status = "disabled";
 759                 };
 760
 761                 rng: rng@50060800 {
 762                         compatible = "st,stm32-rng";
 763                         reg = <0x50060800 0x400>;
 764                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
 765
 766                 };
 767         };
 768 };
 769
 770 &systick {
 771         clocks = <&rcc 1 SYSTICK>;
 772         status = "okay";
 773 };