arch/arm/dts/stm32f429-disco-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
   5  */
   6
   7 #include <dt-bindings/memory/stm32-sdram.h>
   8 /{
   9         clocks {
  10                 bootph-all;
  11         };
  12
  13         aliases {
  14                 /* Aliases for gpios so as to use sequence */
  15                 gpio0 = &gpioa;
  16                 gpio1 = &gpiob;
  17                 gpio2 = &gpioc;
  18                 gpio3 = &gpiod;
  19                 gpio4 = &gpioe;
  20                 gpio5 = &gpiof;
  21                 gpio6 = &gpiog;
  22                 gpio7 = &gpioh;
  23                 gpio8 = &gpioi;
  24                 gpio9 = &gpioj;
  25                 gpio10 = &gpiok;
  26         };
  27
  28         soc {
  29                 bootph-all;
  30                 fmc: fmc@A0000000 {
  31                         compatible = "st,stm32-fmc";
  32                         reg = <0xa0000000 0x1000>;
  33                         clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
  34                         pinctrl-0 = <&fmc_pins>;
  35                         pinctrl-names = "default";
  36                         st,syscfg = <&syscfg>;
  37                         st,swp_fmc = <1>;
  38                         bootph-all;
  39
  40                         /*
  41                          * Memory configuration from sdram datasheet
  42                          * IS42S16400J
  43                          */
  44                         bank1: bank@1 {
  45                                st,sdram-control = /bits/ 8 <NO_COL_8
  46                                                             NO_ROW_12
  47                                                             MWIDTH_16
  48                                                             BANKS_4
  49                                                             CAS_3
  50                                                             SDCLK_2
  51                                                             RD_BURST_EN
  52                                                             RD_PIPE_DL_0>;
  53                                st,sdram-timing = /bits/ 8 <TMRD_3
  54                                                            TXSR_7
  55                                                            TRAS_4
  56                                                            TRC_6
  57                                                            TWR_2
  58                                                            TRP_2 TRCD_2>;
  59                                st,sdram-refcount = < 1386 >;
  60                        };
  61                 };
  62         };
  63 };
  64
  65 &clk_hse {
  66         bootph-all;
  67 };
  68
  69 &clk_i2s_ckin {
  70         bootph-all;
  71 };
  72
  73 &clk_lse {
  74         bootph-all;
  75 };
  76
  77 &gpioa {
  78         bootph-all;
  79 };
  80
  81 &gpiob {
  82         bootph-all;
  83 };
  84
  85 &gpioc {
  86         bootph-all;
  87 };
  88
  89 &gpiod {
  90         bootph-all;
  91 };
  92
  93 &gpioe {
  94         bootph-all;
  95 };
  96
  97 &gpiof {
  98         bootph-all;
  99 };
 100
 101 &gpiog {
 102         bootph-all;
 103 };
 104
 105 &gpioh {
 106         bootph-all;
 107 };
 108
 109 &gpioi {
 110         bootph-all;
 111 };
 112
 113 &gpioj {
 114         bootph-all;
 115 };
 116
 117 &gpiok {
 118         bootph-all;
 119 };
 120
 121 &pinctrl {
 122         bootph-all;
 123
 124         usart1_pins_a: usart1-0 {
 125                 bootph-all;
 126                 pins1 {
 127                         bootph-all;
 128                 };
 129                 pins2 {
 130                         bootph-all;
 131                 };
 132         };
 133
 134         fmc_pins: fmc@0 {
 135                 bootph-all;
 136                 pins
 137                 {
 138                         pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
 139                                  <STM32_PINMUX('D', 9, AF12)>, /* D14 */
 140                                  <STM32_PINMUX('D', 8, AF12)>, /* D13 */
 141                                  <STM32_PINMUX('E',15, AF12)>, /* D12 */
 142                                  <STM32_PINMUX('E',14, AF12)>, /* D11 */
 143                                  <STM32_PINMUX('E',13, AF12)>, /* D10 */
 144                                  <STM32_PINMUX('E',12, AF12)>, /* D09 */
 145                                  <STM32_PINMUX('E',11, AF12)>, /* D08 */
 146                                  <STM32_PINMUX('E',10, AF12)>, /* D07 */
 147                                  <STM32_PINMUX('E', 9, AF12)>, /* D06 */
 148                                  <STM32_PINMUX('E', 8, AF12)>, /* D05 */
 149                                  <STM32_PINMUX('E', 7, AF12)>, /* D04 */
 150                                  <STM32_PINMUX('D', 1, AF12)>, /* D03 */
 151                                  <STM32_PINMUX('D', 0, AF12)>, /* D02 */
 152                                  <STM32_PINMUX('D',15, AF12)>, /* D01 */
 153                                  <STM32_PINMUX('D',14, AF12)>, /* D00 */
 154
 155                                  <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
 156                                  <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
 157
 158                                  <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
 159                                  <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
 160
 161                                  <STM32_PINMUX('G', 1, AF12)>, /* A11 */
 162                                  <STM32_PINMUX('G', 0, AF12)>, /* A10 */
 163                                  <STM32_PINMUX('F',15, AF12)>, /* A09 */
 164                                  <STM32_PINMUX('F',14, AF12)>, /* A08 */
 165                                  <STM32_PINMUX('F',13, AF12)>, /* A07 */
 166                                  <STM32_PINMUX('F',12, AF12)>, /* A06 */
 167                                  <STM32_PINMUX('F', 5, AF12)>, /* A05 */
 168                                  <STM32_PINMUX('F', 4, AF12)>, /* A04 */
 169                                  <STM32_PINMUX('F', 3, AF12)>, /* A03 */
 170                                  <STM32_PINMUX('F', 2, AF12)>, /* A02 */
 171                                  <STM32_PINMUX('F', 1, AF12)>, /* A01 */
 172                                  <STM32_PINMUX('F', 0, AF12)>, /* A00 */
 173
 174                                  <STM32_PINMUX('B', 6, AF12)>, /* SDNE1 */
 175                                  <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
 176                                  <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
 177                                  <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
 178                                  <STM32_PINMUX('B', 5, AF12)>, /* SDCKE1 */
 179                                  <STM32_PINMUX('G', 8, AF12)>; /* SDCLK */
 180                         slew-rate = <2>;
 181                         bootph-all;
 182                 };
 183         };
 184 };
 185
 186 &pwrcfg {
 187         bootph-all;
 188 };
 189
 190 &rcc {
 191         bootph-all;
 192 };
 193
 194 &timers5 {
 195         bootph-all;
 196 };