1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Intel Corporation
6 #include "socfpga_stratix10.dtsi"
9 model = "SoCFPGA Stratix 10 SoCDK";
18 stdout-path = "serial0:115200n8";
22 compatible = "gpio-leds";
25 gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
30 gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
35 gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
42 device_type = "memory";
44 reg = <0 0x00000000 0 0x80000000>,
45 <1 0x80000000 0 0x80000000>;
59 max-frame-size = <3800>;
64 compatible = "snps,dwmac-mdio";
65 phy0: ethernet-phy@0 {
68 txd0-skew-ps = <0>; /* -420ps */
69 txd1-skew-ps = <0>; /* -420ps */
70 txd2-skew-ps = <0>; /* -420ps */
71 txd3-skew-ps = <0>; /* -420ps */
72 rxd0-skew-ps = <420>; /* 0ps */
73 rxd1-skew-ps = <420>; /* 0ps */
74 rxd2-skew-ps = <420>; /* 0ps */
75 rxd3-skew-ps = <420>; /* 0ps */
76 txen-skew-ps = <0>; /* -420ps */
77 txc-skew-ps = <900>; /* 0ps */
78 rxdv-skew-ps = <420>; /* 0ps */
79 rxc-skew-ps = <1680>; /* 780ps */
100 #address-cells = <1>;
102 compatible = "n25q00a";
104 spi-max-frequency = <50000000>;
107 cdns,page-size = <256>;
108 cdns,block-size = <16>;
109 cdns,read-delay = <1>;
110 cdns,tshsl-ns = <50>;
111 cdns,tsd2d-ns = <50>;
116 compatible = "fixed-partitions";
117 #address-cells = <1>;
120 qspi_boot: partition@0 {
121 label = "Boot and fpga data";
122 reg = <0x0 0x4000000>;
125 qspi_rootfs: partition@4000000 {
126 label = "Root Filesystem - JFFS2";
127 reg = <0x4000000 0x4000000>;