arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
   2 /*
   3  * U-Boot additions
   4  *
   5  * Copyright (C) 2015 Marek Vasut <marex@denx.de>
   6  * Copyright (c) 2018 Simon Goldschmidt
   7  */
   8
   9 #include "socfpga-common-u-boot.dtsi"
  10
  11 /{
  12         aliases {
  13                 spi0 = "/soc/spi@ff705000";
  14                 udc0 = &usb1;
  15         };
  16 };
  17
  18 &mmc {
  19         status = "disabled";
  20 };
  21
  22 &qspi {
  23         bootph-all;
  24
  25         n25q128@0 {
  26                 compatible = "n25q128", "jedec,spi-nor";
  27                 bootph-all;
  28         };
  29         n25q00@1 {
  30                 compatible = "n25q00", "jedec,spi-nor";
  31                 bootph-all;
  32         };
  33 };
  34
  35 &uart0 {
  36         clock-frequency = <100000000>;
  37         bootph-all;
  38 };
  39
  40 &uart1 {
  41         clock-frequency = <100000000>;
  42 };
  43
  44 &porta {
  45         bank-name = "porta";
  46 };
  47
  48 &portb {
  49         bank-name = "portb";
  50 };
  51
  52 &portc {
  53         bank-name = "portc";
  54 };
  55
  56 &watchdog0 {
  57         bootph-all;
  58 };