arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright (C) 2016-2017 Intel Corporation
   4  *
   5  *<auto-generated>
   6  *      This code was generated by a tool based on
   7  *      handoffs from both Qsys and Quartus.
   8  *
   9  *      Changes to this file may be lost if
  10  *      the code is regenerated.
  11  *</auto-generated>
  12  */
  13
  14 / {
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17         model = "SOCFPGA Arria10 Dev Kit";      /* Bootloader setting: uboot.model */
  18
  19         chosen {
  20                 cff-file = "socfpga.rbf";       /* Bootloader setting: uboot.rbf_filename */
  21         };
  22
  23         /* Clock sources */
  24         clocks {
  25                 #address-cells = <1>;
  26                 #size-cells = <1>;
  27
  28                 /* Clock source: altera_arria10_hps_eosc1 */
  29                 altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
  30                         compatible = "fixed-clock";
  31                         #clock-cells = <0>;
  32                         clock-frequency = <25000000>;
  33                         clock-output-names = "altera_arria10_hps_eosc1-clk";
  34                 };
  35
  36                 /* Clock source: altera_arria10_hps_cb_intosc_ls */
  37                 altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
  38                         compatible = "fixed-clock";
  39                         #clock-cells = <0>;
  40                         clock-frequency = <60000000>;
  41                         clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
  42                 };
  43
  44                 /* Clock source: altera_arria10_hps_f2h_free */
  45                 altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
  46                         compatible = "fixed-clock";
  47                         #clock-cells = <0>;
  48                         clock-frequency = <200000000>;
  49                         clock-output-names = "altera_arria10_hps_f2h_free-clk";
  50                 };
  51         };
  52
  53         /*
  54          * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver
  55          * Version: 1.0
  56          * Binding: device
  57          */
  58         i_clk_mgr: clock_manager@0xffd04000 {
  59                 compatible = "altr,socfpga-a10-clk-init";
  60                 reg = <0xffd04000 0x00000200>;
  61                 reg-names = "soc_clock_manager_OCP_SLV";
  62
  63                 /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
  64                 mainpll {
  65                         vco0-psrc = <0>;        /* Field: vco0.psrc */
  66                         vco1-denom = <1>;       /* Field: vco1.denom */
  67                         vco1-numer = <191>;     /* Field: vco1.numer */
  68                         mpuclk-cnt = <0>;       /* Field: mpuclk.cnt */
  69                         mpuclk-src = <0>;       /* Field: mpuclk.src */
  70                         nocclk-cnt = <0>;       /* Field: nocclk.cnt */
  71                         nocclk-src = <0>;       /* Field: nocclk.src */
  72                         cntr2clk-cnt = <900>;   /* Field: cntr2clk.cnt */
  73                         cntr3clk-cnt = <900>;   /* Field: cntr3clk.cnt */
  74                         cntr4clk-cnt = <900>;   /* Field: cntr4clk.cnt */
  75                         cntr5clk-cnt = <900>;   /* Field: cntr5clk.cnt */
  76                         cntr6clk-cnt = <900>;   /* Field: cntr6clk.cnt */
  77                         cntr7clk-cnt = <900>;   /* Field: cntr7clk.cnt */
  78                         cntr7clk-src = <0>;     /* Field: cntr7clk.src */
  79                         cntr8clk-cnt = <900>;   /* Field: cntr8clk.cnt */
  80                         cntr9clk-cnt = <900>;   /* Field: cntr9clk.cnt */
  81                         cntr9clk-src = <0>;     /* Field: cntr9clk.src */
  82                         cntr15clk-cnt = <900>;  /* Field: cntr15clk.cnt */
  83                         nocdiv-l4mainclk = <0>; /* Field: nocdiv.l4mainclk */
  84                         nocdiv-l4mpclk = <0>;   /* Field: nocdiv.l4mpclk */
  85                         nocdiv-l4spclk = <2>;   /* Field: nocdiv.l4spclk */
  86                         nocdiv-csatclk = <0>;   /* Field: nocdiv.csatclk */
  87                         nocdiv-cstraceclk = <1>;        /* Field: nocdiv.cstraceclk */
  88                         nocdiv-cspdbgclk = <1>; /* Field: nocdiv.cspdbgclk */
  89                 };
  90
  91                 /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
  92                 perpll {
  93                         vco0-psrc = <0>;        /* Field: vco0.psrc */
  94                         vco1-denom = <1>;       /* Field: vco1.denom */
  95                         vco1-numer = <159>;     /* Field: vco1.numer */
  96                         cntr2clk-cnt = <7>;     /* Field: cntr2clk.cnt */
  97                         cntr2clk-src = <1>;     /* Field: cntr2clk.src */
  98                         cntr3clk-cnt = <900>;   /* Field: cntr3clk.cnt */
  99                         cntr3clk-src = <1>;     /* Field: cntr3clk.src */
 100                         cntr4clk-cnt = <19>;    /* Field: cntr4clk.cnt */
 101                         cntr4clk-src = <1>;     /* Field: cntr4clk.src */
 102                         cntr5clk-cnt = <499>;   /* Field: cntr5clk.cnt */
 103                         cntr5clk-src = <1>;     /* Field: cntr5clk.src */
 104                         cntr6clk-cnt = <9>;     /* Field: cntr6clk.cnt */
 105                         cntr6clk-src = <1>;     /* Field: cntr6clk.src */
 106                         cntr7clk-cnt = <900>;   /* Field: cntr7clk.cnt */
 107                         cntr8clk-cnt = <900>;   /* Field: cntr8clk.cnt */
 108                         cntr8clk-src = <0>;     /* Field: cntr8clk.src */
 109                         cntr9clk-cnt = <900>;   /* Field: cntr9clk.cnt */
 110                         emacctl-emac0sel = <0>; /* Field: emacctl.emac0sel */
 111                         emacctl-emac1sel = <0>; /* Field: emacctl.emac1sel */
 112                         emacctl-emac2sel = <0>; /* Field: emacctl.emac2sel */
 113                         gpiodiv-gpiodbclk = <32000>;    /* Field: gpiodiv.gpiodbclk */
 114                 };
 115
 116                 /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
 117                 alteragrp {
 118                         nocclk = <0x0384000b>;  /* Register: nocclk */
 119                         mpuclk = <0x03840001>;  /* Register: mpuclk */
 120                 };
 121         };
 122
 123         /*
 124          * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
 125          * Version: 1.0
 126          * Binding: pinmux
 127          */
 128         i_io48_pin_mux: pinmux@0xffd07000 {
 129                 #address-cells = <1>;
 130                 #size-cells = <1>;
 131                 compatible = "pinctrl-single";
 132                 reg = <0xffd07000 0x00000800>;
 133                 reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
 134
 135                 /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
 136                 shared {
 137                         reg = <0xffd07000 0x00000200>;
 138                         pinctrl-single,register-width = <32>;
 139                         pinctrl-single,function-mask = <0x0000000f>;
 140                         pinctrl-single,pins =
 141                                 <0x00000000 0x00000008>,        /* Register: pinmux_shared_io_q1_1 */
 142                                 <0x00000004 0x00000008>,        /* Register: pinmux_shared_io_q1_2 */
 143                                 <0x00000008 0x00000008>,        /* Register: pinmux_shared_io_q1_3 */
 144                                 <0x0000000c 0x00000008>,        /* Register: pinmux_shared_io_q1_4 */
 145                                 <0x00000010 0x00000008>,        /* Register: pinmux_shared_io_q1_5 */
 146                                 <0x00000014 0x00000008>,        /* Register: pinmux_shared_io_q1_6 */
 147                                 <0x00000018 0x00000008>,        /* Register: pinmux_shared_io_q1_7 */
 148                                 <0x0000001c 0x00000008>,        /* Register: pinmux_shared_io_q1_8 */
 149                                 <0x00000020 0x00000008>,        /* Register: pinmux_shared_io_q1_9 */
 150                                 <0x00000024 0x00000008>,        /* Register: pinmux_shared_io_q1_10 */
 151                                 <0x00000028 0x00000008>,        /* Register: pinmux_shared_io_q1_11 */
 152                                 <0x0000002c 0x00000008>,        /* Register: pinmux_shared_io_q1_12 */
 153                                 <0x00000030 0x00000004>,        /* Register: pinmux_shared_io_q2_1 */
 154                                 <0x00000034 0x00000004>,        /* Register: pinmux_shared_io_q2_2 */
 155                                 <0x00000038 0x00000004>,        /* Register: pinmux_shared_io_q2_3 */
 156                                 <0x0000003c 0x00000004>,        /* Register: pinmux_shared_io_q2_4 */
 157                                 <0x00000040 0x00000004>,        /* Register: pinmux_shared_io_q2_5 */
 158                                 <0x00000044 0x00000004>,        /* Register: pinmux_shared_io_q2_6 */
 159                                 <0x00000048 0x00000004>,        /* Register: pinmux_shared_io_q2_7 */
 160                                 <0x0000004c 0x00000004>,        /* Register: pinmux_shared_io_q2_8 */
 161                                 <0x00000050 0x00000004>,        /* Register: pinmux_shared_io_q2_9 */
 162                                 <0x00000054 0x00000004>,        /* Register: pinmux_shared_io_q2_10 */
 163                                 <0x00000058 0x00000004>,        /* Register: pinmux_shared_io_q2_11 */
 164                                 <0x0000005c 0x00000004>,        /* Register: pinmux_shared_io_q2_12 */
 165                                 <0x00000060 0x00000003>,        /* Register: pinmux_shared_io_q3_1 */
 166                                 <0x00000064 0x00000003>,        /* Register: pinmux_shared_io_q3_2 */
 167                                 <0x00000068 0x00000003>,        /* Register: pinmux_shared_io_q3_3 */
 168                                 <0x0000006c 0x00000003>,        /* Register: pinmux_shared_io_q3_4 */
 169                                 <0x00000070 0x00000003>,        /* Register: pinmux_shared_io_q3_5 */
 170                                 <0x00000074 0x0000000f>,        /* Register: pinmux_shared_io_q3_6 */
 171                                 <0x00000078 0x0000000a>,        /* Register: pinmux_shared_io_q3_7 */
 172                                 <0x0000007c 0x0000000a>,        /* Register: pinmux_shared_io_q3_8 */
 173                                 <0x00000080 0x0000000a>,        /* Register: pinmux_shared_io_q3_9 */
 174                                 <0x00000084 0x0000000a>,        /* Register: pinmux_shared_io_q3_10 */
 175                                 <0x00000088 0x00000001>,        /* Register: pinmux_shared_io_q3_11 */
 176                                 <0x0000008c 0x00000001>,        /* Register: pinmux_shared_io_q3_12 */
 177                                 <0x00000090 0x00000000>,        /* Register: pinmux_shared_io_q4_1 */
 178                                 <0x00000094 0x00000000>,        /* Register: pinmux_shared_io_q4_2 */
 179                                 <0x00000098 0x0000000f>,        /* Register: pinmux_shared_io_q4_3 */
 180                                 <0x0000009c 0x0000000c>,        /* Register: pinmux_shared_io_q4_4 */
 181                                 <0x000000a0 0x0000000f>,        /* Register: pinmux_shared_io_q4_5 */
 182                                 <0x000000a4 0x0000000f>,        /* Register: pinmux_shared_io_q4_6 */
 183                                 <0x000000a8 0x0000000a>,        /* Register: pinmux_shared_io_q4_7 */
 184                                 <0x000000ac 0x0000000a>,        /* Register: pinmux_shared_io_q4_8 */
 185                                 <0x000000b0 0x0000000c>,        /* Register: pinmux_shared_io_q4_9 */
 186                                 <0x000000b4 0x0000000c>,        /* Register: pinmux_shared_io_q4_10 */
 187                                 <0x000000b8 0x0000000c>,        /* Register: pinmux_shared_io_q4_11 */
 188                                 <0x000000bc 0x0000000c>;        /* Register: pinmux_shared_io_q4_12 */
 189                 };
 190
 191                 /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
 192                 dedicated {
 193                         reg = <0xffd07200 0x00000200>;
 194                         pinctrl-single,register-width = <32>;
 195                         pinctrl-single,function-mask = <0x0000000f>;
 196                         pinctrl-single,pins =
 197                                 <0x0000000c 0x00000008>,        /* Register: pinmux_dedicated_io_4 */
 198                                 <0x00000010 0x00000008>,        /* Register: pinmux_dedicated_io_5 */
 199                                 <0x00000014 0x00000008>,        /* Register: pinmux_dedicated_io_6 */
 200                                 <0x00000018 0x00000008>,        /* Register: pinmux_dedicated_io_7 */
 201                                 <0x0000001c 0x00000008>,        /* Register: pinmux_dedicated_io_8 */
 202                                 <0x00000020 0x00000008>,        /* Register: pinmux_dedicated_io_9 */
 203                                 <0x00000024 0x0000000a>,        /* Register: pinmux_dedicated_io_10 */
 204                                 <0x00000028 0x0000000a>,        /* Register: pinmux_dedicated_io_11 */
 205                                 <0x0000002c 0x00000008>,        /* Register: pinmux_dedicated_io_12 */
 206                                 <0x00000030 0x00000008>,        /* Register: pinmux_dedicated_io_13 */
 207                                 <0x00000034 0x00000008>,        /* Register: pinmux_dedicated_io_14 */
 208                                 <0x00000038 0x00000008>,        /* Register: pinmux_dedicated_io_15 */
 209                                 <0x0000003c 0x0000000d>,        /* Register: pinmux_dedicated_io_16 */
 210                                 <0x00000040 0x0000000d>;        /* Register: pinmux_dedicated_io_17 */
 211                 };
 212
 213                 /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
 214                 dedicated_cfg {
 215                         reg = <0xffd07200 0x00000200>;
 216                         pinctrl-single,register-width = <32>;
 217                         pinctrl-single,function-mask = <0x003f3f3f>;
 218                         pinctrl-single,pins =
 219                                 <0x00000100 0x00000101>,        /* Register: configuration_dedicated_io_bank */
 220                                 <0x00000104 0x000b080a>,        /* Register: configuration_dedicated_io_1 */
 221                                 <0x00000108 0x000b080a>,        /* Register: configuration_dedicated_io_2 */
 222                                 <0x0000010c 0x000b080a>,        /* Register: configuration_dedicated_io_3 */
 223                                 <0x00000110 0x000a282a>,        /* Register: configuration_dedicated_io_4 */
 224                                 <0x00000114 0x000a282a>,        /* Register: configuration_dedicated_io_5 */
 225                                 <0x00000118 0x0008282a>,        /* Register: configuration_dedicated_io_6 */
 226                                 <0x0000011c 0x000a282a>,        /* Register: configuration_dedicated_io_7 */
 227                                 <0x00000120 0x000a282a>,        /* Register: configuration_dedicated_io_8 */
 228                                 <0x00000124 0x000a282a>,        /* Register: configuration_dedicated_io_9 */
 229                                 <0x00000128 0x00090000>,        /* Register: configuration_dedicated_io_10 */
 230                                 <0x0000012c 0x00090000>,        /* Register: configuration_dedicated_io_11 */
 231                                 <0x00000130 0x000b282a>,        /* Register: configuration_dedicated_io_12 */
 232                                 <0x00000134 0x000b282a>,        /* Register: configuration_dedicated_io_13 */
 233                                 <0x00000138 0x000b282a>,        /* Register: configuration_dedicated_io_14 */
 234                                 <0x0000013c 0x000b282a>,        /* Register: configuration_dedicated_io_15 */
 235                                 <0x00000140 0x0008282a>,        /* Register: configuration_dedicated_io_16 */
 236                                 <0x00000144 0x000a282a>;        /* Register: configuration_dedicated_io_17 */
 237                 };
 238
 239                 /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
 240                 fpga {
 241                         reg = <0xffd07400 0x00000100>;
 242                         pinctrl-single,register-width = <32>;
 243                         pinctrl-single,function-mask = <0x00000001>;
 244                         pinctrl-single,pins =
 245                                 <0x00000000 0x00000000>,        /* Register: pinmux_emac0_usefpga */
 246                                 <0x00000004 0x00000000>,        /* Register: pinmux_emac1_usefpga */
 247                                 <0x00000008 0x00000000>,        /* Register: pinmux_emac2_usefpga */
 248                                 <0x0000000c 0x00000000>,        /* Register: pinmux_i2c0_usefpga */
 249                                 <0x00000010 0x00000000>,        /* Register: pinmux_i2c1_usefpga */
 250                                 <0x00000014 0x00000000>,        /* Register: pinmux_i2c_emac0_usefpga */
 251                                 <0x00000018 0x00000000>,        /* Register: pinmux_i2c_emac1_usefpga */
 252                                 <0x0000001c 0x00000000>,        /* Register: pinmux_i2c_emac2_usefpga */
 253                                 <0x00000020 0x00000000>,        /* Register: pinmux_nand_usefpga */
 254                                 <0x00000024 0x00000000>,        /* Register: pinmux_qspi_usefpga */
 255                                 <0x00000028 0x00000000>,        /* Register: pinmux_sdmmc_usefpga */
 256                                 <0x0000002c 0x00000000>,        /* Register: pinmux_spim0_usefpga */
 257                                 <0x00000030 0x00000000>,        /* Register: pinmux_spim1_usefpga */
 258                                 <0x00000034 0x00000000>,        /* Register: pinmux_spis0_usefpga */
 259                                 <0x00000038 0x00000000>,        /* Register: pinmux_spis1_usefpga */
 260                                 <0x0000003c 0x00000000>,        /* Register: pinmux_uart0_usefpga */
 261                                 <0x00000040 0x00000000>;        /* Register: pinmux_uart1_usefpga */
 262                 };
 263         };
 264
 265         /*
 266          * Driver: altera_arria10_soc_noc_arria10_uboot_driver
 267          * Version: 1.0
 268          * Binding: device
 269          */
 270         i_noc: noc@0xffd10000 {
 271                 compatible = "altr,socfpga-a10-noc";
 272                 reg = <0xffd10000 0x00008000>;
 273                 reg-names = "mpu_m0";
 274
 275                 firewall {
 276                         /*
 277                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
 278                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
 279                          */
 280                         mpu0 = <0x00000000 0x0000ffff>;
 281                         /*
 282                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base
 283                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit
 284                          */
 285                         l3-0 = <0x00000000 0x0000ffff>;
 286                         /*
 287                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base
 288                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit
 289                          */
 290                         fpga2sdram0-0 = <0x00000000 0x0000ffff>;
 291                         /*
 292                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base
 293                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit
 294                          */
 295                         fpga2sdram1-0 = <0x00000000 0x0000ffff>;
 296                         /*
 297                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base
 298                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit
 299                          */
 300                         fpga2sdram2-0 = <0x00000000 0x0000ffff>;
 301                 };
 302         };
 303
 304         hps_fpgabridge0: fpgabridge@0 {
 305                 compatible = "altr,socfpga-hps2fpga-bridge";
 306                 init-val = <1>;
 307         };
 308
 309         hps_fpgabridge1: fpgabridge@1 {
 310                 compatible = "altr,socfpga-lwhps2fpga-bridge";
 311                 init-val = <1>;
 312         };
 313
 314         hps_fpgabridge2: fpgabridge@2 {
 315                 compatible = "altr,socfpga-fpga2hps-bridge";
 316                 init-val = <1>;
 317         };
 318
 319         hps_fpgabridge3: fpgabridge@3 {
 320                 compatible = "altr,socfpga-fpga2sdram0-bridge";
 321                 init-val = <1>;
 322         };
 323
 324         hps_fpgabridge4: fpgabridge@4 {
 325                 compatible = "altr,socfpga-fpga2sdram1-bridge";
 326                 init-val = <0>;
 327         };
 328
 329         hps_fpgabridge5: fpgabridge@5 {
 330                 compatible = "altr,socfpga-fpga2sdram2-bridge";
 331                 init-val = <1>;
 332         };
 333 };