2 * Copyright Altera Corporation (C) 2014. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
27 enable-method = "altr,socfpga-a10-smp";
30 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
36 compatible = "arm,cortex-a9";
39 next-level-cache = <&L2>;
44 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>;
47 reg = <0xffffd000 0x1000>,
54 compatible = "simple-bus";
56 interrupt-parent = <&intc>;
60 compatible = "simple-bus";
66 compatible = "arm,pl330", "arm,primecell";
67 reg = <0xffda1000 0x1000>;
68 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
69 <0 84 IRQ_TYPE_LEVEL_HIGH>,
70 <0 85 IRQ_TYPE_LEVEL_HIGH>,
71 <0 86 IRQ_TYPE_LEVEL_HIGH>,
72 <0 87 IRQ_TYPE_LEVEL_HIGH>,
73 <0 88 IRQ_TYPE_LEVEL_HIGH>,
74 <0 89 IRQ_TYPE_LEVEL_HIGH>,
75 <0 90 IRQ_TYPE_LEVEL_HIGH>,
76 <0 91 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&l4_main_clk>;
81 clock-names = "apb_pclk";
86 #address-cells = <0x1>;
89 compatible = "fpga-region";
90 fpga-mgr = <&fpga_mgr>;
94 compatible = "altr,clk-mgr";
95 reg = <0xffd04000 0x1000>;
101 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
103 compatible = "fixed-clock";
106 cb_intosc_ls_clk: cb_intosc_ls_clk {
108 compatible = "fixed-clock";
111 f2s_free_clk: f2s_free_clk {
113 compatible = "fixed-clock";
118 compatible = "fixed-clock";
121 main_pll: main_pll@40 {
122 #address-cells = <1>;
125 compatible = "altr,socfpga-a10-pll-clock";
126 clocks = <&osc1>, <&cb_intosc_ls_clk>,
130 main_mpu_base_clk: main_mpu_base_clk {
132 compatible = "altr,socfpga-a10-perip-clk";
133 clocks = <&main_pll>;
134 div-reg = <0x140 0 11>;
137 main_noc_base_clk: main_noc_base_clk {
139 compatible = "altr,socfpga-a10-perip-clk";
140 clocks = <&main_pll>;
141 div-reg = <0x144 0 11>;
144 main_emaca_clk: main_emaca_clk@68 {
146 compatible = "altr,socfpga-a10-perip-clk";
147 clocks = <&main_pll>;
151 main_emacb_clk: main_emacb_clk@6c {
153 compatible = "altr,socfpga-a10-perip-clk";
154 clocks = <&main_pll>;
158 main_emac_ptp_clk: main_emac_ptp_clk@70 {
160 compatible = "altr,socfpga-a10-perip-clk";
161 clocks = <&main_pll>;
165 main_gpio_db_clk: main_gpio_db_clk@74 {
167 compatible = "altr,socfpga-a10-perip-clk";
168 clocks = <&main_pll>;
172 main_sdmmc_clk: main_sdmmc_clk@78 {
174 compatible = "altr,socfpga-a10-perip-clk"
176 clocks = <&main_pll>;
180 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
182 compatible = "altr,socfpga-a10-perip-clk";
183 clocks = <&main_pll>;
187 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
189 compatible = "altr,socfpga-a10-perip-clk";
190 clocks = <&main_pll>;
194 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
196 compatible = "altr,socfpga-a10-perip-clk";
197 clocks = <&main_pll>;
201 main_periph_ref_clk: main_periph_ref_clk@9c {
203 compatible = "altr,socfpga-a10-perip-clk";
204 clocks = <&main_pll>;
209 periph_pll: periph_pll@c0 {
210 #address-cells = <1>;
213 compatible = "altr,socfpga-a10-pll-clock";
214 clocks = <&osc1>, <&cb_intosc_ls_clk>,
215 <&f2s_free_clk>, <&main_periph_ref_clk>;
218 peri_mpu_base_clk: peri_mpu_base_clk {
220 compatible = "altr,socfpga-a10-perip-clk";
221 clocks = <&periph_pll>;
222 div-reg = <0x140 16 11>;
225 peri_noc_base_clk: peri_noc_base_clk {
227 compatible = "altr,socfpga-a10-perip-clk";
228 clocks = <&periph_pll>;
229 div-reg = <0x144 16 11>;
232 peri_emaca_clk: peri_emaca_clk@e8 {
234 compatible = "altr,socfpga-a10-perip-clk";
235 clocks = <&periph_pll>;
239 peri_emacb_clk: peri_emacb_clk@ec {
241 compatible = "altr,socfpga-a10-perip-clk";
242 clocks = <&periph_pll>;
246 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
248 compatible = "altr,socfpga-a10-perip-clk";
249 clocks = <&periph_pll>;
253 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
255 compatible = "altr,socfpga-a10-perip-clk";
256 clocks = <&periph_pll>;
260 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
262 compatible = "altr,socfpga-a10-perip-clk";
263 clocks = <&periph_pll>;
267 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
269 compatible = "altr,socfpga-a10-perip-clk";
270 clocks = <&periph_pll>;
274 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
276 compatible = "altr,socfpga-a10-perip-clk";
277 clocks = <&periph_pll>;
281 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
283 compatible = "altr,socfpga-a10-perip-clk";
284 clocks = <&periph_pll>;
289 mpu_free_clk: mpu_free_clk@60 {
291 compatible = "altr,socfpga-a10-perip-clk";
292 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
293 <&osc1>, <&cb_intosc_hs_div2_clk>,
298 noc_free_clk: noc_free_clk@64 {
300 compatible = "altr,socfpga-a10-perip-clk";
301 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
302 <&osc1>, <&cb_intosc_hs_div2_clk>,
307 s2f_user1_free_clk: s2f_user1_free_clk@104 {
309 compatible = "altr,socfpga-a10-perip-clk";
310 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
311 <&osc1>, <&cb_intosc_hs_div2_clk>,
316 sdmmc_free_clk: sdmmc_free_clk@f8 {
318 compatible = "altr,socfpga-a10-perip-clk";
319 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
320 <&osc1>, <&cb_intosc_hs_div2_clk>,
326 l4_sys_free_clk: l4_sys_free_clk {
328 compatible = "altr,socfpga-a10-perip-clk";
329 clocks = <&noc_free_clk>;
333 l4_main_clk: l4_main_clk {
335 compatible = "altr,socfpga-a10-gate-clk";
336 clocks = <&noc_free_clk>;
337 div-reg = <0xA8 0 2>;
341 l4_mp_clk: l4_mp_clk {
343 compatible = "altr,socfpga-a10-gate-clk";
344 clocks = <&noc_free_clk>;
345 div-reg = <0xA8 8 2>;
349 l4_sp_clk: l4_sp_clk {
351 compatible = "altr,socfpga-a10-gate-clk";
352 clocks = <&noc_free_clk>;
353 div-reg = <0xA8 16 2>;
357 mpu_periph_clk: mpu_periph_clk {
359 compatible = "altr,socfpga-a10-gate-clk";
360 clocks = <&mpu_free_clk>;
365 sdmmc_clk: sdmmc_clk {
367 compatible = "altr,socfpga-a10-gate-clk";
368 clocks = <&sdmmc_free_clk>;
375 compatible = "altr,socfpga-a10-gate-clk";
376 clocks = <&l4_main_clk>;
377 clk-gate = <0xC8 11>;
382 compatible = "altr,socfpga-a10-gate-clk";
383 clocks = <&l4_mp_clk>;
384 clk-gate = <0xC8 10>;
387 spi_m_clk: spi_m_clk {
389 compatible = "altr,socfpga-a10-gate-clk";
390 clocks = <&l4_main_clk>;
396 compatible = "altr,socfpga-a10-gate-clk";
397 clocks = <&l4_mp_clk>;
401 s2f_usr1_clk: s2f_usr1_clk {
403 compatible = "altr,socfpga-a10-gate-clk";
404 clocks = <&peri_s2f_usr1_clk>;
410 socfpga_axi_setup: stmmac-axi-config {
411 snps,wr_osr_lmt = <0xf>;
412 snps,rd_osr_lmt = <0xf>;
413 snps,blen = <0 0 0 0 16 0 0>;
416 gmac0: ethernet@ff800000 {
417 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
418 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
419 reg = <0xff800000 0x2000>;
420 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
421 interrupt-names = "macirq";
422 /* Filled in by bootloader */
423 mac-address = [00 00 00 00 00 00];
424 snps,multicast-filter-bins = <256>;
425 snps,perfect-filter-entries = <128>;
426 tx-fifo-depth = <4096>;
427 rx-fifo-depth = <16384>;
428 clocks = <&l4_mp_clk>;
429 clock-names = "stmmaceth";
430 resets = <&rst EMAC0_RESET>;
431 reset-names = "stmmaceth";
432 snps,axi-config = <&socfpga_axi_setup>;
436 gmac1: ethernet@ff802000 {
437 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
438 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
439 reg = <0xff802000 0x2000>;
440 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
441 interrupt-names = "macirq";
442 /* Filled in by bootloader */
443 mac-address = [00 00 00 00 00 00];
444 snps,multicast-filter-bins = <256>;
445 snps,perfect-filter-entries = <128>;
446 tx-fifo-depth = <4096>;
447 rx-fifo-depth = <16384>;
448 clocks = <&l4_mp_clk>;
449 clock-names = "stmmaceth";
450 resets = <&rst EMAC1_RESET>;
451 reset-names = "stmmaceth";
452 snps,axi-config = <&socfpga_axi_setup>;
456 gmac2: ethernet@ff804000 {
457 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
458 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
459 reg = <0xff804000 0x2000>;
460 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-names = "macirq";
462 /* Filled in by bootloader */
463 mac-address = [00 00 00 00 00 00];
464 snps,multicast-filter-bins = <256>;
465 snps,perfect-filter-entries = <128>;
466 tx-fifo-depth = <4096>;
467 rx-fifo-depth = <16384>;
468 clocks = <&l4_mp_clk>;
469 clock-names = "stmmaceth";
470 snps,axi-config = <&socfpga_axi_setup>;
474 gpio0: gpio@ffc02900 {
475 #address-cells = <1>;
477 compatible = "snps,dw-apb-gpio";
478 reg = <0xffc02900 0x100>;
481 porta: gpio-controller@0 {
482 compatible = "snps,dw-apb-gpio-port";
486 snps,nr-gpios = <29>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
490 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
494 gpio1: gpio@ffc02a00 {
495 #address-cells = <1>;
497 compatible = "snps,dw-apb-gpio";
498 reg = <0xffc02a00 0x100>;
501 portb: gpio-controller@0 {
502 compatible = "snps,dw-apb-gpio-port";
506 snps,nr-gpios = <29>;
508 interrupt-controller;
509 #interrupt-cells = <2>;
510 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
514 gpio2: gpio@ffc02b00 {
515 #address-cells = <1>;
517 compatible = "snps,dw-apb-gpio";
518 reg = <0xffc02b00 0x100>;
521 portc: gpio-controller@0 {
522 compatible = "snps,dw-apb-gpio-port";
526 snps,nr-gpios = <27>;
528 interrupt-controller;
529 #interrupt-cells = <2>;
530 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
534 fpga_mgr: fpga-mgr@ffd03000 {
535 compatible = "altr,socfpga-a10-fpga-mgr";
536 reg = <0xffd03000 0x100
538 clocks = <&l4_mp_clk>;
539 resets = <&rst FPGAMGR_RESET>;
540 reset-names = "fpgamgr";
544 #address-cells = <1>;
546 compatible = "snps,designware-i2c";
547 reg = <0xffc02200 0x100>;
548 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&l4_sp_clk>;
554 #address-cells = <1>;
556 compatible = "snps,designware-i2c";
557 reg = <0xffc02300 0x100>;
558 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&l4_sp_clk>;
564 #address-cells = <1>;
566 compatible = "snps,designware-i2c";
567 reg = <0xffc02400 0x100>;
568 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&l4_sp_clk>;
574 #address-cells = <1>;
576 compatible = "snps,designware-i2c";
577 reg = <0xffc02500 0x100>;
578 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&l4_sp_clk>;
584 #address-cells = <1>;
586 compatible = "snps,designware-i2c";
587 reg = <0xffc02600 0x100>;
588 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&l4_sp_clk>;
594 compatible = "snps,dw-apb-ssi";
595 #address-cells = <1>;
597 reg = <0xffda5000 0x100>;
598 interrupts = <0 102 4>;
599 num-chipselect = <4>;
602 tx-dma-channel = <&pdma 16>;
603 rx-dma-channel = <&pdma 17>;
604 clocks = <&spi_m_clk>;
609 compatible = "altr,sdr-ctl", "syscon";
610 reg = <0xffcfb100 0x80>;
613 L2: l2-cache@fffff000 {
614 compatible = "arm,pl310-cache";
615 reg = <0xfffff000 0x1000>;
616 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
620 prefetch-instr = <1>;
624 mmc: dwmmc0@ff808000 {
625 #address-cells = <1>;
627 compatible = "altr,socfpga-dw-mshc";
628 reg = <0xff808000 0x1000>;
629 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
630 fifo-depth = <0x400>;
631 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
632 clock-names = "biu", "ciu";
636 nand: nand@ffb90000 {
637 #address-cells = <1>;
639 compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
640 reg = <0xffb90000 0x20>,
642 reg-names = "nand_data", "denali_reg";
643 interrupts = <0 99 4>;
644 dma-mask = <0xffffffff>;
645 clocks = <&nand_clk>;
649 ocram: sram@ffe00000 {
650 compatible = "mmio-sram";
651 reg = <0xffe00000 0x40000>;
655 compatible = "altr,socfpga-a10-ecc-manager";
656 altr,sysmgr-syscon = <&sysmgr>;
657 #address-cells = <1>;
659 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
660 <0 0 IRQ_TYPE_LEVEL_HIGH>;
661 interrupt-controller;
662 #interrupt-cells = <2>;
666 compatible = "altr,sdram-edac-a10";
667 altr,sdr-syscon = <&sdr>;
668 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
669 <49 IRQ_TYPE_LEVEL_HIGH>;
673 compatible = "altr,socfpga-a10-l2-ecc";
674 reg = <0xffd06010 0x4>;
675 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
676 <32 IRQ_TYPE_LEVEL_HIGH>;
680 compatible = "altr,socfpga-a10-ocram-ecc";
681 reg = <0xff8c3000 0x400>;
682 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
683 <33 IRQ_TYPE_LEVEL_HIGH>;
686 emac0-rx-ecc@ff8c0800 {
687 compatible = "altr,socfpga-eth-mac-ecc";
688 reg = <0xff8c0800 0x400>;
689 altr,ecc-parent = <&gmac0>;
690 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
691 <36 IRQ_TYPE_LEVEL_HIGH>;
694 emac0-tx-ecc@ff8c0c00 {
695 compatible = "altr,socfpga-eth-mac-ecc";
696 reg = <0xff8c0c00 0x400>;
697 altr,ecc-parent = <&gmac0>;
698 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
699 <37 IRQ_TYPE_LEVEL_HIGH>;
703 compatible = "altr,socfpga-dma-ecc";
704 reg = <0xff8c8000 0x400>;
705 altr,ecc-parent = <&pdma>;
706 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
707 <42 IRQ_TYPE_LEVEL_HIGH>;
711 compatible = "altr,socfpga-usb-ecc";
712 reg = <0xff8c8800 0x400>;
713 altr,ecc-parent = <&usb0>;
714 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
715 <34 IRQ_TYPE_LEVEL_HIGH>;
720 compatible = "cdns,qspi-nor", "cadence,qspi";
721 #address-cells = <1>;
723 reg = <0xff809000 0x100>,
724 <0xffa00000 0x100000>;
725 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
726 cdns,fifo-depth = <128>;
727 cdns,fifo-width = <4>;
728 cdns,trigger-address = <0x00000000>;
729 clocks = <&qspi_clk>;
733 rst: rstmgr@ffd05000 {
735 compatible = "altr,rst-mgr";
736 reg = <0xffd05000 0x100>;
737 altr,modrst-offset = <0x20>;
740 scu: snoop-control-unit@ffffc000 {
741 compatible = "arm,cortex-a9-scu";
742 reg = <0xffffc000 0x100>;
745 sysmgr: sysmgr@ffd06000 {
746 compatible = "altr,sys-mgr", "syscon";
747 reg = <0xffd06000 0x300>;
748 cpu1-start-addr = <0xffd06230>;
753 compatible = "arm,cortex-a9-twd-timer";
754 reg = <0xffffc600 0x100>;
755 interrupts = <1 13 0xf04>;
756 clocks = <&mpu_periph_clk>;
759 timer0: timer0@ffc02700 {
760 compatible = "snps,dw-apb-timer";
761 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
762 reg = <0xffc02700 0x100>;
763 clocks = <&l4_sp_clk>;
764 clock-names = "timer";
767 timer1: timer1@ffc02800 {
768 compatible = "snps,dw-apb-timer";
769 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
770 reg = <0xffc02800 0x100>;
771 clocks = <&l4_sp_clk>;
772 clock-names = "timer";
775 timer2: timer2@ffd00000 {
776 compatible = "snps,dw-apb-timer";
777 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
778 reg = <0xffd00000 0x100>;
779 clocks = <&l4_sys_free_clk>;
780 clock-names = "timer";
783 timer3: timer3@ffd00100 {
784 compatible = "snps,dw-apb-timer";
785 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
786 reg = <0xffd01000 0x100>;
787 clocks = <&l4_sys_free_clk>;
788 clock-names = "timer";
791 uart0: serial0@ffc02000 {
792 compatible = "snps,dw-apb-uart";
793 reg = <0xffc02000 0x100>;
794 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
797 clocks = <&l4_sp_clk>;
801 uart1: serial1@ffc02100 {
802 compatible = "snps,dw-apb-uart";
803 reg = <0xffc02100 0x100>;
804 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&l4_sp_clk>;
813 compatible = "usb-nop-xceiv";
818 compatible = "snps,dwc2";
819 reg = <0xffb00000 0xffff>;
820 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
823 resets = <&rst USB0_RESET>;
824 reset-names = "dwc2";
826 phy-names = "usb2-phy";
831 compatible = "snps,dwc2";
832 reg = <0xffb40000 0xffff>;
833 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
836 resets = <&rst USB1_RESET>;
837 reset-names = "dwc2";
839 phy-names = "usb2-phy";
843 watchdog0: watchdog@ffd00200 {
844 compatible = "snps,dw-wdt";
845 reg = <0xffd00200 0x100>;
846 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&l4_sys_free_clk>;
851 watchdog1: watchdog@ffd00300 {
852 compatible = "snps,dw-wdt";
853 reg = <0xffd00300 0x100>;
854 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&l4_sys_free_clk>;