arch/arm/dts/socfpga_arria10-handoff.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2
   3 / {
   4         clocks {
   5                 #address-cells = <1>;
   6                 #size-cells = <1>;
   7                 u-boot,dm-pre-reloc;
   8
   9                 altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
  10                         compatible = "fixed-clock";
  11                         #clock-cells = <0>;
  12                         clock-frequency = <EOSC1_CLK_HZ>;
  13                         clock-output-names = "altera_arria10_hps_eosc1-clk";
  14                         u-boot,dm-pre-reloc;
  15                 };
  16
  17                 altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
  18                         compatible = "fixed-clock";
  19                         #clock-cells = <0>;
  20                         clock-frequency = <CB_INTOSC_LS_CLK_HZ>;
  21                         clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
  22                         u-boot,dm-pre-reloc;
  23                 };
  24
  25                 /* Clock source: altera_arria10_hps_f2h_free */
  26                 altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
  27                         compatible = "fixed-clock";
  28                         #clock-cells = <0>;
  29                         clock-frequency = <F2H_FREE_CLK_HZ>;
  30                         clock-output-names = "altera_arria10_hps_f2h_free-clk";
  31                         u-boot,dm-pre-reloc;
  32                 };
  33         };
  34
  35         clkmgr@0xffd04000 {
  36                 compatible = "altr,socfpga-a10-clk-init";
  37                 reg = <0xffd04000 0x00000200>;
  38                 reg-names = "soc_clock_manager_OCP_SLV";
  39                 u-boot,dm-pre-reloc;
  40
  41                 mainpll {
  42                         vco0-psrc = <MAINPLLGRP_VCO0_PSRC>;
  43                         vco1-denom = <MAINPLLGRP_VCO1_DENOM>;
  44                         vco1-numer = <MAINPLLGRP_VCO1_NUMER>;
  45                         mpuclk-cnt = <MAINPLLGRP_MPUCLK_CNT>;
  46                         mpuclk-src = <MAINPLLGRP_MPUCLK_SRC>;
  47                         nocclk-cnt = <MAINPLLGRP_NOCCLK_CNT>;
  48                         nocclk-src = <MAINPLLGRP_NOCCLK_SRC>;
  49                         cntr2clk-cnt = <MAINPLLGRP_CNTR2CLK_CNT>;
  50                         cntr3clk-cnt = <MAINPLLGRP_CNTR3CLK_CNT>;
  51                         cntr4clk-cnt = <MAINPLLGRP_CNTR4CLK_CNT>;
  52                         cntr5clk-cnt = <MAINPLLGRP_CNTR5CLK_CNT>;
  53                         cntr6clk-cnt = <MAINPLLGRP_CNTR6CLK_CNT>;
  54                         cntr7clk-cnt = <MAINPLLGRP_CNTR7CLK_CNT>;
  55                         cntr7clk-src = <MAINPLLGRP_CNTR7CLK_SRC>;
  56                         cntr8clk-cnt = <MAINPLLGRP_CNTR8CLK_CNT>;
  57                         cntr9clk-cnt = <MAINPLLGRP_CNTR9CLK_CNT>;
  58                         cntr9clk-src = <MAINPLLGRP_CNTR9CLK_SRC>;
  59                         cntr15clk-cnt = <MAINPLLGRP_CNTR15CLK_CNT>;
  60                         nocdiv-l4mainclk = <MAINPLLGRP_NOCDIV_L4MAINCLK>;
  61                         nocdiv-l4mpclk = <MAINPLLGRP_NOCDIV_L4MPCLK>;
  62                         nocdiv-l4spclk = <MAINPLLGRP_NOCDIV_L4SPCLK>;
  63                         nocdiv-csatclk = <MAINPLLGRP_NOCDIV_CSATCLK>;
  64                         nocdiv-cstraceclk = <MAINPLLGRP_NOCDIV_CSTRACECLK>;
  65                         nocdiv-cspdbgclk = <MAINPLLGRP_NOCDIV_CSPDBGCLK>;
  66                         u-boot,dm-pre-reloc;
  67                 };
  68
  69                 perpll {
  70                         vco0-psrc = <PERPLLGRP_VCO0_PSRC>;
  71                         vco1-denom = <PERPLLGRP_VCO1_DENOM>;
  72                         vco1-numer = <PERPLLGRP_VCO1_NUMER>;
  73                         cntr2clk-cnt = <PERPLLGRP_CNTR2CLK_CNT>;
  74                         cntr2clk-src = <PERPLLGRP_CNTR2CLK_SRC>;
  75                         cntr3clk-cnt = <PERPLLGRP_CNTR3CLK_CNT>;
  76                         cntr3clk-src = <PERPLLGRP_CNTR3CLK_SRC>;
  77                         cntr4clk-cnt = <PERPLLGRP_CNTR4CLK_CNT>;
  78                         cntr4clk-src = <PERPLLGRP_CNTR4CLK_SRC>;
  79                         cntr5clk-cnt = <PERPLLGRP_CNTR5CLK_CNT>;
  80                         cntr5clk-src = <PERPLLGRP_CNTR5CLK_SRC>;
  81                         cntr6clk-cnt = <PERPLLGRP_CNTR6CLK_CNT>;
  82                         cntr6clk-src = <PERPLLGRP_CNTR6CLK_SRC>;
  83                         cntr7clk-cnt = <PERPLLGRP_CNTR7CLK_CNT>;
  84                         cntr8clk-cnt = <PERPLLGRP_CNTR8CLK_CNT>;
  85                         cntr8clk-src = <PERPLLGRP_CNTR8CLK_SRC>;
  86                         cntr9clk-cnt = <PERPLLGRP_CNTR9CLK_CNT>;
  87                         emacctl-emac0sel = <PERPLLGRP_EMACCTL_EMAC0SEL>;
  88                         emacctl-emac1sel = <PERPLLGRP_EMACCTL_EMAC1SEL>;
  89                         emacctl-emac2sel = <PERPLLGRP_EMACCTL_EMAC2SEL>;
  90                         gpiodiv-gpiodbclk = <PERPLLGRP_GPIODIV_GPIODBCLK>;
  91                         u-boot,dm-pre-reloc;
  92                 };
  93
  94                 alteragrp {
  95                         nocclk = <ALTERAGRP_NOCCLK>;
  96                         mpuclk = <ALTERAGRP_MPUCLK>;
  97                         u-boot,dm-pre-reloc;
  98                 };
  99         };
 100
 101         i_io48_pin_mux: pinmux@0xffd07000 {
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104                 compatible = "pinctrl-single";
 105                 reg = <0xffd07000 0x00000800>;
 106                 reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
 107                 u-boot,dm-pre-reloc;
 108
 109                 shared {
 110                         reg = <0xffd07000 0x00000200>;
 111                         pinctrl-single,register-width = <32>;
 112                         pinctrl-single,function-mask = <0x0000000f>;
 113                         pinctrl-single,pins =
 114                                 <0x00000000 PINMUX_SHARED_IO_Q1_1_SEL>,
 115                                 <0x00000004 PINMUX_SHARED_IO_Q1_2_SEL>,
 116                                 <0x00000008 PINMUX_SHARED_IO_Q1_3_SEL>,
 117                                 <0x0000000c PINMUX_SHARED_IO_Q1_4_SEL>,
 118                                 <0x00000010 PINMUX_SHARED_IO_Q1_5_SEL>,
 119                                 <0x00000014 PINMUX_SHARED_IO_Q1_6_SEL>,
 120                                 <0x00000018 PINMUX_SHARED_IO_Q1_7_SEL>,
 121                                 <0x0000001c PINMUX_SHARED_IO_Q1_8_SEL>,
 122                                 <0x00000020 PINMUX_SHARED_IO_Q1_9_SEL>,
 123                                 <0x00000024 PINMUX_SHARED_IO_Q1_10_SEL>,
 124                                 <0x00000028 PINMUX_SHARED_IO_Q1_11_SEL>,
 125                                 <0x0000002c PINMUX_SHARED_IO_Q1_12_SEL>,
 126                                 <0x00000030 PINMUX_SHARED_IO_Q2_1_SEL>,
 127                                 <0x00000034 PINMUX_SHARED_IO_Q2_2_SEL>,
 128                                 <0x00000038 PINMUX_SHARED_IO_Q2_3_SEL>,
 129                                 <0x0000003c PINMUX_SHARED_IO_Q2_4_SEL>,
 130                                 <0x00000040 PINMUX_SHARED_IO_Q2_5_SEL>,
 131                                 <0x00000044 PINMUX_SHARED_IO_Q2_6_SEL>,
 132                                 <0x00000048 PINMUX_SHARED_IO_Q2_7_SEL>,
 133                                 <0x0000004c PINMUX_SHARED_IO_Q2_8_SEL>,
 134                                 <0x00000050 PINMUX_SHARED_IO_Q2_9_SEL>,
 135                                 <0x00000054 PINMUX_SHARED_IO_Q2_10_SEL>,
 136                                 <0x00000058 PINMUX_SHARED_IO_Q2_11_SEL>,
 137                                 <0x0000005c PINMUX_SHARED_IO_Q2_12_SEL>,
 138                                 <0x00000060 PINMUX_SHARED_IO_Q3_1_SEL>,
 139                                 <0x00000064 PINMUX_SHARED_IO_Q3_2_SEL>,
 140                                 <0x00000068 PINMUX_SHARED_IO_Q3_3_SEL>,
 141                                 <0x0000006c PINMUX_SHARED_IO_Q3_4_SEL>,
 142                                 <0x00000070 PINMUX_SHARED_IO_Q3_5_SEL>,
 143                                 <0x00000074 PINMUX_SHARED_IO_Q3_6_SEL>,
 144                                 <0x00000078 PINMUX_SHARED_IO_Q3_7_SEL>,
 145                                 <0x0000007c PINMUX_SHARED_IO_Q3_8_SEL>,
 146                                 <0x00000080 PINMUX_SHARED_IO_Q3_9_SEL>,
 147                                 <0x00000084 PINMUX_SHARED_IO_Q3_10_SEL>,
 148                                 <0x00000088 PINMUX_SHARED_IO_Q3_11_SEL>,
 149                                 <0x0000008c PINMUX_SHARED_IO_Q3_12_SEL>,
 150                                 <0x00000090 PINMUX_SHARED_IO_Q4_1_SEL>,
 151                                 <0x00000094 PINMUX_SHARED_IO_Q4_2_SEL>,
 152                                 <0x00000098 PINMUX_SHARED_IO_Q4_3_SEL>,
 153                                 <0x0000009c PINMUX_SHARED_IO_Q4_4_SEL>,
 154                                 <0x000000a0 PINMUX_SHARED_IO_Q4_5_SEL>,
 155                                 <0x000000a4 PINMUX_SHARED_IO_Q4_6_SEL>,
 156                                 <0x000000a8 PINMUX_SHARED_IO_Q4_7_SEL>,
 157                                 <0x000000ac PINMUX_SHARED_IO_Q4_8_SEL>,
 158                                 <0x000000b0 PINMUX_SHARED_IO_Q4_9_SEL>,
 159                                 <0x000000b4 PINMUX_SHARED_IO_Q4_10_SEL>,
 160                                 <0x000000b8 PINMUX_SHARED_IO_Q4_11_SEL>,
 161                                 <0x000000bc PINMUX_SHARED_IO_Q4_12_SEL>;
 162                         u-boot,dm-pre-reloc;
 163                 };
 164
 165                 dedicated {
 166                         reg = <0xffd07200 0x00000200>;
 167                         pinctrl-single,register-width = <32>;
 168                         pinctrl-single,function-mask = <0x0000000f>;
 169                         pinctrl-single,pins =
 170                                 <0x0000000c PINMUX_DEDICATED_IO_4_SEL>,
 171                                 <0x00000010 PINMUX_DEDICATED_IO_5_SEL>,
 172                                 <0x00000014 PINMUX_DEDICATED_IO_6_SEL>,
 173                                 <0x00000018 PINMUX_DEDICATED_IO_7_SEL>,
 174                                 <0x0000001c PINMUX_DEDICATED_IO_8_SEL>,
 175                                 <0x00000020 PINMUX_DEDICATED_IO_9_SEL>,
 176                                 <0x00000024 PINMUX_DEDICATED_IO_10_SEL>,
 177                                 <0x00000028 PINMUX_DEDICATED_IO_11_SEL>,
 178                                 <0x0000002c PINMUX_DEDICATED_IO_12_SEL>,
 179                                 <0x00000030 PINMUX_DEDICATED_IO_13_SEL>,
 180                                 <0x00000034 PINMUX_DEDICATED_IO_14_SEL>,
 181                                 <0x00000038 PINMUX_DEDICATED_IO_15_SEL>,
 182                                 <0x0000003c PINMUX_DEDICATED_IO_16_SEL>,
 183                                 <0x00000040 PINMUX_DEDICATED_IO_17_SEL>;
 184                         u-boot,dm-pre-reloc;
 185                 };
 186
 187                 dedicated_cfg {
 188                         reg = <0xffd07200 0x00000200>;
 189                         pinctrl-single,register-width = <32>;
 190                         pinctrl-single,function-mask = <0x003f3f3f>;
 191                         pinctrl-single,pins =
 192                                 <0x00000100 CONFIG_IO_BANK_VSEL>,
 193                                 <0x00000104 CONFIG_IO_MACRO (CONFIG_IO_1)>,
 194                                 <0x00000108 CONFIG_IO_MACRO (CONFIG_IO_2)>,
 195                                 <0x0000010c CONFIG_IO_MACRO (CONFIG_IO_3)>,
 196                                 <0x00000110 CONFIG_IO_MACRO (CONFIG_IO_4)>,
 197                                 <0x00000114 CONFIG_IO_MACRO (CONFIG_IO_5)>,
 198                                 <0x00000118 CONFIG_IO_MACRO (CONFIG_IO_6)>,
 199                                 <0x0000011c CONFIG_IO_MACRO (CONFIG_IO_7)>,
 200                                 <0x00000120 CONFIG_IO_MACRO (CONFIG_IO_8)>,
 201                                 <0x00000124 CONFIG_IO_MACRO (CONFIG_IO_9)>,
 202                                 <0x00000128 CONFIG_IO_MACRO (CONFIG_IO_10)>,
 203                                 <0x0000012c CONFIG_IO_MACRO (CONFIG_IO_11)>,
 204                                 <0x00000130 CONFIG_IO_MACRO (CONFIG_IO_12)>,
 205                                 <0x00000134 CONFIG_IO_MACRO (CONFIG_IO_13)>,
 206                                 <0x00000138 CONFIG_IO_MACRO (CONFIG_IO_14)>,
 207                                 <0x0000013c CONFIG_IO_MACRO (CONFIG_IO_15)>,
 208                                 <0x00000140 CONFIG_IO_MACRO (CONFIG_IO_16)>,
 209                                 <0x00000144 CONFIG_IO_MACRO (CONFIG_IO_17)>;
 210                         u-boot,dm-pre-reloc;
 211                 };
 212
 213                 fpga {
 214                         reg = <0xffd07400 0x00000100>;
 215                         pinctrl-single,register-width = <32>;
 216                         pinctrl-single,function-mask = <0x00000001>;
 217                         pinctrl-single,pins =
 218                                 <0x00000000 PINMUX_RGMII0_USEFPGA_SEL>,
 219                                 <0x00000004 PINMUX_RGMII1_USEFPGA_SEL>,
 220                                 <0x00000008 PINMUX_RGMII2_USEFPGA_SEL>,
 221                                 <0x0000000c PINMUX_I2C0_USEFPGA_SEL>,
 222                                 <0x00000010 PINMUX_I2C1_USEFPGA_SEL>,
 223                                 <0x00000014 PINMUX_I2CEMAC0_USEFPGA_SEL>,
 224                                 <0x00000018 PINMUX_I2CEMAC1_USEFPGA_SEL>,
 225                                 <0x0000001c PINMUX_I2CEMAC2_USEFPGA_SEL>,
 226                                 <0x00000020 PINMUX_NAND_USEFPGA_SEL>,
 227                                 <0x00000024 PINMUX_QSPI_USEFPGA_SEL>,
 228                                 <0x00000028 PINMUX_SDMMC_USEFPGA_SEL>,
 229                                 <0x0000002c PINMUX_SPIM0_USEFPGA_SEL>,
 230                                 <0x00000030 PINMUX_SPIM1_USEFPGA_SEL>,
 231                                 <0x00000034 PINMUX_SPIS0_USEFPGA_SEL>,
 232                                 <0x00000038 PINMUX_SPIS1_USEFPGA_SEL>,
 233                                 <0x0000003c PINMUX_UART0_USEFPGA_SEL>,
 234                                 <0x00000040 PINMUX_UART1_USEFPGA_SEL>;
 235                         u-boot,dm-pre-reloc;
 236                 };
 237         };
 238
 239         i_noc: noc@0xffd10000 {
 240                 compatible = "altr,socfpga-a10-noc";
 241                 reg = <0xffd10000 0x00008000>;
 242                 reg-names = "mpu_m0";
 243                 u-boot,dm-pre-reloc;
 244
 245                 firewall {
 246                         mpu0 = <0x00000000 0x0000ffff>;
 247                         l3-0 = <0x00000000 0x0000ffff>;
 248                         fpga2sdram0-0 = <0x00000000 0x0000ffff>;
 249                         fpga2sdram1-0 = <0x00000000 0x0000ffff>;
 250                         fpga2sdram2-0 = <0x00000000 0x0000ffff>;
 251                         u-boot,dm-pre-reloc;
 252                 };
 253         };
 254
 255         hps_fpgabridge0: fpgabridge@0 {
 256                 compatible = "altr,socfpga-hps2fpga-bridge";
 257                 init-val = <H2F_AXI_MASTER>;
 258                 u-boot,dm-pre-reloc;
 259         };
 260
 261         hps_fpgabridge1: fpgabridge@1 {
 262                 compatible = "altr,socfpga-lwhps2fpga-bridge";
 263                 init-val = <LWH2F_AXI_MASTER>;
 264                 u-boot,dm-pre-reloc;
 265         };
 266
 267         hps_fpgabridge2: fpgabridge@2 {
 268                 compatible = "altr,socfpga-fpga2hps-bridge";
 269                 init-val = <F2H_AXI_SLAVE>;
 270                 u-boot,dm-pre-reloc;
 271         };
 272
 273         hps_fpgabridge3: fpgabridge@3 {
 274                 compatible = "altr,socfpga-fpga2sdram0-bridge";
 275                 init-val = <F2SDRAM0_AXI_SLAVE>;
 276                 u-boot,dm-pre-reloc;
 277         };
 278
 279         hps_fpgabridge4: fpgabridge@4 {
 280                 compatible = "altr,socfpga-fpga2sdram1-bridge";
 281                 init-val = <F2SDRAM1_AXI_SLAVE>;
 282                 u-boot,dm-pre-reloc;
 283         };
 284
 285         hps_fpgabridge5: fpgabridge@5 {
 286                 compatible = "altr,socfpga-fpga2sdram2-bridge";
 287                 init-val = <F2SDRAM2_AXI_SLAVE>;
 288                 u-boot,dm-pre-reloc;
 289         };
 290 };