arch/arm/dts/sama7g5ek.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 /*
   3  * sama7g5ek.dts - Device Tree file for SAMA7G5 EK
   4  *                 SAMA7G5 Evaluation Kit
   5  *
   6  *  Copyright (c) 2020, Microchip Technology Inc.
   7  *                2020, Eugen Hristev <eugen.hristev@microchip.com>
   8  *                2020, Claudiu Beznea <claudiu.beznea@microchip.com>
   9  */
  10 /dts-v1/;
  11 #include "sama7g5.dtsi"
  12 #include "sama7g5-pinfunc.h"
  13
  14 / {
  15         model = "Microchip SAMA7G5 Evaluation Kit";
  16         compatible = "microchip,sama7g5ek", "microchip,sama7g54", "microchip,sama7g5", "microchip,sama7";
  17
  18         aliases {
  19                 serial0 = &uart0;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24         };
  25
  26         clocks {
  27                 slow_xtal: slow_xtal {
  28                         clock-frequency = <32768>;
  29                 };
  30
  31                 main_xtal: main_xtal {
  32                         clock-frequency = <24000000>;
  33                 };
  34         };
  35
  36         ahb {
  37
  38                 apb {
  39                         sdmmc0: sdio-host@e1204000 {
  40                                 bus-width = <8>;
  41                                 non-removable;
  42                                 pinctrl-names = "default";
  43                                 pinctrl-0 = <&pinctrl_sdmmc0_cmd_data_default
  44                                              &pinctrl_sdmmc0_ck_rstn_ds_cd_default>;
  45                                 status = "okay";
  46                         };
  47
  48                         sdmmc1: sdio-host@e1208000 {
  49                                 bus-width = <4>;
  50                                 pinctrl-names = "default";
  51                                 pinctrl-0 = <&pinctrl_sdmmc1_cmd_data_default
  52                                              &pinctrl_sdmmc1_ck_cd_rstn_vddsel_default>;
  53                                 status = "okay";
  54                         };
  55
  56                         uart0: serial@e1824200 {
  57                                 pinctrl-names = "default";
  58                                 pinctrl-0 = <&pinctrl_flx3_default>;
  59                                 status = "okay";
  60                         };
  61                 };
  62         };
  63 };
  64
  65 &gmac0 {
  66         #address-cells = <1>;
  67         #size-cells = <0>;
  68         pinctrl-names = "default";
  69         pinctrl-0 = <&pinctrl_gmac0_default>;
  70         phy-mode = "rgmii-id";
  71         status = "okay";
  72
  73         ethernet-phy@7 {
  74                 reg = <0x7>;
  75         };
  76 };
  77
  78 &gmac1 {
  79         #address-cells = <1>;
  80         #size-cells = <0>;
  81         pinctrl-names = "default";
  82         pinctrl-0 = <&pinctrl_gmac1_default>;
  83         phy-mode = "rmii";
  84         status = "okay";
  85
  86         ethernet-phy@0 {
  87                 reg = <0x0>;
  88         };
  89 };
  90
  91 &pinctrl {
  92         pinctrl_flx3_default: flx3_default {
  93                 pinmux = <PIN_PD16__FLEXCOM3_IO0>,
  94                          <PIN_PD17__FLEXCOM3_IO1>;
  95                 bias-disable;
  96         };
  97
  98         pinctrl_sdmmc0_cmd_data_default: sdmmc0_cmd_data_default {
  99                 pinmux = <PIN_PA1__SDMMC0_CMD>,
 100                          <PIN_PA3__SDMMC0_DAT0>,
 101                          <PIN_PA4__SDMMC0_DAT1>,
 102                          <PIN_PA5__SDMMC0_DAT2>,
 103                          <PIN_PA6__SDMMC0_DAT3>,
 104                          <PIN_PA7__SDMMC0_DAT4>,
 105                          <PIN_PA8__SDMMC0_DAT5>,
 106                          <PIN_PA9__SDMMC0_DAT6>,
 107                          <PIN_PA10__SDMMC0_DAT7>;
 108                 bias-pull-up;
 109         };
 110
 111         pinctrl_sdmmc0_ck_rstn_ds_cd_default: sdmmc0_ck_rstn_ds_cd_default {
 112                 pinmux = <PIN_PA0__SDMMC0_CK>,
 113                          <PIN_PA2__SDMMC0_RSTN>,
 114                          <PIN_PA11__SDMMC0_DS>,
 115                          <PIN_PA14__SDMMC0_CD>;
 116                 bias-pull-up;
 117         };
 118
 119         pinctrl_sdmmc1_cmd_data_default: sdmmc1_cmd_data_default {
 120                 pinmux = <PIN_PB29__SDMMC1_CMD>,
 121                          <PIN_PB31__SDMMC1_DAT0>,
 122                          <PIN_PC0__SDMMC1_DAT1>,
 123                          <PIN_PC1__SDMMC1_DAT2>,
 124                          <PIN_PC2__SDMMC1_DAT3>;
 125                 bias-pull-up;
 126         };
 127
 128         pinctrl_sdmmc1_ck_cd_rstn_vddsel_default: sdmmc1_ck_cd_rstn_vddsel_default {
 129                 pinmux = <PIN_PB30__SDMMC1_CK>,
 130                          <PIN_PB28__SDMMC1_RSTN>,
 131                          <PIN_PC5__SDMMC1_1V8SEL>,
 132                          <PIN_PC4__SDMMC1_CD>;
 133                 bias-pull-up;
 134         };
 135
 136         pinctrl_gmac0_default: gmac0_default {
 137                 pinmux = <PIN_PA16__G0_TX0>,
 138                          <PIN_PA17__G0_TX1>,
 139                          <PIN_PA26__G0_TX2>,
 140                          <PIN_PA27__G0_TX3>,
 141                          <PIN_PA19__G0_RX0>,
 142                          <PIN_PA20__G0_RX1>,
 143                          <PIN_PA28__G0_RX2>,
 144                          <PIN_PA29__G0_RX3>,
 145                          <PIN_PA15__G0_TXEN>,
 146                          <PIN_PA24__G0_TXCK>,
 147                          <PIN_PA30__G0_RXCK>,
 148                          <PIN_PA18__G0_RXDV>,
 149                          <PIN_PA22__G0_MDC>,
 150                          <PIN_PA23__G0_MDIO>,
 151                          <PIN_PA25__G0_125CK>;
 152                 bias-disable;
 153         };
 154
 155         pinctrl_gmac1_default: gmac1_default {
 156                 pinmux = <PIN_PD30__G1_TXCK>,
 157                          <PIN_PD22__G1_TX0>,
 158                          <PIN_PD23__G1_TX1>,
 159                          <PIN_PD21__G1_TXEN>,
 160                          <PIN_PD25__G1_RX0>,
 161                          <PIN_PD26__G1_RX1>,
 162                          <PIN_PD27__G1_RXER>,
 163                          <PIN_PD24__G1_RXDV>,
 164                          <PIN_PD28__G1_MDC>,
 165                          <PIN_PD29__G1_MDIO>;
 166                 bias-disable;
 167         };
 168 };