arch/arm/dts/sama7g5ek.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 /*
   3  * sama7g5ek.dts - Device Tree file for SAMA7G5 EK
   4  *                 SAMA7G5 Evaluation Kit
   5  *
   6  *  Copyright (c) 2020, Microchip Technology Inc.
   7  *                2020, Eugen Hristev <eugen.hristev@microchip.com>
   8  *                2020, Claudiu Beznea <claudiu.beznea@microchip.com>
   9  */
  10 /dts-v1/;
  11 #include "sama7g5.dtsi"
  12 #include "sama7g5-pinfunc.h"
  13
  14 / {
  15         model = "Microchip SAMA7G5 Evaluation Kit";
  16         compatible = "microchip,sama7g5ek", "microchip,sama7g54", "microchip,sama7g5", "microchip,sama7";
  17
  18         aliases {
  19                 serial0 = &uart0;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24         };
  25
  26         clocks {
  27                 slow_xtal: slow_xtal {
  28                         clock-frequency = <32768>;
  29                 };
  30
  31                 main_xtal: main_xtal {
  32                         clock-frequency = <24000000>;
  33                 };
  34         };
  35
  36         ahb {
  37
  38                 apb {
  39                         sdmmc1: sdio-host@e1208000 {
  40                                 bus-width = <4>;
  41                                 pinctrl-names = "default";
  42                                 pinctrl-0 = <&pinctrl_sdmmc1_cmd_data_default
  43                                              &pinctrl_sdmmc1_ck_cd_rstn_vddsel_default>;
  44                                 status = "okay";
  45                         };
  46
  47                         uart0: serial@e1824200 {
  48                                 pinctrl-names = "default";
  49                                 pinctrl-0 = <&pinctrl_flx3_default>;
  50                                 status = "okay";
  51                         };
  52                 };
  53         };
  54 };
  55
  56 &gmac0 {
  57         #address-cells = <1>;
  58         #size-cells = <0>;
  59         pinctrl-names = "default";
  60         pinctrl-0 = <&pinctrl_gmac0_default>;
  61         phy-mode = "rgmii-id";
  62         status = "okay";
  63
  64         ethernet-phy@7 {
  65                 reg = <0x7>;
  66         };
  67 };
  68
  69 &gmac1 {
  70         #address-cells = <1>;
  71         #size-cells = <0>;
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_gmac1_default>;
  74         phy-mode = "rmii";
  75         status = "okay";
  76
  77         ethernet-phy@0 {
  78                 reg = <0x0>;
  79         };
  80 };
  81
  82 &pinctrl {
  83         pinctrl_flx3_default: flx3_default {
  84                 pinmux = <PIN_PD16__FLEXCOM3_IO0>,
  85                          <PIN_PD17__FLEXCOM3_IO1>;
  86                 bias-disable;
  87         };
  88
  89         pinctrl_sdmmc1_cmd_data_default: sdmmc1_cmd_data_default {
  90                 pinmux = <PIN_PB29__SDMMC1_CMD>,
  91                          <PIN_PB31__SDMMC1_DAT0>,
  92                          <PIN_PC0__SDMMC1_DAT1>,
  93                          <PIN_PC1__SDMMC1_DAT2>,
  94                          <PIN_PC2__SDMMC1_DAT3>;
  95                 bias-pull-up;
  96         };
  97
  98         pinctrl_sdmmc1_ck_cd_rstn_vddsel_default: sdmmc1_ck_cd_rstn_vddsel_default {
  99                 pinmux = <PIN_PB30__SDMMC1_CK>,
 100                          <PIN_PB28__SDMMC1_RSTN>,
 101                          <PIN_PC5__SDMMC1_1V8SEL>,
 102                          <PIN_PC4__SDMMC1_CD>;
 103                 bias-pull-up;
 104         };
 105
 106         pinctrl_gmac0_default: gmac0_default {
 107                 pinmux = <PIN_PA16__G0_TX0>,
 108                          <PIN_PA17__G0_TX1>,
 109                          <PIN_PA26__G0_TX2>,
 110                          <PIN_PA27__G0_TX3>,
 111                          <PIN_PA19__G0_RX0>,
 112                          <PIN_PA20__G0_RX1>,
 113                          <PIN_PA28__G0_RX2>,
 114                          <PIN_PA29__G0_RX3>,
 115                          <PIN_PA15__G0_TXEN>,
 116                          <PIN_PA24__G0_TXCK>,
 117                          <PIN_PA30__G0_RXCK>,
 118                          <PIN_PA18__G0_RXDV>,
 119                          <PIN_PA22__G0_MDC>,
 120                          <PIN_PA23__G0_MDIO>,
 121                          <PIN_PA25__G0_125CK>;
 122                 bias-disable;
 123         };
 124
 125         pinctrl_gmac1_default: gmac1_default {
 126                 pinmux = <PIN_PD30__G1_TXCK>,
 127                          <PIN_PD22__G1_TX0>,
 128                          <PIN_PD23__G1_TX1>,
 129                          <PIN_PD21__G1_TXEN>,
 130                          <PIN_PD25__G1_RX0>,
 131                          <PIN_PD26__G1_RX1>,
 132                          <PIN_PD27__G1_RXER>,
 133                          <PIN_PD24__G1_RXDV>,
 134                          <PIN_PD28__G1_MDC>,
 135                          <PIN_PD29__G1_MDIO>;
 136                 bias-disable;
 137         };
 138 };