1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 SoC.
5 * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
7 * Author: Eugen Hristev <eugen.hristev@microchip.com>
8 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
12 #include "skeleton.dtsi"
13 #include <dt-bindings/clk/at91.h>
16 model = "Microchip SAMA7G5 family SoC";
17 compatible = "microchip,sama7g5";
20 slow_rc_osc: slow_rc_osc {
21 compatible = "fixed-clock";
23 clock-frequency = <32000>;
27 compatible = "fixed-clock";
29 clock-frequency = <12000000>;
32 slow_xtal: slow_xtal {
33 compatible = "fixed-clock";
37 main_xtal: main_xtal {
38 compatible = "fixed-clock";
49 compatible = "arm,cortex-a7";
50 clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>;
51 clock-names = "cpu", "master", "xtal";
56 compatible = "simple-bus";
61 compatible = "simple-bus";
65 pioA: pinctrl@e0014000 {
66 compatible = "microchip,sama7g5-gpio";
67 reg = <0xe0014000 0x800>;
70 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
73 pinctrl: pinctrl_default {
74 compatible = "microchip,sama7g5-pinctrl";
79 compatible = "microchip,sama7g5-pmc";
80 reg = <0xe0018000 0x200>;
82 clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
83 clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
87 clk32: sckc@e001d050 {
88 compatible = "microchip,sam9x60-sckc";
89 reg = <0xe001d050 0x4>;
90 clocks = <&slow_rc_osc>, <&slow_xtal>;
94 sdmmc0: sdio-host@e1204000 {
95 compatible = "microchip,sama7g5-sdhci";
96 reg = <0xe1204000 0x300>;
97 clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
98 clock-names = "hclock", "multclk";
99 assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
100 assigned-clock-rates = <200000000>;
101 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
105 sdmmc1: sdio-host@e1208000 {
106 compatible = "microchip,sama7g5-sdhci";
107 reg = <0xe1208000 0x300>;
108 clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
109 clock-names = "hclock", "multclk";
110 assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
111 assigned-clock-rates = <200000000>;
112 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
116 pit64b0: timer@e1800000 {
117 compatible = "microchip,sama7g5-pit64b";
118 reg = <0xe1800000 0x4000>;
119 clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
120 clock-names = "pclk", "gclk";
124 flx1: flexcom@e181c000 {
125 compatible = "atmel,sama5d2-flexcom";
126 reg = <0xe181c000 0x200>;
127 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
128 #address-cells = <1>;
130 ranges = <0x0 0xe181c000 0x800>;
134 compatible = "atmel,sama5d2-i2c";
136 #address-cells = <1>;
138 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
142 uart0: serial@e1824200 {
143 compatible = "atmel,at91sam9260-usart";
144 reg = <0xe1824200 0x200>;
145 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
146 clock-names = "usart";
150 gmac0: ethernet@e2800000 {
151 compatible = "cdns,sama7g5-gem";
152 reg = <0xe2800000 0x4000>;
153 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>;
154 clock-names = "hclk", "pclk", "tx_clk";
155 assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
156 assigned-clock-parents = <&pmc PMC_TYPE_CORE 21>; /* eth pll div. */
157 assigned-clock-rates = <125000000>;
161 gmac1: ethernet@e2804000 {
162 compatible = "cdns,sama7g5-emac";
163 reg = <0xe2804000 0x1000>;
164 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
165 clock-names = "pclk", "hclk";