arch/arm/dts/sama7g5.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * sama7g5.dtsi - Device Tree Include file for SAMA7G5 SoC.
   4  *
   5  * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
   6  *
   7  * Author: Eugen Hristev <eugen.hristev@microchip.com>
   8  * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
   9  *
  10  */
  11
  12 #include "skeleton.dtsi"
  13 #include <dt-bindings/clk/at91.h>
  14
  15 / {
  16         model = "Microchip SAMA7G5 family SoC";
  17         compatible = "microchip,sama7g5";
  18
  19         clocks {
  20                 slow_rc_osc: slow_rc_osc {
  21                         compatible = "fixed-clock";
  22                         #clock-cells = <0>;
  23                         clock-frequency = <32000>;
  24                 };
  25
  26                 main_rc: main_rc {
  27                         compatible = "fixed-clock";
  28                         #clock-cells = <0>;
  29                         clock-frequency = <12000000>;
  30                 };
  31
  32                 slow_xtal: slow_xtal {
  33                         compatible = "fixed-clock";
  34                         #clock-cells = <0>;
  35                 };
  36
  37                 main_xtal: main_xtal {
  38                         compatible = "fixed-clock";
  39                         #clock-cells = <0>;
  40                 };
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 A7_0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a7";
  50                         clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>;
  51                         clock-names = "cpu", "master", "xtal";
  52                 };
  53         };
  54
  55         ahb {
  56                 compatible = "simple-bus";
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59
  60                 apb {
  61                         compatible = "simple-bus";
  62                         #address-cells = <1>;
  63                         #size-cells = <1>;
  64
  65                         pioA: pinctrl@e0014000 {
  66                                 compatible = "microchip,sama7g5-gpio";
  67                                 reg = <0xe0014000 0x800>;
  68                                 gpio-controller;
  69                                 #gpio-cells = <2>;
  70                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
  71                                 status = "okay";
  72
  73                                 pinctrl: pinctrl_default {
  74                                         compatible = "microchip,sama7g5-pinctrl";
  75                                 };
  76                         };
  77
  78                         pmc: pmc@e0018000 {
  79                                 compatible = "microchip,sama7g5-pmc";
  80                                 reg = <0xe0018000 0x200>;
  81                                 #clock-cells = <2>;
  82                                 clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
  83                                 clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
  84                                 status = "okay";
  85                         };
  86
  87                         clk32: sckc@e001d050 {
  88                                 compatible = "microchip,sam9x60-sckc";
  89                                 reg = <0xe001d050 0x4>;
  90                                 clocks = <&slow_rc_osc>, <&slow_xtal>;
  91                                 #clock-cells = <1>;
  92                         };
  93
  94                         qspi0: spi@e080c000 {
  95                                 compatible = "microchip,sama7g5-ospi";
  96                                 reg = <0xe080c000 0x400>, <0x20000000 0x10000000>;
  97                                 reg-names = "qspi_base", "qspi_mmap";
  98                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>;
  99                                 clock-names = "pclk", "gclk";
 100                                 assigned-clocks = <&pmc PMC_TYPE_GCK 78>;
 101                                 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
 102                                 #address-cells = <1>;
 103                                 #size-cells = <0>;
 104                                 status = "disabled";
 105                         };
 106
 107                         qspi1: spi@e0810000 {
 108                                 compatible = "microchip,sama7g5-qspi";
 109                                 reg = <0xe0810000 0x400>, <0x30000000 0x10000000>;
 110                                 reg-names = "qspi_base", "qspi_mmap";
 111                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>;
 112                                 clock-names = "pclk", "gclk";
 113                                 assigned-clocks = <&pmc PMC_TYPE_GCK 78>;
 114                                 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
 115                                 #address-cells = <1>;
 116                                 #size-cells = <0>;
 117                                 status = "disabled";
 118                         };
 119
 120                         sdmmc0: sdio-host@e1204000 {
 121                                 compatible = "microchip,sama7g5-sdhci";
 122                                 reg = <0xe1204000 0x300>;
 123                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
 124                                 clock-names = "hclock", "multclk";
 125                                 assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
 126                                 assigned-clock-rates = <200000000>;
 127                                 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
 128                                 status = "disabled";
 129                         };
 130
 131                         sdmmc1: sdio-host@e1208000 {
 132                                 compatible = "microchip,sama7g5-sdhci";
 133                                 reg = <0xe1208000 0x300>;
 134                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
 135                                 clock-names = "hclock", "multclk";
 136                                 assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
 137                                 assigned-clock-rates = <200000000>;
 138                                 assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
 139                                 status = "disabled";
 140                         };
 141
 142                         pit64b0: timer@e1800000 {
 143                                 compatible = "microchip,sama7g5-pit64b";
 144                                 reg = <0xe1800000 0x4000>;
 145                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
 146                                 clock-names = "pclk", "gclk";
 147                                 status = "okay";
 148                         };
 149
 150                         flx1: flexcom@e181c000 {
 151                                 compatible = "atmel,sama5d2-flexcom";
 152                                 reg = <0xe181c000 0x200>;
 153                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
 154                                 #address-cells = <1>;
 155                                 #size-cells = <1>;
 156                                 ranges = <0x0 0xe181c000 0x800>;
 157                                 status = "disabled";
 158
 159                                 i2c1: i2c@600 {
 160                                         compatible = "atmel,sama5d2-i2c";
 161                                         reg = <0x600 0x200>;
 162                                         #address-cells = <1>;
 163                                         #size-cells = <0>;
 164                                         clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
 165                                 };
 166                         };
 167
 168                         uart0: serial@e1824200 {
 169                                 compatible = "atmel,at91sam9260-usart";
 170                                 reg = <0xe1824200 0x200>;
 171                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
 172                                 clock-names = "usart";
 173                                 status = "disabled";
 174                         };
 175
 176                         gmac0: ethernet@e2800000 {
 177                                 compatible = "cdns,sama7g5-gem";
 178                                 reg = <0xe2800000 0x4000>;
 179                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>;
 180                                 clock-names = "hclk", "pclk", "tx_clk";
 181                                 assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
 182                                 assigned-clock-parents = <&pmc PMC_TYPE_CORE 21>; /* eth pll div. */
 183                                 assigned-clock-rates = <125000000>;
 184                                 status = "disabled";
 185                         };
 186
 187                         gmac1: ethernet@e2804000 {
 188                                 compatible = "cdns,sama7g5-emac";
 189                                 reg = <0xe2804000 0x1000>;
 190                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
 191                                 clock-names = "pclk", "hclk";
 192                                 status = "disabled";
 193                         };
 194                 };
 195         };
 196 };