arch/arm/dts/sama5d27_wlsom1.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1
   4  *
   5  * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
   6  *
   7  * Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
   8  */
   9 #include "sama5d2.dtsi"
  10 #include "sama5d2-pinfunc.h"
  11 / {
  12         model = "Microchip SAMA5D27 WLSOM1";
  13         compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d2", "atmel,sama5";
  14
  15         memory {
  16                 reg = <0x20000000 0x10000000>;
  17         };
  18
  19         ahb {
  20                 apb {
  21                         qspi1: spi@f0024000 {
  22                                 pinctrl-names = "default";
  23                                 pinctrl-0 = <&pinctrl_qspi1_default>;
  24
  25                                 qspi1_flash: spi_flash@0 {
  26                                         compatible = "jedec,spi-nor";
  27                                         reg = <0>;
  28                                         spi-max-frequency = <50000000>;
  29                                         spi-rx-bus-width = <4>;
  30                                         spi-tx-bus-width = <4>;
  31                                 };
  32                         };
  33
  34                         macb0: ethernet@f8008000 {
  35                                 pinctrl-names = "default";
  36                                 pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
  37                                 phy-mode = "rmii";
  38
  39                                 ethernet-phy@0 {
  40                                         reg = <0x0>;
  41                                 };
  42                         };
  43
  44                         pioA: gpio@fc038000 {
  45                                 pinctrl {
  46                                         pinctrl_macb0_phy_irq: macb0_phy_irq {
  47                                                 pinmux = <PIN_PB24__GPIO>;
  48                                                 bias-disable;
  49                                         };
  50
  51                                         pinctrl_macb0_rmii: macb0_rmii {
  52                                                 pinmux = <PIN_PB14__GTXCK>,
  53                                                          <PIN_PB15__GTXEN>,
  54                                                          <PIN_PB16__GRXDV>,
  55                                                          <PIN_PB17__GRXER>,
  56                                                          <PIN_PB18__GRX0>,
  57                                                          <PIN_PB19__GRX1>,
  58                                                          <PIN_PB20__GTX0>,
  59                                                          <PIN_PB21__GTX1>,
  60                                                          <PIN_PB22__GMDC>,
  61                                                          <PIN_PB23__GMDIO>;
  62                                                 bias-disable;
  63                                         };
  64
  65                                         pinctrl_qspi1_default: qspi1_default {
  66                                                 pinmux = <PIN_PB5__QSPI1_SCK>,
  67                                                          <PIN_PB6__QSPI1_CS>,
  68                                                          <PIN_PB7__QSPI1_IO0>,
  69                                                          <PIN_PB8__QSPI1_IO1>,
  70                                                          <PIN_PB9__QSPI1_IO2>,
  71                                                          <PIN_PB10__QSPI1_IO3>;
  72                                                 bias-pull-up;
  73                                         };
  74                                 };
  75                         };
  76                 };
  77         };
  78 };