arch/arm/dts/sam9x60.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
   4  *
   5  * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
   6  *
   7  * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
   8  */
   9
  10 #include "skeleton.dtsi"
  11 #include <dt-bindings/dma/at91.h>
  12 #include <dt-bindings/pinctrl/at91.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/clock/at91.h>
  16
  17 /{
  18         model = "Microchip SAM9X60 SoC";
  19         compatible = "microchip,sam9x60";
  20
  21         aliases {
  22                 serial0 = &dbgu;
  23                 gpio0 = &pioA;
  24                 gpio1 = &pioB;
  25                 gpio3 = &pioD;
  26                 spi0 = &qspi;
  27         };
  28
  29         clocks {
  30                 slow_rc_osc: slow_rc_osc {
  31                         compatible = "fixed-clock";
  32                         #clock-cells = <0>;
  33                         clock-frequency = <18500>;
  34                 };
  35
  36                 slow_xtal: slow_xtal {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                 };
  40
  41                 main_xtal: main_xtal {
  42                         compatible = "fixed-clock";
  43                         #clock-cells = <0>;
  44                 };
  45         };
  46
  47         ahb {
  48                 compatible = "simple-bus";
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 ranges;
  52
  53                 sdhci0: sdhci-host@80000000 {
  54                         compatible = "microchip,sam9x60-sdhci";
  55                         reg = <0x80000000 0x300>;
  56                         clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>;
  57                         clock-names = "hclock", "multclk", "baseclk";
  58                         bus-width = <4>;
  59                         pinctrl-names = "default";
  60                         pinctrl-0 = <&pinctrl_sdhci0>;
  61                 };
  62
  63                 apb {
  64                         compatible = "simple-bus";
  65                         #address-cells = <1>;
  66                         #size-cells = <1>;
  67                         ranges;
  68
  69                         qspi: spi@f0014000 {
  70                                 compatible = "microchip,sam9x60-qspi";
  71                                 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
  72                                 reg-names = "qspi_base", "qspi_mmap";
  73                                 clocks =  <&qspi_clk>, <&qspick>;
  74                                 clock-names = "pclk", "qspick";
  75                                 #address-cells = <1>;
  76                                 #size-cells = <0>;
  77                                 status = "disabled";
  78                         };
  79
  80                         flx0: flexcom@f801c600 {
  81                                 compatible = "atmel,sama5d2-flexcom";
  82                                 reg = <0xf801c000 0x200>;
  83                                 clocks = <&flx0_clk>;
  84                                 #address-cells = <1>;
  85                                 #size-cells = <1>;
  86                                 ranges = <0x0 0xf801c000 0x800>;
  87                                 status = "disabled";
  88                         };
  89
  90                         macb0: ethernet@f802c000 {
  91                                 compatible = "cdns,sam9x60-macb", "cdns,macb";
  92                                 reg = <0xf802c000 0x100>;
  93                                 pinctrl-names = "default";
  94                                 pinctrl-0 = <&pinctrl_macb0_rmii>;
  95                                 clock-names = "hclk", "pclk";
  96                                 clocks = <&macb0_clk>, <&macb0_clk>;
  97                                 status = "disabled";
  98                         };
  99
 100                         dbgu: serial@fffff200 {
 101                                 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
 102                                 reg = <0xfffff200 0x200>;
 103                                 pinctrl-names = "default";
 104                                 pinctrl-0 = <&pinctrl_dbgu>;
 105                                 clocks = <&dbgu_clk>;
 106                                 clock-names = "usart";
 107                         };
 108
 109                         pinctrl {
 110                                 #address-cells = <1>;
 111                                 #size-cells = <1>;
 112                                 compatible = "microchip,sam9x60-pinctrl", "simple-bus";
 113                                 ranges = <0xfffff400 0xfffff400 0x800>;
 114                                 reg = <0xfffff400 0x200         /* pioA */
 115                                        0xfffff600 0x200         /* pioB */
 116                                        0xfffff800 0x200         /* pioC */
 117                                        0xfffffa00 0x200>;       /* pioD */
 118
 119                                 /* shared pinctrl settings */
 120                                 dbgu {
 121                                         pinctrl_dbgu: dbgu-0 {
 122                                                 atmel,pins =
 123                                                         <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
 124                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
 125                                         };
 126                                 };
 127
 128                                 macb0 {
 129                                         pinctrl_macb0_rmii: macb0_rmii-0 {
 130                                                 atmel,pins =
 131                                                         <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
 132                                                          AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
 133                                                          AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A */
 134                                                          AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
 135                                                          AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
 136                                                          AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A */
 137                                                          AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
 138                                                          AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
 139                                                          AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
 140                                                          AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
 141                                         };
 142                                 };
 143
 144                                 sdhci0 {
 145                                         pinctrl_sdhci0: sdhci0 {
 146                                                 atmel,pins =
 147                                                         <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT /* PA17 CK  periph A with pullup */
 148                                                          AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA16 CMD periph A with pullup */
 149                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA15 DAT0 periph A */
 150                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA18 DAT1 periph A with pullup */
 151                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA19 DAT2 periph A with pullup */
 152                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;              /* PA20 DAT3 periph A with pullup */
 153                                         };
 154                                 };
 155                         };
 156
 157                         pioA: gpio@fffff400 {
 158                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 159                                 reg = <0xfffff400 0x200>;
 160                                 #gpio-cells = <2>;
 161                                 gpio-controller;
 162                                 clocks = <&pioA_clk>;
 163                         };
 164
 165                         pioB: gpio@fffff600 {
 166                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 167                                 reg = <0xfffff600 0x200>;
 168                                 #gpio-cells = <2>;
 169                                 gpio-controller;
 170                                 clocks = <&pioB_clk>;
 171                         };
 172
 173                         pioD: gpio@fffffa00 {
 174                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 175                                 reg = <0xfffffa00 0x200>;
 176                                 #gpio-cells = <2>;
 177                                 gpio-controller;
 178                                 clocks = <&pioD_clk>;
 179                         };
 180
 181                         pmc: pmc@fffffc00 {
 182                                 compatible = "atmel,at91sam9x5-pmc";
 183                                 reg = <0xfffffc00 0x200>;
 184                                 #address-cells = <1>;
 185                                 #size-cells = <0>;
 186
 187                                 main: mainck {
 188                                         compatible = "atmel,at91sam9x5-clk-main";
 189                                         #clock-cells = <0>;
 190                                 };
 191
 192                                 plla: pllack {
 193                                         compatible = "microchip,sam9x60-clk-pll";
 194                                         #clock-cells = <0>;
 195                                         clocks = <&main>;
 196                                         reg = <0>;
 197                                         atmel,clk-input-range = <8000000 24000000>;
 198                                         #atmel,pll-clk-output-range-cells = <4>;
 199                                         atmel,pll-clk-output-ranges = <140000000 1200000000 0 0>;
 200                                 };
 201
 202                                 mck: masterck {
 203                                         compatible = "atmel,at91sam9x5-clk-master";
 204                                         #clock-cells = <0>;
 205                                         clocks = <&clk32 0>, <&main>, <&plla>;
 206                                         atmel,clk-output-range = <140000000 200000000>;
 207                                         atmel,clk-divisors = <1 2 4 6>;
 208                                 };
 209
 210                                 system: systemck {
 211                                         compatible = "atmel,at91rm9200-clk-system";
 212                                         #address-cells = <1>;
 213                                         #size-cells = <0>;
 214
 215                                         qspick: qspick {
 216                                                 #clock-cells = <0>;
 217                                                 reg = <19>;
 218                                                 clocks = <&mck>;
 219                                         };
 220                                 };
 221
 222                                 periph: periphck {
 223                                         compatible = "microchip,sam9x60-clk-peripheral";
 224                                         #address-cells = <1>;
 225                                         #size-cells = <0>;
 226                                         clocks = <&mck>;
 227
 228                                         pioA_clk: pioA_clk {
 229                                                 #clock-cells = <0>;
 230                                                 reg = <2>;
 231                                         };
 232
 233                                         pioB_clk: pioB_clk {
 234                                                 #clock-cells = <0>;
 235                                                 reg = <3>;
 236                                         };
 237
 238                                         flx0_clk: flx0_clk {
 239                                                 #clock-cells = <0>;
 240                                                 reg = <5>;
 241                                         };
 242
 243                                         pioD_clk: pioD_clk {
 244                                                 #clock-cells = <0>;
 245                                                 reg = <44>;
 246                                         };
 247
 248                                         sdhci0_clk: sdhci0_clk {
 249                                                 #clock-cells = <0>;
 250                                                 reg = <12>;
 251                                         };
 252
 253                                         dbgu_clk: dbgu_clk {
 254                                                 #clock-cells = <0>;
 255                                                 reg = <47>;
 256                                         };
 257
 258                                         macb0_clk: macb0_clk {
 259                                                 #clock-cells = <0>;
 260                                                 reg = <24>;
 261                                         };
 262
 263                                         qspi_clk: qspi_clk {
 264                                                 #clock-cells = <0>;
 265                                                 reg = <35>;
 266                                         };
 267                                 };
 268
 269                                 generic: gck {
 270                                         compatible = "microchip,sam9x60-clk-generated";
 271                                         #address-cells = <1>;
 272                                         #size-cells = <0>;
 273                                         clocks = <&clk32 0>, <&clk32 1>, <&main>, <&mck>, <&plla>;
 274
 275                                         sdhci0_gclk: sdhci0_gclk {
 276                                                 #clock-cells = <0>;
 277                                                 reg = <12>;
 278                                         };
 279                                 };
 280                         };
 281
 282                         pit: timer@fffffe40 {
 283                                 compatible = "atmel,at91sam9260-pit";
 284                                 reg = <0xfffffe40 0x10>;
 285                                 clocks = <&mck>;
 286                         };
 287
 288                         clk32: sckc@fffffe50 {
 289                                 compatible = "microchip,sam9x60-sckc";
 290                                 reg = <0xfffffe50 0x4>;
 291                                 clocks = <&slow_rc_osc>, <&slow_xtal>;
 292                                 #clock-cells = <1>;
 293                         };
 294                 };
 295         };
 296
 297         onewire_tm: onewire {
 298                 compatible = "w1-gpio";
 299                 status = "disabled";
 300         };
 301 };