arch/arm/dts/sam9x60.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
   4  *
   5  * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
   6  *
   7  * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
   8  */
   9
  10 #include "skeleton.dtsi"
  11 #include <dt-bindings/dma/at91.h>
  12 #include <dt-bindings/pinctrl/at91.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/clock/at91.h>
  16
  17 /{
  18         model = "Microchip SAM9X60 SoC";
  19         compatible = "microchip,sam9x60";
  20
  21         aliases {
  22                 serial0 = &dbgu;
  23                 gpio0 = &pioA;
  24                 gpio1 = &pioB;
  25                 gpio3 = &pioD;
  26                 spi0 = &qspi;
  27         };
  28
  29         clocks {
  30                 slow_xtal: slow_xtal {
  31                         compatible = "fixed-clock";
  32                         #clock-cells = <0>;
  33                 };
  34
  35                 main_xtal: main_xtal {
  36                         compatible = "fixed-clock";
  37                         #clock-cells = <0>;
  38                 };
  39         };
  40
  41         ahb {
  42                 compatible = "simple-bus";
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 ranges;
  46
  47                 sdhci0: sdhci-host@80000000 {
  48                         compatible = "microchip,sam9x60-sdhci";
  49                         reg = <0x80000000 0x300>;
  50                         clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>;
  51                         clock-names = "hclock", "multclk", "baseclk";
  52                         bus-width = <4>;
  53                         pinctrl-names = "default";
  54                         pinctrl-0 = <&pinctrl_sdhci0>;
  55                 };
  56
  57                 apb {
  58                         compatible = "simple-bus";
  59                         #address-cells = <1>;
  60                         #size-cells = <1>;
  61                         ranges;
  62
  63                         qspi: spi@f0014000 {
  64                                 compatible = "microchip,sam9x60-qspi";
  65                                 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
  66                                 reg-names = "qspi_base", "qspi_mmap";
  67                                 clocks =  <&qspi_clk>, <&qspick>;
  68                                 clock-names = "pclk", "qspick";
  69                                 #address-cells = <1>;
  70                                 #size-cells = <0>;
  71                                 status = "disabled";
  72                         };
  73
  74                         flx0: flexcom@f801c600 {
  75                                 compatible = "atmel,sama5d2-flexcom";
  76                                 reg = <0xf801c000 0x200>;
  77                                 clocks = <&flx0_clk>;
  78                                 #address-cells = <1>;
  79                                 #size-cells = <1>;
  80                                 ranges = <0x0 0xf801c000 0x800>;
  81                                 status = "disabled";
  82                         };
  83
  84                         macb0: ethernet@f802c000 {
  85                                 compatible = "cdns,sam9x60-macb", "cdns,macb";
  86                                 reg = <0xf802c000 0x100>;
  87                                 pinctrl-names = "default";
  88                                 pinctrl-0 = <&pinctrl_macb0_rmii>;
  89                                 clock-names = "hclk", "pclk";
  90                                 clocks = <&macb0_clk>, <&macb0_clk>;
  91                                 status = "disabled";
  92                         };
  93
  94                         dbgu: serial@fffff200 {
  95                                 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
  96                                 reg = <0xfffff200 0x200>;
  97                                 pinctrl-names = "default";
  98                                 pinctrl-0 = <&pinctrl_dbgu>;
  99                                 clocks = <&dbgu_clk>;
 100                                 clock-names = "usart";
 101                         };
 102
 103                         pinctrl {
 104                                 #address-cells = <1>;
 105                                 #size-cells = <1>;
 106                                 compatible = "microchip,sam9x60-pinctrl", "simple-bus";
 107                                 ranges = <0xfffff400 0xfffff400 0x800>;
 108                                 reg = <0xfffff400 0x200         /* pioA */
 109                                        0xfffff600 0x200         /* pioB */
 110                                        0xfffff800 0x200         /* pioC */
 111                                        0xfffffa00 0x200>;       /* pioD */
 112
 113                                 /* shared pinctrl settings */
 114                                 dbgu {
 115                                         pinctrl_dbgu: dbgu-0 {
 116                                                 atmel,pins =
 117                                                         <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
 118                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
 119                                         };
 120                                 };
 121
 122                                 macb0 {
 123                                         pinctrl_macb0_rmii: macb0_rmii-0 {
 124                                                 atmel,pins =
 125                                                         <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
 126                                                          AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
 127                                                          AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A */
 128                                                          AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
 129                                                          AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
 130                                                          AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A */
 131                                                          AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
 132                                                          AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
 133                                                          AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
 134                                                          AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
 135                                         };
 136                                 };
 137
 138                                 sdhci0 {
 139                                         pinctrl_sdhci0: sdhci0 {
 140                                                 atmel,pins =
 141                                                         <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT /* PA17 CK  periph A with pullup */
 142                                                          AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA16 CMD periph A with pullup */
 143                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA15 DAT0 periph A */
 144                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA18 DAT1 periph A with pullup */
 145                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA19 DAT2 periph A with pullup */
 146                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;              /* PA20 DAT3 periph A with pullup */
 147                                         };
 148                                 };
 149                         };
 150
 151                         pioA: gpio@fffff400 {
 152                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 153                                 reg = <0xfffff400 0x200>;
 154                                 #gpio-cells = <2>;
 155                                 gpio-controller;
 156                                 clocks = <&pioA_clk>;
 157                         };
 158
 159                         pioB: gpio@fffff600 {
 160                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 161                                 reg = <0xfffff600 0x200>;
 162                                 #gpio-cells = <2>;
 163                                 gpio-controller;
 164                                 clocks = <&pioB_clk>;
 165                         };
 166
 167                         pioD: gpio@fffffa00 {
 168                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 169                                 reg = <0xfffffa00 0x200>;
 170                                 #gpio-cells = <2>;
 171                                 gpio-controller;
 172                                 clocks = <&pioD_clk>;
 173                         };
 174
 175                         pmc: pmc@fffffc00 {
 176                                 compatible = "atmel,at91sam9x5-pmc";
 177                                 reg = <0xfffffc00 0x200>;
 178                                 #address-cells = <1>;
 179                                 #size-cells = <0>;
 180
 181                                 main: mainck {
 182                                         compatible = "atmel,at91sam9x5-clk-main";
 183                                         #clock-cells = <0>;
 184                                 };
 185
 186                                 plla: pllack {
 187                                         compatible = "microchip,sam9x60-clk-pll";
 188                                         #clock-cells = <0>;
 189                                         clocks = <&main>;
 190                                         reg = <0>;
 191                                         atmel,clk-input-range = <8000000 24000000>;
 192                                         #atmel,pll-clk-output-range-cells = <4>;
 193                                         atmel,pll-clk-output-ranges = <140000000 1200000000 0 0>;
 194                                 };
 195
 196                                 mck: masterck {
 197                                         compatible = "atmel,at91sam9x5-clk-master";
 198                                         #clock-cells = <0>;
 199                                         clocks = <&md_slck>, <&main>, <&plla>;
 200                                         atmel,clk-output-range = <140000000 200000000>;
 201                                         atmel,clk-divisors = <1 2 4 6>;
 202                                 };
 203
 204                                 system: systemck {
 205                                         compatible = "atmel,at91rm9200-clk-system";
 206                                         #address-cells = <1>;
 207                                         #size-cells = <0>;
 208
 209                                         qspick: qspick {
 210                                                 #clock-cells = <0>;
 211                                                 reg = <19>;
 212                                                 clocks = <&mck>;
 213                                         };
 214                                 };
 215
 216                                 periph: periphck {
 217                                         compatible = "microchip,sam9x60-clk-peripheral";
 218                                         #address-cells = <1>;
 219                                         #size-cells = <0>;
 220                                         clocks = <&mck>;
 221
 222                                         pioA_clk: pioA_clk {
 223                                                 #clock-cells = <0>;
 224                                                 reg = <2>;
 225                                         };
 226
 227                                         pioB_clk: pioB_clk {
 228                                                 #clock-cells = <0>;
 229                                                 reg = <3>;
 230                                         };
 231
 232                                         flx0_clk: flx0_clk {
 233                                                 #clock-cells = <0>;
 234                                                 reg = <5>;
 235                                         };
 236
 237                                         pioD_clk: pioD_clk {
 238                                                 #clock-cells = <0>;
 239                                                 reg = <44>;
 240                                         };
 241
 242                                         sdhci0_clk: sdhci0_clk {
 243                                                 #clock-cells = <0>;
 244                                                 reg = <12>;
 245                                         };
 246
 247                                         dbgu_clk: dbgu_clk {
 248                                                 #clock-cells = <0>;
 249                                                 reg = <47>;
 250                                         };
 251
 252                                         macb0_clk: macb0_clk {
 253                                                 #clock-cells = <0>;
 254                                                 reg = <24>;
 255                                         };
 256
 257                                         qspi_clk: qspi_clk {
 258                                                 #clock-cells = <0>;
 259                                                 reg = <35>;
 260                                         };
 261                                 };
 262
 263                                 generic: gck {
 264                                         compatible = "microchip,sam9x60-clk-generated";
 265                                         #address-cells = <1>;
 266                                         #size-cells = <0>;
 267                                         clocks = <&md_slck>, <&td_slck>, <&main>, <&mck>, <&plla>;
 268
 269                                         sdhci0_gclk: sdhci0_gclk {
 270                                                 #clock-cells = <0>;
 271                                                 reg = <12>;
 272                                         };
 273                                 };
 274                         };
 275
 276                         pit: timer@fffffe40 {
 277                                 compatible = "atmel,at91sam9260-pit";
 278                                 reg = <0xfffffe40 0x10>;
 279                                 clocks = <&mck>;
 280                         };
 281
 282                         slowckc: sckc@fffffe50 {
 283                                 compatible = "atmel,at91sam9x5-sckc";
 284                                 reg = <0xfffffe50 0x4>;
 285
 286                                 slow_osc: slow_osc {
 287                                         compatible = "atmel,at91sam9x5-clk-slow-osc";
 288                                         #clock-cells = <0>;
 289                                         clocks = <&slow_xtal>;
 290                                 };
 291
 292                                 slow_rc_osc: slow_rc_osc {
 293                                         compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
 294                                         #clock-cells = <0>;
 295                                         clock-frequency = <32768>;
 296                                 };
 297
 298                                 td_slck: td_slck {
 299                                         compatible = "atmel,at91sam9x5-clk-slow";
 300                                         #clock-cells = <0>;
 301                                         clocks = <&slow_rc_osc>, <&slow_osc>;
 302                                 };
 303
 304                                 md_slck: md_slck {
 305                                         compatible = "atmel,at91sam9x5-clk-slow";
 306                                         #clock-cells = <0>;
 307                                         clocks = <&slow_rc_osc>;
 308                                 };
 309                         };
 310                 };
 311         };
 312
 313         onewire_tm: onewire {
 314                 compatible = "w1-gpio";
 315                 status = "disabled";
 316         };
 317 };