arch/arm/dts/rk3xxx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/soc/rockchip,boot-mode.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 ethernet0 = &emac;
  19                 i2c0 = &i2c0;
  20                 i2c1 = &i2c1;
  21                 i2c2 = &i2c2;
  22                 i2c3 = &i2c3;
  23                 i2c4 = &i2c4;
  24                 serial0 = &uart0;
  25                 serial1 = &uart1;
  26                 serial2 = &uart2;
  27                 serial3 = &uart3;
  28                 spi0 = &spi0;
  29                 spi1 = &spi1;
  30         };
  31
  32         xin24m: oscillator {
  33                 compatible = "fixed-clock";
  34                 clock-frequency = <24000000>;
  35                 #clock-cells = <0>;
  36                 clock-output-names = "xin24m";
  37         };
  38
  39         gpu: gpu@10090000 {
  40                 compatible = "arm,mali-400";
  41                 reg = <0x10090000 0x10000>;
  42                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
  43                 clock-names = "bus", "core";
  44                 assigned-clocks = <&cru ACLK_GPU>;
  45                 assigned-clock-rates = <100000000>;
  46                 resets = <&cru SRST_GPU>;
  47                 status = "disabled";
  48         };
  49
  50         vpu: video-codec@10104000 {
  51                 compatible = "rockchip,rk3066-vpu";
  52                 reg = <0x10104000 0x800>;
  53                 interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
  54                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  55                 interrupt-names = "vepu", "vdpu";
  56                 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
  57                          <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
  58                 clock-names = "aclk_vdpu", "hclk_vdpu",
  59                               "aclk_vepu", "hclk_vepu";
  60         };
  61
  62         L2: cache-controller@10138000 {
  63                 compatible = "arm,pl310-cache";
  64                 reg = <0x10138000 0x1000>;
  65                 cache-unified;
  66                 cache-level = <2>;
  67         };
  68
  69         scu@1013c000 {
  70                 compatible = "arm,cortex-a9-scu";
  71                 reg = <0x1013c000 0x100>;
  72         };
  73
  74         global_timer: global-timer@1013c200 {
  75                 compatible = "arm,cortex-a9-global-timer";
  76                 reg = <0x1013c200 0x20>;
  77                 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
  78                 clocks = <&cru CORE_PERI>;
  79                 status = "disabled";
  80                 /* The clock source and the sched_clock provided by the arm_global_timer
  81                  * on Rockchip rk3066a/rk3188 are quite unstable because their rates
  82                  * depend on the CPU frequency.
  83                  * Keep the arm_global_timer disabled in order to have the
  84                  * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
  85                  */
  86         };
  87
  88         local_timer: local-timer@1013c600 {
  89                 compatible = "arm,cortex-a9-twd-timer";
  90                 reg = <0x1013c600 0x20>;
  91                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
  92                 clocks = <&cru CORE_PERI>;
  93         };
  94
  95         gic: interrupt-controller@1013d000 {
  96                 compatible = "arm,cortex-a9-gic";
  97                 interrupt-controller;
  98                 #interrupt-cells = <3>;
  99                 reg = <0x1013d000 0x1000>,
 100                       <0x1013c100 0x0100>;
 101         };
 102
 103         uart0: serial@10124000 {
 104                 compatible = "snps,dw-apb-uart";
 105                 reg = <0x10124000 0x400>;
 106                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 107                 reg-shift = <2>;
 108                 reg-io-width = <1>;
 109                 clock-names = "baudclk", "apb_pclk";
 110                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 111                 status = "disabled";
 112         };
 113
 114         uart1: serial@10126000 {
 115                 compatible = "snps,dw-apb-uart";
 116                 reg = <0x10126000 0x400>;
 117                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 118                 reg-shift = <2>;
 119                 reg-io-width = <1>;
 120                 clock-names = "baudclk", "apb_pclk";
 121                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 122                 status = "disabled";
 123         };
 124
 125         qos_gpu: qos@1012d000 {
 126                 compatible = "rockchip,rk3066-qos", "syscon";
 127                 reg = <0x1012d000 0x20>;
 128         };
 129
 130         qos_vpu: qos@1012e000 {
 131                 compatible = "rockchip,rk3066-qos", "syscon";
 132                 reg = <0x1012e000 0x20>;
 133         };
 134
 135         qos_lcdc0: qos@1012f000 {
 136                 compatible = "rockchip,rk3066-qos", "syscon";
 137                 reg = <0x1012f000 0x20>;
 138         };
 139
 140         qos_cif0: qos@1012f080 {
 141                 compatible = "rockchip,rk3066-qos", "syscon";
 142                 reg = <0x1012f080 0x20>;
 143         };
 144
 145         qos_ipp: qos@1012f100 {
 146                 compatible = "rockchip,rk3066-qos", "syscon";
 147                 reg = <0x1012f100 0x20>;
 148         };
 149
 150         qos_lcdc1: qos@1012f180 {
 151                 compatible = "rockchip,rk3066-qos", "syscon";
 152                 reg = <0x1012f180 0x20>;
 153         };
 154
 155         qos_cif1: qos@1012f200 {
 156                 compatible = "rockchip,rk3066-qos", "syscon";
 157                 reg = <0x1012f200 0x20>;
 158         };
 159
 160         qos_rga: qos@1012f280 {
 161                 compatible = "rockchip,rk3066-qos", "syscon";
 162                 reg = <0x1012f280 0x20>;
 163         };
 164
 165         usb_otg: usb@10180000 {
 166                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
 167                 reg = <0x10180000 0x40000>;
 168                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 169                 clocks = <&cru HCLK_OTG0>;
 170                 clock-names = "otg";
 171                 dr_mode = "otg";
 172                 g-np-tx-fifo-size = <16>;
 173                 g-rx-fifo-size = <275>;
 174                 g-tx-fifo-size = <256 128 128 64 64 32>;
 175                 phys = <&usbphy0>;
 176                 phy-names = "usb2-phy";
 177                 status = "disabled";
 178         };
 179
 180         usb_host: usb@101c0000 {
 181                 compatible = "snps,dwc2";
 182                 reg = <0x101c0000 0x40000>;
 183                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 184                 clocks = <&cru HCLK_OTG1>;
 185                 clock-names = "otg";
 186                 dr_mode = "host";
 187                 phys = <&usbphy1>;
 188                 phy-names = "usb2-phy";
 189                 status = "disabled";
 190         };
 191
 192         emac: ethernet@10204000 {
 193                 compatible = "snps,arc-emac";
 194                 reg = <0x10204000 0x3c>;
 195                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 196
 197                 rockchip,grf = <&grf>;
 198
 199                 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
 200                 clock-names = "hclk", "macref";
 201                 max-speed = <100>;
 202                 phy-mode = "rmii";
 203
 204                 status = "disabled";
 205         };
 206
 207         mmc0: mmc@10214000 {
 208                 compatible = "rockchip,rk2928-dw-mshc";
 209                 reg = <0x10214000 0x1000>;
 210                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 211                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 212                 clock-names = "biu", "ciu";
 213                 dmas = <&dmac2 1>;
 214                 dma-names = "rx-tx";
 215                 fifo-depth = <256>;
 216                 resets = <&cru SRST_SDMMC>;
 217                 reset-names = "reset";
 218                 status = "disabled";
 219         };
 220
 221         mmc1: mmc@10218000 {
 222                 compatible = "rockchip,rk2928-dw-mshc";
 223                 reg = <0x10218000 0x1000>;
 224                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 225                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 226                 clock-names = "biu", "ciu";
 227                 dmas = <&dmac2 3>;
 228                 dma-names = "rx-tx";
 229                 fifo-depth = <256>;
 230                 resets = <&cru SRST_SDIO>;
 231                 reset-names = "reset";
 232                 status = "disabled";
 233         };
 234
 235         emmc: mmc@1021c000 {
 236                 compatible = "rockchip,rk2928-dw-mshc";
 237                 reg = <0x1021c000 0x1000>;
 238                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 239                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 240                 clock-names = "biu", "ciu";
 241                 dmas = <&dmac2 4>;
 242                 dma-names = "rx-tx";
 243                 fifo-depth = <256>;
 244                 resets = <&cru SRST_EMMC>;
 245                 reset-names = "reset";
 246                 status = "disabled";
 247         };
 248
 249         nfc: nand-controller@10500000 {
 250                 compatible = "rockchip,rk2928-nfc";
 251                 reg = <0x10500000 0x4000>;
 252                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 253                 clocks = <&cru HCLK_NANDC0>;
 254                 clock-names = "ahb";
 255                 status = "disabled";
 256         };
 257
 258         pmu: pmu@20004000 {
 259                 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
 260                 reg = <0x20004000 0x100>;
 261
 262                 reboot-mode {
 263                         compatible = "syscon-reboot-mode";
 264                         offset = <0x40>;
 265                         mode-normal = <BOOT_NORMAL>;
 266                         mode-recovery = <BOOT_RECOVERY>;
 267                         mode-bootloader = <BOOT_FASTBOOT>;
 268                         mode-loader = <BOOT_BL_DOWNLOAD>;
 269                 };
 270         };
 271
 272         grf: grf@20008000 {
 273                 compatible = "syscon", "simple-mfd";
 274                 reg = <0x20008000 0x200>;
 275         };
 276
 277         dmac1_s: dma-controller@20018000 {
 278                 compatible = "arm,pl330", "arm,primecell";
 279                 reg = <0x20018000 0x4000>;
 280                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 282                 #dma-cells = <1>;
 283                 arm,pl330-broken-no-flushp;
 284                 arm,pl330-periph-burst;
 285                 clocks = <&cru ACLK_DMA1>;
 286                 clock-names = "apb_pclk";
 287         };
 288
 289         dmac1_ns: dma-controller@2001c000 {
 290                 compatible = "arm,pl330", "arm,primecell";
 291                 reg = <0x2001c000 0x4000>;
 292                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 294                 #dma-cells = <1>;
 295                 arm,pl330-broken-no-flushp;
 296                 arm,pl330-periph-burst;
 297                 clocks = <&cru ACLK_DMA1>;
 298                 clock-names = "apb_pclk";
 299                 status = "disabled";
 300         };
 301
 302         i2c0: i2c@2002d000 {
 303                 compatible = "rockchip,rk3066-i2c";
 304                 reg = <0x2002d000 0x1000>;
 305                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 306                 #address-cells = <1>;
 307                 #size-cells = <0>;
 308
 309                 rockchip,grf = <&grf>;
 310
 311                 clock-names = "i2c";
 312                 clocks = <&cru PCLK_I2C0>;
 313
 314                 status = "disabled";
 315         };
 316
 317         i2c1: i2c@2002f000 {
 318                 compatible = "rockchip,rk3066-i2c";
 319                 reg = <0x2002f000 0x1000>;
 320                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 321                 #address-cells = <1>;
 322                 #size-cells = <0>;
 323
 324                 rockchip,grf = <&grf>;
 325
 326                 clocks = <&cru PCLK_I2C1>;
 327                 clock-names = "i2c";
 328
 329                 status = "disabled";
 330         };
 331
 332         pwm0: pwm@20030000 {
 333                 compatible = "rockchip,rk2928-pwm";
 334                 reg = <0x20030000 0x10>;
 335                 #pwm-cells = <2>;
 336                 clocks = <&cru PCLK_PWM01>;
 337                 status = "disabled";
 338         };
 339
 340         pwm1: pwm@20030010 {
 341                 compatible = "rockchip,rk2928-pwm";
 342                 reg = <0x20030010 0x10>;
 343                 #pwm-cells = <2>;
 344                 clocks = <&cru PCLK_PWM01>;
 345                 status = "disabled";
 346         };
 347
 348         wdt: watchdog@2004c000 {
 349                 compatible = "snps,dw-wdt";
 350                 reg = <0x2004c000 0x100>;
 351                 clocks = <&cru PCLK_WDT>;
 352                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 353                 status = "disabled";
 354         };
 355
 356         pwm2: pwm@20050020 {
 357                 compatible = "rockchip,rk2928-pwm";
 358                 reg = <0x20050020 0x10>;
 359                 #pwm-cells = <2>;
 360                 clocks = <&cru PCLK_PWM23>;
 361                 status = "disabled";
 362         };
 363
 364         pwm3: pwm@20050030 {
 365                 compatible = "rockchip,rk2928-pwm";
 366                 reg = <0x20050030 0x10>;
 367                 #pwm-cells = <2>;
 368                 clocks = <&cru PCLK_PWM23>;
 369                 status = "disabled";
 370         };
 371
 372         i2c2: i2c@20056000 {
 373                 compatible = "rockchip,rk3066-i2c";
 374                 reg = <0x20056000 0x1000>;
 375                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378
 379                 rockchip,grf = <&grf>;
 380
 381                 clocks = <&cru PCLK_I2C2>;
 382                 clock-names = "i2c";
 383
 384                 status = "disabled";
 385         };
 386
 387         i2c3: i2c@2005a000 {
 388                 compatible = "rockchip,rk3066-i2c";
 389                 reg = <0x2005a000 0x1000>;
 390                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393
 394                 rockchip,grf = <&grf>;
 395
 396                 clocks = <&cru PCLK_I2C3>;
 397                 clock-names = "i2c";
 398
 399                 status = "disabled";
 400         };
 401
 402         i2c4: i2c@2005e000 {
 403                 compatible = "rockchip,rk3066-i2c";
 404                 reg = <0x2005e000 0x1000>;
 405                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408
 409                 rockchip,grf = <&grf>;
 410
 411                 clocks = <&cru PCLK_I2C4>;
 412                 clock-names = "i2c";
 413
 414                 status = "disabled";
 415         };
 416
 417         uart2: serial@20064000 {
 418                 compatible = "snps,dw-apb-uart";
 419                 reg = <0x20064000 0x400>;
 420                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 421                 reg-shift = <2>;
 422                 reg-io-width = <1>;
 423                 clock-names = "baudclk", "apb_pclk";
 424                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 425                 status = "disabled";
 426         };
 427
 428         uart3: serial@20068000 {
 429                 compatible = "snps,dw-apb-uart";
 430                 reg = <0x20068000 0x400>;
 431                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 432                 reg-shift = <2>;
 433                 reg-io-width = <1>;
 434                 clock-names = "baudclk", "apb_pclk";
 435                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 436                 status = "disabled";
 437         };
 438
 439         saradc: saradc@2006c000 {
 440                 compatible = "rockchip,saradc";
 441                 reg = <0x2006c000 0x100>;
 442                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 443                 #io-channel-cells = <1>;
 444                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 445                 clock-names = "saradc", "apb_pclk";
 446                 resets = <&cru SRST_SARADC>;
 447                 reset-names = "saradc-apb";
 448                 status = "disabled";
 449         };
 450
 451         spi0: spi@20070000 {
 452                 compatible = "rockchip,rk3066-spi";
 453                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 454                 clock-names = "spiclk", "apb_pclk";
 455                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 456                 reg = <0x20070000 0x1000>;
 457                 #address-cells = <1>;
 458                 #size-cells = <0>;
 459                 dmas = <&dmac2 10>, <&dmac2 11>;
 460                 dma-names = "tx", "rx";
 461                 status = "disabled";
 462         };
 463
 464         spi1: spi@20074000 {
 465                 compatible = "rockchip,rk3066-spi";
 466                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 467                 clock-names = "spiclk", "apb_pclk";
 468                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 469                 reg = <0x20074000 0x1000>;
 470                 #address-cells = <1>;
 471                 #size-cells = <0>;
 472                 dmas = <&dmac2 12>, <&dmac2 13>;
 473                 dma-names = "tx", "rx";
 474                 status = "disabled";
 475         };
 476
 477         dmac2: dma-controller@20078000 {
 478                 compatible = "arm,pl330", "arm,primecell";
 479                 reg = <0x20078000 0x4000>;
 480                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 481                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 482                 #dma-cells = <1>;
 483                 arm,pl330-broken-no-flushp;
 484                 arm,pl330-periph-burst;
 485                 clocks = <&cru ACLK_DMA2>;
 486                 clock-names = "apb_pclk";
 487         };
 488 };