arch/arm/dts/rk3588s-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
   4  */
   5
   6 #include "rockchip-u-boot.dtsi"
   7
   8 / {
   9         dmc {
  10                 compatible = "rockchip,rk3588-dmc";
  11                 bootph-all;
  12                 status = "okay";
  13         };
  14
  15         pmu1_grf: syscon@fd58a000 {
  16                 bootph-all;
  17                 compatible = "rockchip,rk3588-pmu1-grf", "syscon";
  18                 reg = <0x0 0xfd58a000 0x0 0x2000>;
  19         };
  20
  21         otp: nvmem@fecc0000 {
  22                 compatible = "rockchip,rk3588-otp";
  23                 reg = <0x0 0xfecc0000 0x0 0x400>;
  24                 #address-cells = <1>;
  25                 #size-cells = <1>;
  26                 status = "okay";
  27
  28                 cpu_id: id@7 {
  29                         reg = <0x07 0x10>;
  30                 };
  31         };
  32
  33         rng: rng@fe378000 {
  34                 compatible = "rockchip,trngv1";
  35                 reg = <0x0 0xfe378000 0x0 0x200>;
  36                 status = "disabled";
  37         };
  38 };
  39
  40 &xin24m {
  41         bootph-all;
  42         status = "okay";
  43 };
  44
  45 &cru {
  46         bootph-pre-ram;
  47         status = "okay";
  48 };
  49
  50 &sys_grf {
  51         bootph-pre-ram;
  52         status = "okay";
  53 };
  54
  55 &scmi {
  56         bootph-pre-ram;
  57 };
  58
  59 &scmi_clk {
  60         bootph-pre-ram;
  61 };
  62
  63 &sdmmc {
  64         bootph-pre-ram;
  65         u-boot,spl-fifo-mode;
  66 };
  67
  68 &sdhci {
  69         bootph-pre-ram;
  70 };
  71
  72 &uart2 {
  73         clock-frequency = <24000000>;
  74         bootph-pre-ram;
  75         status = "okay";
  76 };
  77
  78 &ioc {
  79         bootph-pre-ram;
  80 };