dts: rk3399: add gmac for the rk3399
[platform/kernel/u-boot.git] / arch / arm / dts / rk3399.dtsi
1 /*
2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <dt-bindings/clock/rk3399-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #define USB_CLASS_HUB                   9
13
14 / {
15         compatible = "rockchip,rk3399";
16
17         interrupt-parent = <&gic>;
18         #address-cells = <2>;
19         #size-cells = <2>;
20
21         aliases {
22                 serial0 = &uart0;
23                 serial1 = &uart1;
24                 serial2 = &uart2;
25                 serial3 = &uart3;
26                 serial4 = &uart4;
27                 mmc0 = &sdhci;
28                 mmc1 = &sdmmc;
29         };
30
31         cpus {
32                 #address-cells = <2>;
33                 #size-cells = <0>;
34
35                 cpu-map {
36                         cluster0 {
37                                 core0 {
38                                         cpu = <&cpu_l0>;
39                                 };
40                                 core1 {
41                                         cpu = <&cpu_l1>;
42                                 };
43                                 core2 {
44                                         cpu = <&cpu_l2>;
45                                 };
46                                 core3 {
47                                         cpu = <&cpu_l3>;
48                                 };
49                         };
50
51                         cluster1 {
52                                 core0 {
53                                         cpu = <&cpu_b0>;
54                                 };
55                                 core1 {
56                                         cpu = <&cpu_b1>;
57                                 };
58                         };
59                 };
60
61                 cpu_l0: cpu@0 {
62                         device_type = "cpu";
63                         compatible = "arm,cortex-a53", "arm,armv8";
64                         reg = <0x0 0x0>;
65                         enable-method = "psci";
66                         #cooling-cells = <2>; /* min followed by max */
67                         clocks = <&cru ARMCLKL>;
68                 };
69
70                 cpu_l1: cpu@1 {
71                         device_type = "cpu";
72                         compatible = "arm,cortex-a53", "arm,armv8";
73                         reg = <0x0 0x1>;
74                         enable-method = "psci";
75                         clocks = <&cru ARMCLKL>;
76                 };
77
78                 cpu_l2: cpu@2 {
79                         device_type = "cpu";
80                         compatible = "arm,cortex-a53", "arm,armv8";
81                         reg = <0x0 0x2>;
82                         enable-method = "psci";
83                         clocks = <&cru ARMCLKL>;
84                 };
85
86                 cpu_l3: cpu@3 {
87                         device_type = "cpu";
88                         compatible = "arm,cortex-a53", "arm,armv8";
89                         reg = <0x0 0x3>;
90                         enable-method = "psci";
91                         clocks = <&cru ARMCLKL>;
92                 };
93
94                 cpu_b0: cpu@100 {
95                         device_type = "cpu";
96                         compatible = "arm,cortex-a72", "arm,armv8";
97                         reg = <0x0 0x100>;
98                         enable-method = "psci";
99                         #cooling-cells = <2>; /* min followed by max */
100                         clocks = <&cru ARMCLKB>;
101                 };
102
103                 cpu_b1: cpu@101 {
104                         device_type = "cpu";
105                         compatible = "arm,cortex-a72", "arm,armv8";
106                         reg = <0x0 0x101>;
107                         enable-method = "psci";
108                         clocks = <&cru ARMCLKB>;
109                 };
110         };
111
112         psci {
113                 compatible = "arm,psci-1.0";
114                 method = "smc";
115         };
116
117         timer {
118                 compatible = "arm,armv8-timer";
119                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
120                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
121                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
122                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
123         };
124
125         xin24m: xin24m {
126                 compatible = "fixed-clock";
127                 clock-frequency = <24000000>;
128                 clock-output-names = "xin24m";
129                 #clock-cells = <0>;
130         };
131
132         amba {
133                 compatible = "simple-bus";
134                 #address-cells = <2>;
135                 #size-cells = <2>;
136                 ranges;
137
138                 dmac_bus: dma-controller@ff6d0000 {
139                         compatible = "arm,pl330", "arm,primecell";
140                         reg = <0x0 0xff6d0000 0x0 0x4000>;
141                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
142                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
143                         #dma-cells = <1>;
144                         clocks = <&cru ACLK_DMAC0_PERILP>;
145                         clock-names = "apb_pclk";
146                 };
147
148                 dmac_peri: dma-controller@ff6e0000 {
149                         compatible = "arm,pl330", "arm,primecell";
150                         reg = <0x0 0xff6e0000 0x0 0x4000>;
151                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
152                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
153                         #dma-cells = <1>;
154                         clocks = <&cru ACLK_DMAC1_PERILP>;
155                         clock-names = "apb_pclk";
156                 };
157         };
158
159         sdio0: dwmmc@fe310000 {
160                 compatible = "rockchip,rk3399-dw-mshc",
161                              "rockchip,rk3288-dw-mshc";
162                 reg = <0x0 0xfe310000 0x0 0x4000>;
163                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
164                 clock-freq-min-max = <400000 150000000>;
165                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
166                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
167                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
168                 fifo-depth = <0x100>;
169                 status = "disabled";
170         };
171
172         sdmmc: dwmmc@fe320000 {
173                 compatible = "rockchip,rk3399-dw-mshc",
174                              "rockchip,rk3288-dw-mshc";
175                 reg = <0x0 0xfe320000 0x0 0x4000>;
176                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
177                 clock-freq-min-max = <400000 150000000>;
178                 clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>,
179                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
180                 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
181                 pinctrl-names = "default";
182                 pinctrl-0 = <&sdmmc_clk>;
183                 fifo-depth = <0x100>;
184                 status = "disabled";
185         };
186
187         sdhci: sdhci@fe330000 {
188                 u-boot,dm-pre-reloc;
189                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
190                 reg = <0x0 0xfe330000 0x0 0x10000>;
191                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
192                 assigned-clocks = <&cru SCLK_EMMC>;
193                 assigned-clock-rates = <200000000>;
194                 max-frequency = <200000000>;
195                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
196                 clock-names = "clk_xin", "clk_ahb";
197                 phys = <&emmc_phy>;
198                 phy-names = "phy_arasan";
199                 status = "disabled";
200         };
201
202         usb_host0_ehci: usb@fe380000 {
203                 compatible = "generic-ehci";
204                 reg = <0x0 0xfe380000 0x0 0x20000>;
205                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
206                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
207                 clock-names = "hclk_host0", "hclk_host0_arb";
208                 status = "disabled";
209         };
210
211         usb_host0_ohci: usb@fe3a0000 {
212                 compatible = "generic-ohci";
213                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
214                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
215                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
216                 clock-names = "hclk_host0", "hclk_host0_arb";
217                 status = "disabled";
218         };
219
220         usb_host1_ehci: usb@fe3c0000 {
221                 compatible = "generic-ehci";
222                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
223                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
224                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
225                 clock-names = "hclk_host1", "hclk_host1_arb";
226                 status = "disabled";
227         };
228
229         usb_host1_ohci: usb@fe3e0000 {
230                 compatible = "generic-ohci";
231                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
232                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
233                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
234                 clock-names = "hclk_host1", "hclk_host1_arb";
235                 status = "disabled";
236         };
237
238         dwc3_typec0: usb@fe800000 {
239                 compatible = "rockchip,rk3399-xhci";
240                 reg = <0x0 0xfe800000 0x0 0x100000>;
241                 status = "disabled";
242                 rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
243                 snps,dis-enblslpm-quirk;
244                 snps,phyif-utmi-bits = <16>;
245                 snps,dis-u2-freeclk-exists-quirk;
246                 snps,dis-u2-susphy-quirk;
247
248                 #address-cells = <2>;
249                 #size-cells = <2>;
250                 hub {
251                         compatible = "usb-hub";
252                         usb,device-class = <USB_CLASS_HUB>;
253                 };
254                 typec_phy0 {
255                         compatible = "rockchip,rk3399-usb3-phy";
256                         reg = <0x0 0xff7c0000 0x0 0x40000>;
257                 };
258         };
259
260         dwc3_typec1: usb@fe900000 {
261                 compatible = "rockchip,rk3399-xhci";
262                 reg = <0x0 0xfe900000 0x0 0x100000>;
263                 status = "disabled";
264                 rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
265                 snps,dis-enblslpm-quirk;
266                 snps,phyif-utmi-bits = <16>;
267                 snps,dis-u2-freeclk-exists-quirk;
268                 snps,dis-u2-susphy-quirk;
269
270                 #address-cells = <2>;
271                 #size-cells = <2>;
272                 hub {
273                         compatible = "usb-hub";
274                         usb,device-class = <USB_CLASS_HUB>;
275                 };
276                 typec_phy1 {
277                         compatible = "rockchip,rk3399-usb3-phy";
278                         reg = <0x0 0xff800000 0x0 0x40000>;
279                 };
280         };
281
282         gic: interrupt-controller@fee00000 {
283                 compatible = "arm,gic-v3";
284                 #interrupt-cells = <3>;
285                 #address-cells = <2>;
286                 #size-cells = <2>;
287                 ranges;
288                 interrupt-controller;
289
290                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
291                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
292                       <0x0 0xfff00000 0 0x10000>, /* GICC */
293                       <0x0 0xfff10000 0 0x10000>, /* GICH */
294                       <0x0 0xfff20000 0 0x10000>; /* GICV */
295                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
296                 its: interrupt-controller@fee20000 {
297                         compatible = "arm,gic-v3-its";
298                         msi-controller;
299                         reg = <0x0 0xfee20000 0x0 0x20000>;
300                 };
301         };
302
303         uart0: serial@ff180000 {
304                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
305                 reg = <0x0 0xff180000 0x0 0x100>;
306                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
307                 clock-names = "baudclk", "apb_pclk";
308                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
309                 reg-shift = <2>;
310                 reg-io-width = <4>;
311                 pinctrl-names = "default";
312                 pinctrl-0 = <&uart0_xfer>;
313                 status = "disabled";
314         };
315
316         uart1: serial@ff190000 {
317                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
318                 reg = <0x0 0xff190000 0x0 0x100>;
319                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
320                 clock-names = "baudclk", "apb_pclk";
321                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
322                 reg-shift = <2>;
323                 reg-io-width = <4>;
324                 pinctrl-names = "default";
325                 pinctrl-0 = <&uart1_xfer>;
326                 status = "disabled";
327         };
328
329         uart2: serial@ff1a0000 {
330                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
331                 reg = <0x0 0xff1a0000 0x0 0x100>;
332                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
333                 clock-names = "baudclk", "apb_pclk";
334                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
335                 clock-frequency = <24000000>;
336                 reg-shift = <2>;
337                 reg-io-width = <4>;
338                 pinctrl-names = "default";
339                 pinctrl-0 = <&uart2c_xfer>;
340                 status = "disabled";
341         };
342
343         uart3: serial@ff1b0000 {
344                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
345                 reg = <0x0 0xff1b0000 0x0 0x100>;
346                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
347                 clock-names = "baudclk", "apb_pclk";
348                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
349                 reg-shift = <2>;
350                 reg-io-width = <4>;
351                 pinctrl-names = "default";
352                 pinctrl-0 = <&uart3_xfer>;
353                 status = "disabled";
354         };
355
356         spi0: spi@ff1c0000 {
357                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
358                 reg = <0x0 0xff1c0000 0x0 0x1000>;
359                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
360                 clock-names = "spiclk", "apb_pclk";
361                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
362                 pinctrl-names = "default";
363                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
364                 #address-cells = <1>;
365                 #size-cells = <0>;
366                 status = "disabled";
367         };
368
369         spi1: spi@ff1d0000 {
370                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
371                 reg = <0x0 0xff1d0000 0x0 0x1000>;
372                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
373                 clock-names = "spiclk", "apb_pclk";
374                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
375                 pinctrl-names = "default";
376                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
377                 #address-cells = <1>;
378                 #size-cells = <0>;
379                 status = "disabled";
380         };
381
382         spi2: spi@ff1e0000 {
383                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
384                 reg = <0x0 0xff1e0000 0x0 0x1000>;
385                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
386                 clock-names = "spiclk", "apb_pclk";
387                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
388                 pinctrl-names = "default";
389                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
390                 #address-cells = <1>;
391                 #size-cells = <0>;
392                 status = "disabled";
393         };
394
395         spi4: spi@ff1f0000 {
396                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
397                 reg = <0x0 0xff1f0000 0x0 0x1000>;
398                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
399                 clock-names = "spiclk", "apb_pclk";
400                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
401                 pinctrl-names = "default";
402                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
403                 #address-cells = <1>;
404                 #size-cells = <0>;
405                 status = "disabled";
406         };
407
408         spi5: spi@ff200000 {
409                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
410                 reg = <0x0 0xff200000 0x0 0x1000>;
411                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
412                 clock-names = "spiclk", "apb_pclk";
413                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
414                 pinctrl-names = "default";
415                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
416                 #address-cells = <1>;
417                 #size-cells = <0>;
418                 status = "disabled";
419         };
420
421         pmugrf: syscon@ff320000 {
422                 u-boot,dm-pre-reloc;
423                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
424                 reg = <0x0 0xff320000 0x0 0x1000>;
425                 #address-cells = <1>;
426                 #size-cells = <1>;
427
428                 pmu_io_domains: io-domains {
429                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
430                         status = "disabled";
431                 };
432         };
433
434         pmusgrf: syscon@ff330000 {
435                 u-boot,dm-pre-reloc;
436                 compatible = "rockchip,rk3399-pmusgrf", "syscon";
437                 reg = <0x0 0xff330000 0x0 0xe3d4>;
438         };
439
440         spi3: spi@ff350000 {
441                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
442                 reg = <0x0 0xff350000 0x0 0x1000>;
443                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
444                 clock-names = "spiclk", "apb_pclk";
445                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
446                 pinctrl-names = "default";
447                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
448                 #address-cells = <1>;
449                 #size-cells = <0>;
450                 status = "disabled";
451         };
452
453         uart4: serial@ff370000 {
454                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
455                 reg = <0x0 0xff370000 0x0 0x100>;
456                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
457                 clock-names = "baudclk", "apb_pclk";
458                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
459                 reg-shift = <2>;
460                 reg-io-width = <4>;
461                 pinctrl-names = "default";
462                 pinctrl-0 = <&uart4_xfer>;
463                 status = "disabled";
464         };
465
466         pwm0: pwm@ff420000 {
467                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
468                 reg = <0x0 0xff420000 0x0 0x10>;
469                 #pwm-cells = <3>;
470                 pinctrl-names = "default";
471                 pinctrl-0 = <&pwm0_pin>;
472                 clocks = <&pmucru PCLK_RKPWM_PMU>;
473                 clock-names = "pwm";
474                 status = "disabled";
475         };
476
477         pwm1: pwm@ff420010 {
478                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
479                 reg = <0x0 0xff420010 0x0 0x10>;
480                 #pwm-cells = <3>;
481                 pinctrl-names = "default";
482                 pinctrl-0 = <&pwm1_pin>;
483                 clocks = <&pmucru PCLK_RKPWM_PMU>;
484                 clock-names = "pwm";
485                 status = "disabled";
486         };
487
488         pwm2: pwm@ff420020 {
489                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
490                 reg = <0x0 0xff420020 0x0 0x10>;
491                 #pwm-cells = <3>;
492                 pinctrl-names = "default";
493                 pinctrl-0 = <&pwm2_pin>;
494                 clocks = <&pmucru PCLK_RKPWM_PMU>;
495                 clock-names = "pwm";
496                 status = "disabled";
497         };
498
499         pwm3: pwm@ff420030 {
500                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
501                 reg = <0x0 0xff420030 0x0 0x10>;
502                 #pwm-cells = <3>;
503                 pinctrl-names = "default";
504                 pinctrl-0 = <&pwm3a_pin>;
505                 clocks = <&pmucru PCLK_RKPWM_PMU>;
506                 clock-names = "pwm";
507                 status = "disabled";
508         };
509
510         cic: syscon@ff620000 {
511                 u-boot,dm-pre-reloc;
512                 compatible = "rockchip,rk3399-cic", "syscon";
513                 reg = <0x0 0xff620000 0x0 0x100>;
514         };
515
516         dfi: dfi@ff630000 {
517                 reg = <0x00 0xff630000 0x00 0x4000>;
518                 compatible = "rockchip,rk3399-dfi";
519                 rockchip,pmu = <&pmugrf>;
520                 clocks = <&cru PCLK_DDR_MON>;
521                 clock-names = "pclk_ddr_mon";
522                 status = "disabled";
523         };
524
525         dmc: dmc {
526                 u-boot,dm-pre-reloc;
527                 compatible = "rockchip,rk3399-dmc";
528                 devfreq-events = <&dfi>;
529                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
530                 clocks = <&cru SCLK_DDRCLK>;
531                 clock-names = "dmc_clk";
532                 reg = <0x0 0xffa80000 0x0 0x0800
533                        0x0 0xffa80800 0x0 0x1800
534                        0x0 0xffa82000 0x0 0x2000
535                        0x0 0xffa84000 0x0 0x1000
536                        0x0 0xffa88000 0x0 0x0800
537                        0x0 0xffa88800 0x0 0x1800
538                        0x0 0xffa8a000 0x0 0x2000
539                        0x0 0xffa8c000 0x0 0x1000>;
540         };
541
542         pmucru: pmu-clock-controller@ff750000 {
543                 u-boot,dm-pre-reloc;
544                 compatible = "rockchip,rk3399-pmucru";
545                 reg = <0x0 0xff750000 0x0 0x1000>;
546                 #clock-cells = <1>;
547                 #reset-cells = <1>;
548                 assigned-clocks = <&pmucru PLL_PPLL>;
549                 assigned-clock-rates = <676000000>;
550         };
551
552         cru: clock-controller@ff760000 {
553                 u-boot,dm-pre-reloc;
554                 compatible = "rockchip,rk3399-cru";
555                 reg = <0x0 0xff760000 0x0 0x1000>;
556                 #clock-cells = <1>;
557                 #reset-cells = <1>;
558                 assigned-clocks =
559                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
560                         <&cru PLL_NPLL>,
561                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
562                         <&cru PCLK_PERIHP>,
563                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
564                         <&cru PCLK_PERILP0>,
565                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
566                 assigned-clock-rates =
567                          <594000000>,  <800000000>,
568                         <1000000000>,
569                          <150000000>,   <75000000>,
570                           <37500000>,
571                          <100000000>,  <100000000>,
572                           <50000000>,
573                          <100000000>,   <50000000>;
574         };
575
576         grf: syscon@ff770000 {
577                 u-boot,dm-pre-reloc;
578                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
579                 reg = <0x0 0xff770000 0x0 0x10000>;
580                 #address-cells = <1>;
581                 #size-cells = <1>;
582
583                 io_domains: io-domains {
584                         compatible = "rockchip,rk3399-io-voltage-domain";
585                         status = "disabled";
586                 };
587
588                 emmc_phy: phy@f780 {
589                         compatible = "rockchip,rk3399-emmc-phy";
590                         reg = <0xf780 0x24>;
591                         #phy-cells = <0>;
592                         status = "disabled";
593                 };
594         };
595
596         watchdog@ff840000 {
597                 compatible = "snps,dw-wdt";
598                 reg = <0x0 0xff840000 0x0 0x100>;
599                 clocks = <&cru PCLK_WDT>;
600                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
601         };
602
603         gmac: eth@fe300000 {
604                 compatible = "rockchip,rk3399-gmac";
605                 reg = <0x0 0xfe300000 0x0 0x10000>;
606                 rockchip,grf = <&grf>;
607                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
608                 interrupt-names = "macirq";
609                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
610                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
611                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
612                          <&cru PCLK_GMAC>;
613                 clock-names = "stmmaceth", "mac_clk_rx",
614                               "mac_clk_tx", "clk_mac_ref",
615                               "clk_mac_refout", "aclk_mac",
616                               "pclk_mac";
617                 resets = <&cru SRST_A_GMAC>;
618                 reset-names = "stmmaceth";
619                 status = "disabled";
620         };
621
622         spdif: spdif@ff870000 {
623                 compatible = "rockchip,rk3399-spdif";
624                 reg = <0x0 0xff870000 0x0 0x1000>;
625                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
626                 dmas = <&dmac_bus 7>;
627                 dma-names = "tx";
628                 clock-names = "mclk", "hclk";
629                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
630                 pinctrl-names = "default";
631                 pinctrl-0 = <&spdif_bus>;
632                 status = "disabled";
633         };
634
635         i2s0: i2s@ff880000 {
636                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
637                 reg = <0x0 0xff880000 0x0 0x1000>;
638                 rockchip,grf = <&grf>;
639                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
640                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
641                 dma-names = "tx", "rx";
642                 clock-names = "i2s_clk", "i2s_hclk";
643                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
644                 pinctrl-names = "default";
645                 pinctrl-0 = <&i2s0_8ch_bus>;
646                 status = "disabled";
647         };
648
649         i2s1: i2s@ff890000 {
650                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
651                 reg = <0x0 0xff890000 0x0 0x1000>;
652                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
653                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
654                 dma-names = "tx", "rx";
655                 clock-names = "i2s_clk", "i2s_hclk";
656                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
657                 pinctrl-names = "default";
658                 pinctrl-0 = <&i2s1_2ch_bus>;
659                 status = "disabled";
660         };
661
662         i2s2: i2s@ff8a0000 {
663                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
664                 reg = <0x0 0xff8a0000 0x0 0x1000>;
665                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
666                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
667                 dma-names = "tx", "rx";
668                 clock-names = "i2s_clk", "i2s_hclk";
669                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
670                 status = "disabled";
671         };
672
673         pinctrl: pinctrl {
674                 u-boot,dm-pre-reloc;
675                 compatible = "rockchip,rk3399-pinctrl";
676                 rockchip,grf = <&grf>;
677                 rockchip,pmu = <&pmugrf>;
678                 #address-cells = <2>;
679                 #size-cells = <2>;
680                 ranges;
681
682                 gpio0: gpio0@ff720000 {
683                         compatible = "rockchip,gpio-bank";
684                         reg = <0x0 0xff720000 0x0 0x100>;
685                         clocks = <&pmucru PCLK_GPIO0_PMU>;
686                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
687
688                         gpio-controller;
689                         #gpio-cells = <0x2>;
690
691                         interrupt-controller;
692                         #interrupt-cells = <0x2>;
693                 };
694
695                 gpio1: gpio1@ff730000 {
696                         compatible = "rockchip,gpio-bank";
697                         reg = <0x0 0xff730000 0x0 0x100>;
698                         clocks = <&pmucru PCLK_GPIO1_PMU>;
699                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
700
701                         gpio-controller;
702                         #gpio-cells = <0x2>;
703
704                         interrupt-controller;
705                         #interrupt-cells = <0x2>;
706                 };
707
708                 gpio2: gpio2@ff780000 {
709                         compatible = "rockchip,gpio-bank";
710                         reg = <0x0 0xff780000 0x0 0x100>;
711                         clocks = <&cru PCLK_GPIO2>;
712                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
713
714                         gpio-controller;
715                         #gpio-cells = <0x2>;
716
717                         interrupt-controller;
718                         #interrupt-cells = <0x2>;
719                 };
720
721                 gpio3: gpio3@ff788000 {
722                         compatible = "rockchip,gpio-bank";
723                         reg = <0x0 0xff788000 0x0 0x100>;
724                         clocks = <&cru PCLK_GPIO3>;
725                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
726
727                         gpio-controller;
728                         #gpio-cells = <0x2>;
729
730                         interrupt-controller;
731                         #interrupt-cells = <0x2>;
732                 };
733
734                 gpio4: gpio4@ff790000 {
735                         compatible = "rockchip,gpio-bank";
736                         reg = <0x0 0xff790000 0x0 0x100>;
737                         clocks = <&cru PCLK_GPIO4>;
738                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
739
740                         gpio-controller;
741                         #gpio-cells = <0x2>;
742
743                         interrupt-controller;
744                         #interrupt-cells = <0x2>;
745                 };
746
747                 pcfg_pull_up: pcfg-pull-up {
748                         bias-pull-up;
749                 };
750
751                 pcfg_pull_down: pcfg-pull-down {
752                         bias-pull-down;
753                 };
754
755                 pcfg_pull_none: pcfg-pull-none {
756                         bias-disable;
757                 };
758
759                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
760                         bias-disable;
761                         drive-strength = <12>;
762                 };
763
764                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
765                         bias-pull-up;
766                         drive-strength = <8>;
767                 };
768
769                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
770                         bias-pull-down;
771                         drive-strength = <4>;
772                 };
773
774                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
775                         bias-pull-up;
776                         drive-strength = <2>;
777                 };
778
779                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
780                         bias-pull-down;
781                         drive-strength = <12>;
782                 };
783
784                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
785                         bias-disable;
786                         drive-strength = <13>;
787                 };
788
789                 i2c0 {
790                         i2c0_xfer: i2c0-xfer {
791                                 rockchip,pins =
792                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
793                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
794                         };
795                 };
796
797                 i2c1 {
798                         i2c1_xfer: i2c1-xfer {
799                                 rockchip,pins =
800                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
801                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
802                         };
803                 };
804
805                 i2c2 {
806                         i2c2_xfer: i2c2-xfer {
807                                 rockchip,pins =
808                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
809                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
810                         };
811                 };
812
813                 i2c3 {
814                         i2c3_xfer: i2c3-xfer {
815                                 rockchip,pins =
816                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
817                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
818                         };
819                 };
820
821                 i2c4 {
822                         i2c4_xfer: i2c4-xfer {
823                                 rockchip,pins =
824                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
825                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
826                         };
827                 };
828
829                 i2c5 {
830                         i2c5_xfer: i2c5-xfer {
831                                 rockchip,pins =
832                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
833                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
834                         };
835                 };
836
837                 i2c6 {
838                         i2c6_xfer: i2c6-xfer {
839                                 rockchip,pins =
840                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
841                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
842                         };
843                 };
844
845                 i2c7 {
846                         i2c7_xfer: i2c7-xfer {
847                                 rockchip,pins =
848                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
849                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
850                         };
851                 };
852
853                 i2c8 {
854                         i2c8_xfer: i2c8-xfer {
855                                 rockchip,pins =
856                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
857                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
858                         };
859                 };
860
861                 i2s0 {
862                         i2s0_8ch_bus: i2s0-8ch-bus {
863                                 rockchip,pins =
864                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
865                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
866                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
867                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
868                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
869                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
870                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
871                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
872                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
873                         };
874                 };
875
876                 i2s1 {
877                         i2s1_2ch_bus: i2s1-2ch-bus {
878                                 rockchip,pins =
879                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
880                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
881                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
882                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
883                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
884                         };
885                 };
886
887                 gmac {
888                         rgmii_pins: rgmii-pins {
889                                 rockchip,pins =
890                                         /* mac_txclk */
891                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
892                                         /* mac_rxclk */
893                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
894                                         /* mac_mdio */
895                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
896                                         /* mac_txen */
897                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
898                                         /* mac_clk */
899                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
900                                         /* mac_rxdv */
901                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
902                                         /* mac_mdc */
903                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
904                                         /* mac_rxd1 */
905                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
906                                         /* mac_rxd0 */
907                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
908                                         /* mac_txd1 */
909                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
910                                         /* mac_txd0 */
911                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
912                                         /* mac_rxd3 */
913                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
914                                         /* mac_rxd2 */
915                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
916                                         /* mac_txd3 */
917                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
918                                         /* mac_txd2 */
919                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
920                         };
921                 };
922
923                 sdmmc {
924                         sdmmc_bus1: sdmmc-bus1 {
925                                 rockchip,pins =
926                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
927                         };
928
929                         sdmmc_bus4: sdmmc-bus4 {
930                                 rockchip,pins =
931                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
932                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
933                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
934                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
935                         };
936
937                         sdmmc_clk: sdmmc-clk {
938                                 rockchip,pins =
939                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
940                         };
941
942                         sdmmc_cmd: sdmmc-cmd {
943                                 rockchip,pins =
944                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
945                         };
946
947                         sdmmc_cd: sdmcc-cd {
948                                 rockchip,pins =
949                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
950                         };
951
952                         sdmmc_wp: sdmmc-wp {
953                                 rockchip,pins =
954                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
955                         };
956                 };
957
958                 spdif {
959                         spdif_bus: spdif-bus {
960                                 rockchip,pins =
961                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
962                         };
963                 };
964
965                 spi0 {
966                         spi0_clk: spi0-clk {
967                                 rockchip,pins =
968                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
969                         };
970                         spi0_cs0: spi0-cs0 {
971                                 rockchip,pins =
972                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
973                         };
974                         spi0_cs1: spi0-cs1 {
975                                 rockchip,pins =
976                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
977                         };
978                         spi0_tx: spi0-tx {
979                                 rockchip,pins =
980                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
981                         };
982                         spi0_rx: spi0-rx {
983                                 rockchip,pins =
984                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
985                         };
986                 };
987
988                 spi1 {
989                         spi1_clk: spi1-clk {
990                                 rockchip,pins =
991                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
992                         };
993                         spi1_cs0: spi1-cs0 {
994                                 rockchip,pins =
995                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
996                         };
997                         spi1_rx: spi1-rx {
998                                 rockchip,pins =
999                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1000                         };
1001                         spi1_tx: spi1-tx {
1002                                 rockchip,pins =
1003                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1004                         };
1005                 };
1006
1007                 spi2 {
1008                         spi2_clk: spi2-clk {
1009                                 rockchip,pins =
1010                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1011                         };
1012                         spi2_cs0: spi2-cs0 {
1013                                 rockchip,pins =
1014                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1015                         };
1016                         spi2_rx: spi2-rx {
1017                                 rockchip,pins =
1018                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1019                         };
1020                         spi2_tx: spi2-tx {
1021                                 rockchip,pins =
1022                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1023                         };
1024                 };
1025
1026                 spi3 {
1027                         spi3_clk: spi3-clk {
1028                                 rockchip,pins =
1029                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1030                         };
1031                         spi3_cs0: spi3-cs0 {
1032                                 rockchip,pins =
1033                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1034                         };
1035                         spi3_rx: spi3-rx {
1036                                 rockchip,pins =
1037                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1038                         };
1039                         spi3_tx: spi3-tx {
1040                                 rockchip,pins =
1041                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1042                         };
1043                 };
1044
1045                 spi4 {
1046                         spi4_clk: spi4-clk {
1047                                 rockchip,pins =
1048                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1049                         };
1050                         spi4_cs0: spi4-cs0 {
1051                                 rockchip,pins =
1052                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1053                         };
1054                         spi4_rx: spi4-rx {
1055                                 rockchip,pins =
1056                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1057                         };
1058                         spi4_tx: spi4-tx {
1059                                 rockchip,pins =
1060                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1061                         };
1062                 };
1063
1064                 spi5 {
1065                         spi5_clk: spi5-clk {
1066                                 rockchip,pins =
1067                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1068                         };
1069                         spi5_cs0: spi5-cs0 {
1070                                 rockchip,pins =
1071                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1072                         };
1073                         spi5_rx: spi5-rx {
1074                                 rockchip,pins =
1075                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1076                         };
1077                         spi5_tx: spi5-tx {
1078                                 rockchip,pins =
1079                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1080                         };
1081                 };
1082
1083                 uart0 {
1084                         uart0_xfer: uart0-xfer {
1085                                 rockchip,pins =
1086                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1087                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1088                         };
1089
1090                         uart0_cts: uart0-cts {
1091                                 rockchip,pins =
1092                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1093                         };
1094
1095                         uart0_rts: uart0-rts {
1096                                 rockchip,pins =
1097                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1098                         };
1099                 };
1100
1101                 uart1 {
1102                         uart1_xfer: uart1-xfer {
1103                                 rockchip,pins =
1104                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1105                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1106                         };
1107                 };
1108
1109                 uart2a {
1110                         uart2a_xfer: uart2a-xfer {
1111                                 rockchip,pins =
1112                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1113                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1114                         };
1115                 };
1116
1117                 uart2b {
1118                         uart2b_xfer: uart2b-xfer {
1119                                 rockchip,pins =
1120                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1121                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1122                         };
1123                 };
1124
1125                 uart2c {
1126                         uart2c_xfer: uart2c-xfer {
1127                                 rockchip,pins =
1128                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1129                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1130                         };
1131                 };
1132
1133                 uart3 {
1134                         uart3_xfer: uart3-xfer {
1135                                 rockchip,pins =
1136                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1137                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1138                         };
1139
1140                         uart3_cts: uart3-cts {
1141                                 rockchip,pins =
1142                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1143                         };
1144
1145                         uart3_rts: uart3-rts {
1146                                 rockchip,pins =
1147                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1148                         };
1149                 };
1150
1151                 uart4 {
1152                         uart4_xfer: uart4-xfer {
1153                                 rockchip,pins =
1154                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1155                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1156                         };
1157                 };
1158
1159                 uarthdcp {
1160                         uarthdcp_xfer: uarthdcp-xfer {
1161                                 rockchip,pins =
1162                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1163                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1164                         };
1165                 };
1166
1167                 pwm0 {
1168                         pwm0_pin: pwm0-pin {
1169                                 rockchip,pins =
1170                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1171                         };
1172
1173                         vop0_pwm_pin: vop0-pwm-pin {
1174                                 rockchip,pins =
1175                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1176                         };
1177                 };
1178
1179                 pwm1 {
1180                         pwm1_pin: pwm1-pin {
1181                                 rockchip,pins =
1182                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1183                         };
1184
1185                         vop1_pwm_pin: vop1-pwm-pin {
1186                                 rockchip,pins =
1187                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1188                         };
1189                 };
1190
1191                 pwm2 {
1192                         pwm2_pin: pwm2-pin {
1193                                 rockchip,pins =
1194                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1195                         };
1196                 };
1197
1198                 pwm3a {
1199                         pwm3a_pin: pwm3a-pin {
1200                                 rockchip,pins =
1201                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1202                         };
1203                 };
1204
1205                 pwm3b {
1206                         pwm3b_pin: pwm3b-pin {
1207                                 rockchip,pins =
1208                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1209                         };
1210                 };
1211         };
1212 };