2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/rk3399-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #define USB_CLASS_HUB 9
15 compatible = "rockchip,rk3399";
17 interrupt-parent = <&gic>;
64 compatible = "arm,cortex-a53", "arm,armv8";
66 enable-method = "psci";
67 #cooling-cells = <2>; /* min followed by max */
68 clocks = <&cru ARMCLKL>;
73 compatible = "arm,cortex-a53", "arm,armv8";
75 enable-method = "psci";
76 clocks = <&cru ARMCLKL>;
81 compatible = "arm,cortex-a53", "arm,armv8";
83 enable-method = "psci";
84 clocks = <&cru ARMCLKL>;
89 compatible = "arm,cortex-a53", "arm,armv8";
91 enable-method = "psci";
92 clocks = <&cru ARMCLKL>;
97 compatible = "arm,cortex-a72", "arm,armv8";
99 enable-method = "psci";
100 #cooling-cells = <2>; /* min followed by max */
101 clocks = <&cru ARMCLKB>;
106 compatible = "arm,cortex-a72", "arm,armv8";
108 enable-method = "psci";
109 clocks = <&cru ARMCLKB>;
114 compatible = "arm,psci-1.0";
119 compatible = "arm,armv8-timer";
120 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
121 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
122 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
123 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
127 compatible = "fixed-clock";
128 clock-frequency = <24000000>;
129 clock-output-names = "xin24m";
134 compatible = "simple-bus";
135 #address-cells = <2>;
139 dmac_bus: dma-controller@ff6d0000 {
140 compatible = "arm,pl330", "arm,primecell";
141 reg = <0x0 0xff6d0000 0x0 0x4000>;
142 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&cru ACLK_DMAC0_PERILP>;
146 clock-names = "apb_pclk";
149 dmac_peri: dma-controller@ff6e0000 {
150 compatible = "arm,pl330", "arm,primecell";
151 reg = <0x0 0xff6e0000 0x0 0x4000>;
152 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&cru ACLK_DMAC1_PERILP>;
156 clock-names = "apb_pclk";
160 sdio0: dwmmc@fe310000 {
161 compatible = "rockchip,rk3399-dw-mshc",
162 "rockchip,rk3288-dw-mshc";
163 reg = <0x0 0xfe310000 0x0 0x4000>;
164 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
165 clock-freq-min-max = <400000 150000000>;
166 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
167 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
168 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
169 fifo-depth = <0x100>;
173 sdmmc: dwmmc@fe320000 {
174 compatible = "rockchip,rk3399-dw-mshc",
175 "rockchip,rk3288-dw-mshc";
176 reg = <0x0 0xfe320000 0x0 0x4000>;
177 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
178 clock-freq-min-max = <400000 150000000>;
179 clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>,
180 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
181 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
182 pinctrl-names = "default";
183 pinctrl-0 = <&sdmmc_clk>;
184 fifo-depth = <0x100>;
188 sdhci: sdhci@fe330000 {
190 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
191 reg = <0x0 0xfe330000 0x0 0x10000>;
192 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
193 assigned-clocks = <&cru SCLK_EMMC>;
194 assigned-clock-rates = <200000000>;
195 max-frequency = <200000000>;
196 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
197 clock-names = "clk_xin", "clk_ahb";
199 phy-names = "phy_arasan";
203 usb_host0_ehci: usb@fe380000 {
204 compatible = "generic-ehci";
205 reg = <0x0 0xfe380000 0x0 0x20000>;
206 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
208 clock-names = "hclk_host0", "hclk_host0_arb";
212 usb_host0_ohci: usb@fe3a0000 {
213 compatible = "generic-ohci";
214 reg = <0x0 0xfe3a0000 0x0 0x20000>;
215 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
217 clock-names = "hclk_host0", "hclk_host0_arb";
221 usb_host1_ehci: usb@fe3c0000 {
222 compatible = "generic-ehci";
223 reg = <0x0 0xfe3c0000 0x0 0x20000>;
224 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
226 clock-names = "hclk_host1", "hclk_host1_arb";
230 usb_host1_ohci: usb@fe3e0000 {
231 compatible = "generic-ohci";
232 reg = <0x0 0xfe3e0000 0x0 0x20000>;
233 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
235 clock-names = "hclk_host1", "hclk_host1_arb";
239 dwc3_typec0: usb@fe800000 {
240 compatible = "rockchip,rk3399-xhci";
241 reg = <0x0 0xfe800000 0x0 0x100000>;
243 snps,dis-enblslpm-quirk;
244 snps,phyif-utmi-bits = <16>;
245 snps,dis-u2-freeclk-exists-quirk;
246 snps,dis-u2-susphy-quirk;
248 #address-cells = <2>;
251 compatible = "usb-hub";
252 usb,device-class = <USB_CLASS_HUB>;
255 compatible = "rockchip,rk3399-usb3-phy";
256 reg = <0x0 0xff7c0000 0x0 0x40000>;
260 dwc3_typec1: usb@fe900000 {
261 compatible = "rockchip,rk3399-xhci";
262 reg = <0x0 0xfe900000 0x0 0x100000>;
264 snps,dis-enblslpm-quirk;
265 snps,phyif-utmi-bits = <16>;
266 snps,dis-u2-freeclk-exists-quirk;
267 snps,dis-u2-susphy-quirk;
269 #address-cells = <2>;
272 compatible = "usb-hub";
273 usb,device-class = <USB_CLASS_HUB>;
276 compatible = "rockchip,rk3399-usb3-phy";
277 reg = <0x0 0xff800000 0x0 0x40000>;
281 gic: interrupt-controller@fee00000 {
282 compatible = "arm,gic-v3";
283 #interrupt-cells = <3>;
284 #address-cells = <2>;
287 interrupt-controller;
289 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
290 <0x0 0xfef00000 0 0xc0000>, /* GICR */
291 <0x0 0xfff00000 0 0x10000>, /* GICC */
292 <0x0 0xfff10000 0 0x10000>, /* GICH */
293 <0x0 0xfff20000 0 0x10000>; /* GICV */
294 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
295 its: interrupt-controller@fee20000 {
296 compatible = "arm,gic-v3-its";
298 reg = <0x0 0xfee20000 0x0 0x20000>;
302 uart0: serial@ff180000 {
303 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
304 reg = <0x0 0xff180000 0x0 0x100>;
305 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
306 clock-names = "baudclk", "apb_pclk";
307 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&uart0_xfer>;
315 uart1: serial@ff190000 {
316 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
317 reg = <0x0 0xff190000 0x0 0x100>;
318 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
319 clock-names = "baudclk", "apb_pclk";
320 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&uart1_xfer>;
328 uart2: serial@ff1a0000 {
329 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
330 reg = <0x0 0xff1a0000 0x0 0x100>;
331 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
332 clock-names = "baudclk", "apb_pclk";
333 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
334 clock-frequency = <24000000>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart2c_xfer>;
342 uart3: serial@ff1b0000 {
343 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
344 reg = <0x0 0xff1b0000 0x0 0x100>;
345 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
346 clock-names = "baudclk", "apb_pclk";
347 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&uart3_xfer>;
356 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
357 reg = <0x0 0xff1c0000 0x0 0x1000>;
358 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
359 clock-names = "spiclk", "apb_pclk";
360 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
363 #address-cells = <1>;
369 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
370 reg = <0x0 0xff1d0000 0x0 0x1000>;
371 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
372 clock-names = "spiclk", "apb_pclk";
373 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
376 #address-cells = <1>;
382 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
383 reg = <0x0 0xff1e0000 0x0 0x1000>;
384 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
385 clock-names = "spiclk", "apb_pclk";
386 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
389 #address-cells = <1>;
395 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
396 reg = <0x0 0xff1f0000 0x0 0x1000>;
397 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
398 clock-names = "spiclk", "apb_pclk";
399 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
402 #address-cells = <1>;
408 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
409 reg = <0x0 0xff200000 0x0 0x1000>;
410 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
411 clock-names = "spiclk", "apb_pclk";
412 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
415 #address-cells = <1>;
420 pmugrf: syscon@ff320000 {
422 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
423 reg = <0x0 0xff320000 0x0 0x1000>;
424 #address-cells = <1>;
427 pmu_io_domains: io-domains {
428 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
433 pmusgrf: syscon@ff330000 {
435 compatible = "rockchip,rk3399-pmusgrf", "syscon";
436 reg = <0x0 0xff330000 0x0 0xe3d4>;
440 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
441 reg = <0x0 0xff350000 0x0 0x1000>;
442 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
443 clock-names = "spiclk", "apb_pclk";
444 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
447 #address-cells = <1>;
452 uart4: serial@ff370000 {
453 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
454 reg = <0x0 0xff370000 0x0 0x100>;
455 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
456 clock-names = "baudclk", "apb_pclk";
457 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&uart4_xfer>;
466 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
467 reg = <0x0 0xff420000 0x0 0x10>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pwm0_pin>;
471 clocks = <&pmucru PCLK_RKPWM_PMU>;
477 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
478 reg = <0x0 0xff420010 0x0 0x10>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&pwm1_pin>;
482 clocks = <&pmucru PCLK_RKPWM_PMU>;
488 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
489 reg = <0x0 0xff420020 0x0 0x10>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&pwm2_pin>;
493 clocks = <&pmucru PCLK_RKPWM_PMU>;
499 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
500 reg = <0x0 0xff420030 0x0 0x10>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&pwm3a_pin>;
504 clocks = <&pmucru PCLK_RKPWM_PMU>;
509 cic: syscon@ff620000 {
511 compatible = "rockchip,rk3399-cic", "syscon";
512 reg = <0x0 0xff620000 0x0 0x100>;
516 reg = <0x00 0xff630000 0x00 0x4000>;
517 compatible = "rockchip,rk3399-dfi";
518 rockchip,pmu = <&pmugrf>;
519 clocks = <&cru PCLK_DDR_MON>;
520 clock-names = "pclk_ddr_mon";
526 compatible = "rockchip,rk3399-dmc";
527 devfreq-events = <&dfi>;
528 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
529 clocks = <&cru SCLK_DDRCLK>;
530 clock-names = "dmc_clk";
531 reg = <0x0 0xffa80000 0x0 0x0800
532 0x0 0xffa80800 0x0 0x1800
533 0x0 0xffa82000 0x0 0x2000
534 0x0 0xffa84000 0x0 0x1000
535 0x0 0xffa88000 0x0 0x0800
536 0x0 0xffa88800 0x0 0x1800
537 0x0 0xffa8a000 0x0 0x2000
538 0x0 0xffa8c000 0x0 0x1000>;
541 pmucru: pmu-clock-controller@ff750000 {
543 compatible = "rockchip,rk3399-pmucru";
544 reg = <0x0 0xff750000 0x0 0x1000>;
547 assigned-clocks = <&pmucru PLL_PPLL>;
548 assigned-clock-rates = <676000000>;
551 cru: clock-controller@ff760000 {
553 compatible = "rockchip,rk3399-cru";
554 reg = <0x0 0xff760000 0x0 0x1000>;
558 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
560 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
562 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
564 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
565 assigned-clock-rates =
566 <594000000>, <800000000>,
568 <150000000>, <75000000>,
570 <100000000>, <100000000>,
572 <100000000>, <50000000>;
575 grf: syscon@ff770000 {
577 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
578 reg = <0x0 0xff770000 0x0 0x10000>;
579 #address-cells = <1>;
582 io_domains: io-domains {
583 compatible = "rockchip,rk3399-io-voltage-domain";
588 compatible = "rockchip,rk3399-emmc-phy";
596 compatible = "snps,dw-wdt";
597 reg = <0x0 0xff840000 0x0 0x100>;
598 clocks = <&cru PCLK_WDT>;
599 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
603 compatible = "rockchip,rk3399-gmac";
604 reg = <0x0 0xfe300000 0x0 0x10000>;
605 rockchip,grf = <&grf>;
606 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
607 interrupt-names = "macirq";
608 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
609 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
610 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
612 clock-names = "stmmaceth", "mac_clk_rx",
613 "mac_clk_tx", "clk_mac_ref",
614 "clk_mac_refout", "aclk_mac",
616 resets = <&cru SRST_A_GMAC>;
617 reset-names = "stmmaceth";
621 spdif: spdif@ff870000 {
622 compatible = "rockchip,rk3399-spdif";
623 reg = <0x0 0xff870000 0x0 0x1000>;
624 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
625 dmas = <&dmac_bus 7>;
627 clock-names = "mclk", "hclk";
628 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
629 pinctrl-names = "default";
630 pinctrl-0 = <&spdif_bus>;
635 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
636 reg = <0x0 0xff880000 0x0 0x1000>;
637 rockchip,grf = <&grf>;
638 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
639 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
640 dma-names = "tx", "rx";
641 clock-names = "i2s_clk", "i2s_hclk";
642 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&i2s0_8ch_bus>;
649 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
650 reg = <0x0 0xff890000 0x0 0x1000>;
651 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
652 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
653 dma-names = "tx", "rx";
654 clock-names = "i2s_clk", "i2s_hclk";
655 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
656 pinctrl-names = "default";
657 pinctrl-0 = <&i2s1_2ch_bus>;
662 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
663 reg = <0x0 0xff8a0000 0x0 0x1000>;
664 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
665 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
666 dma-names = "tx", "rx";
667 clock-names = "i2s_clk", "i2s_hclk";
668 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
673 compatible = "rockchip,rk3399-i2c";
674 reg = <0x0 0xff3c0000 0x0 0x1000>;
675 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
676 assigned-clock-rates = <200000000>;
677 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
678 clock-names = "i2c", "pclk";
679 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
680 pinctrl-names = "default";
681 pinctrl-0 = <&i2c0_xfer>;
682 #address-cells = <1>;
689 compatible = "rockchip,rk3399-pinctrl";
690 rockchip,grf = <&grf>;
691 rockchip,pmu = <&pmugrf>;
692 #address-cells = <2>;
696 gpio0: gpio0@ff720000 {
697 compatible = "rockchip,gpio-bank";
698 reg = <0x0 0xff720000 0x0 0x100>;
699 clocks = <&pmucru PCLK_GPIO0_PMU>;
700 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
705 interrupt-controller;
706 #interrupt-cells = <0x2>;
709 gpio1: gpio1@ff730000 {
710 compatible = "rockchip,gpio-bank";
711 reg = <0x0 0xff730000 0x0 0x100>;
712 clocks = <&pmucru PCLK_GPIO1_PMU>;
713 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
718 interrupt-controller;
719 #interrupt-cells = <0x2>;
722 gpio2: gpio2@ff780000 {
723 compatible = "rockchip,gpio-bank";
724 reg = <0x0 0xff780000 0x0 0x100>;
725 clocks = <&cru PCLK_GPIO2>;
726 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
731 interrupt-controller;
732 #interrupt-cells = <0x2>;
735 gpio3: gpio3@ff788000 {
736 compatible = "rockchip,gpio-bank";
737 reg = <0x0 0xff788000 0x0 0x100>;
738 clocks = <&cru PCLK_GPIO3>;
739 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
744 interrupt-controller;
745 #interrupt-cells = <0x2>;
748 gpio4: gpio4@ff790000 {
749 compatible = "rockchip,gpio-bank";
750 reg = <0x0 0xff790000 0x0 0x100>;
751 clocks = <&cru PCLK_GPIO4>;
752 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
757 interrupt-controller;
758 #interrupt-cells = <0x2>;
761 pcfg_pull_up: pcfg-pull-up {
765 pcfg_pull_down: pcfg-pull-down {
769 pcfg_pull_none: pcfg-pull-none {
773 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
775 drive-strength = <12>;
778 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
780 drive-strength = <8>;
783 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
785 drive-strength = <4>;
788 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
790 drive-strength = <2>;
793 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
795 drive-strength = <12>;
798 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
800 drive-strength = <13>;
804 i2c0_xfer: i2c0-xfer {
806 <1 15 RK_FUNC_2 &pcfg_pull_none>,
807 <1 16 RK_FUNC_2 &pcfg_pull_none>;
812 i2c1_xfer: i2c1-xfer {
814 <4 2 RK_FUNC_1 &pcfg_pull_none>,
815 <4 1 RK_FUNC_1 &pcfg_pull_none>;
820 i2c2_xfer: i2c2-xfer {
822 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
823 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
828 i2c3_xfer: i2c3-xfer {
830 <4 17 RK_FUNC_1 &pcfg_pull_none>,
831 <4 16 RK_FUNC_1 &pcfg_pull_none>;
836 i2c4_xfer: i2c4-xfer {
838 <1 12 RK_FUNC_1 &pcfg_pull_none>,
839 <1 11 RK_FUNC_1 &pcfg_pull_none>;
844 i2c5_xfer: i2c5-xfer {
846 <3 11 RK_FUNC_2 &pcfg_pull_none>,
847 <3 10 RK_FUNC_2 &pcfg_pull_none>;
852 i2c6_xfer: i2c6-xfer {
854 <2 10 RK_FUNC_2 &pcfg_pull_none>,
855 <2 9 RK_FUNC_2 &pcfg_pull_none>;
860 i2c7_xfer: i2c7-xfer {
862 <2 8 RK_FUNC_2 &pcfg_pull_none>,
863 <2 7 RK_FUNC_2 &pcfg_pull_none>;
868 i2c8_xfer: i2c8-xfer {
870 <1 21 RK_FUNC_1 &pcfg_pull_none>,
871 <1 20 RK_FUNC_1 &pcfg_pull_none>;
876 i2s0_8ch_bus: i2s0-8ch-bus {
878 <3 24 RK_FUNC_1 &pcfg_pull_none>,
879 <3 25 RK_FUNC_1 &pcfg_pull_none>,
880 <3 26 RK_FUNC_1 &pcfg_pull_none>,
881 <3 27 RK_FUNC_1 &pcfg_pull_none>,
882 <3 28 RK_FUNC_1 &pcfg_pull_none>,
883 <3 29 RK_FUNC_1 &pcfg_pull_none>,
884 <3 30 RK_FUNC_1 &pcfg_pull_none>,
885 <3 31 RK_FUNC_1 &pcfg_pull_none>,
886 <4 0 RK_FUNC_1 &pcfg_pull_none>;
891 i2s1_2ch_bus: i2s1-2ch-bus {
893 <4 3 RK_FUNC_1 &pcfg_pull_none>,
894 <4 4 RK_FUNC_1 &pcfg_pull_none>,
895 <4 5 RK_FUNC_1 &pcfg_pull_none>,
896 <4 6 RK_FUNC_1 &pcfg_pull_none>,
897 <4 7 RK_FUNC_1 &pcfg_pull_none>;
902 rgmii_pins: rgmii-pins {
905 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
907 <3 14 RK_FUNC_1 &pcfg_pull_none>,
909 <3 13 RK_FUNC_1 &pcfg_pull_none>,
911 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
913 <3 11 RK_FUNC_1 &pcfg_pull_none>,
915 <3 9 RK_FUNC_1 &pcfg_pull_none>,
917 <3 8 RK_FUNC_1 &pcfg_pull_none>,
919 <3 7 RK_FUNC_1 &pcfg_pull_none>,
921 <3 6 RK_FUNC_1 &pcfg_pull_none>,
923 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
925 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
927 <3 3 RK_FUNC_1 &pcfg_pull_none>,
929 <3 2 RK_FUNC_1 &pcfg_pull_none>,
931 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
933 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
938 sdmmc_bus1: sdmmc-bus1 {
940 <4 8 RK_FUNC_1 &pcfg_pull_up>;
943 sdmmc_bus4: sdmmc-bus4 {
945 <4 8 RK_FUNC_1 &pcfg_pull_up>,
946 <4 9 RK_FUNC_1 &pcfg_pull_up>,
947 <4 10 RK_FUNC_1 &pcfg_pull_up>,
948 <4 11 RK_FUNC_1 &pcfg_pull_up>;
951 sdmmc_clk: sdmmc-clk {
953 <4 12 RK_FUNC_1 &pcfg_pull_none>;
956 sdmmc_cmd: sdmmc-cmd {
958 <4 13 RK_FUNC_1 &pcfg_pull_up>;
963 <0 7 RK_FUNC_1 &pcfg_pull_up>;
968 <0 8 RK_FUNC_1 &pcfg_pull_up>;
973 spdif_bus: spdif-bus {
975 <4 21 RK_FUNC_1 &pcfg_pull_none>;
982 <3 6 RK_FUNC_2 &pcfg_pull_up>;
986 <3 7 RK_FUNC_2 &pcfg_pull_up>;
990 <3 8 RK_FUNC_2 &pcfg_pull_up>;
994 <3 5 RK_FUNC_2 &pcfg_pull_up>;
998 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1003 spi1_clk: spi1-clk {
1005 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1007 spi1_cs0: spi1-cs0 {
1009 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1013 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1017 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1022 spi2_clk: spi2-clk {
1024 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1026 spi2_cs0: spi2-cs0 {
1028 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1032 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1036 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1041 spi3_clk: spi3-clk {
1043 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1045 spi3_cs0: spi3-cs0 {
1047 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1051 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1055 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1060 spi4_clk: spi4-clk {
1062 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1064 spi4_cs0: spi4-cs0 {
1066 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1070 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1074 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1079 spi5_clk: spi5-clk {
1081 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1083 spi5_cs0: spi5-cs0 {
1085 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1089 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1093 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1098 uart0_xfer: uart0-xfer {
1100 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1101 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1104 uart0_cts: uart0-cts {
1106 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1109 uart0_rts: uart0-rts {
1111 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1116 uart1_xfer: uart1-xfer {
1118 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1119 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1124 uart2a_xfer: uart2a-xfer {
1126 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1127 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1132 uart2b_xfer: uart2b-xfer {
1134 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1135 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1140 uart2c_xfer: uart2c-xfer {
1142 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1143 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1148 uart3_xfer: uart3-xfer {
1150 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1151 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1154 uart3_cts: uart3-cts {
1156 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1159 uart3_rts: uart3-rts {
1161 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1166 uart4_xfer: uart4-xfer {
1168 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1169 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1174 uarthdcp_xfer: uarthdcp-xfer {
1176 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1177 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1182 pwm0_pin: pwm0-pin {
1184 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1187 vop0_pwm_pin: vop0-pwm-pin {
1189 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1194 pwm1_pin: pwm1-pin {
1196 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1199 vop1_pwm_pin: vop1-pwm-pin {
1201 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1206 pwm2_pin: pwm2-pin {
1208 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1213 pwm3a_pin: pwm3a-pin {
1215 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1220 pwm3b_pin: pwm3b-pin {
1222 <1 14 RK_FUNC_1 &pcfg_pull_none>;