2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/rk3399-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #define USB_CLASS_HUB 9
15 compatible = "rockchip,rk3399";
17 interrupt-parent = <&gic>;
61 compatible = "arm,cortex-a53", "arm,armv8";
63 enable-method = "psci";
64 #cooling-cells = <2>; /* min followed by max */
65 clocks = <&cru ARMCLKL>;
70 compatible = "arm,cortex-a53", "arm,armv8";
72 enable-method = "psci";
73 clocks = <&cru ARMCLKL>;
78 compatible = "arm,cortex-a53", "arm,armv8";
80 enable-method = "psci";
81 clocks = <&cru ARMCLKL>;
86 compatible = "arm,cortex-a53", "arm,armv8";
88 enable-method = "psci";
89 clocks = <&cru ARMCLKL>;
94 compatible = "arm,cortex-a72", "arm,armv8";
96 enable-method = "psci";
97 #cooling-cells = <2>; /* min followed by max */
98 clocks = <&cru ARMCLKB>;
103 compatible = "arm,cortex-a72", "arm,armv8";
105 enable-method = "psci";
106 clocks = <&cru ARMCLKB>;
111 compatible = "arm,psci-1.0";
116 compatible = "arm,armv8-timer";
117 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
118 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
119 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
120 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
124 compatible = "fixed-clock";
125 clock-frequency = <24000000>;
126 clock-output-names = "xin24m";
131 compatible = "simple-bus";
132 #address-cells = <2>;
136 dmac_bus: dma-controller@ff6d0000 {
137 compatible = "arm,pl330", "arm,primecell";
138 reg = <0x0 0xff6d0000 0x0 0x4000>;
139 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&cru ACLK_DMAC0_PERILP>;
143 clock-names = "apb_pclk";
146 dmac_peri: dma-controller@ff6e0000 {
147 compatible = "arm,pl330", "arm,primecell";
148 reg = <0x0 0xff6e0000 0x0 0x4000>;
149 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&cru ACLK_DMAC1_PERILP>;
153 clock-names = "apb_pclk";
157 sdio0: dwmmc@fe310000 {
158 compatible = "rockchip,rk3399-dw-mshc",
159 "rockchip,rk3288-dw-mshc";
160 reg = <0x0 0xfe310000 0x0 0x4000>;
161 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
162 clock-freq-min-max = <400000 150000000>;
163 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
164 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
165 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
166 fifo-depth = <0x100>;
170 sdmmc: dwmmc@fe320000 {
171 compatible = "rockchip,rk3399-dw-mshc",
172 "rockchip,rk3288-dw-mshc";
173 reg = <0x0 0xfe320000 0x0 0x4000>;
174 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
175 clock-freq-min-max = <400000 150000000>;
176 clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>,
177 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
178 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
179 pinctrl-names = "default";
180 pinctrl-0 = <&sdmmc_clk>;
181 fifo-depth = <0x100>;
185 sdhci: sdhci@fe330000 {
186 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
187 reg = <0x0 0xfe330000 0x0 0x10000>;
188 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
189 assigned-clocks = <&cru SCLK_EMMC>;
190 assigned-clock-rates = <200000000>;
191 max-frequency = <200000000>;
192 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
193 clock-names = "clk_xin", "clk_ahb";
195 phy-names = "phy_arasan";
199 usb_host0_ehci: usb@fe380000 {
200 compatible = "generic-ehci";
201 reg = <0x0 0xfe380000 0x0 0x20000>;
202 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
204 clock-names = "hclk_host0", "hclk_host0_arb";
208 usb_host0_ohci: usb@fe3a0000 {
209 compatible = "generic-ohci";
210 reg = <0x0 0xfe3a0000 0x0 0x20000>;
211 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
213 clock-names = "hclk_host0", "hclk_host0_arb";
217 usb_host1_ehci: usb@fe3c0000 {
218 compatible = "generic-ehci";
219 reg = <0x0 0xfe3c0000 0x0 0x20000>;
220 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
222 clock-names = "hclk_host1", "hclk_host1_arb";
226 usb_host1_ohci: usb@fe3e0000 {
227 compatible = "generic-ohci";
228 reg = <0x0 0xfe3e0000 0x0 0x20000>;
229 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
231 clock-names = "hclk_host1", "hclk_host1_arb";
235 dwc3_typec0: usb@fe800000 {
236 compatible = "rockchip,rk3399-xhci";
237 reg = <0x0 0xfe800000 0x0 0x100000>;
239 rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
240 snps,dis-enblslpm-quirk;
241 snps,phyif-utmi-bits = <16>;
242 snps,dis-u2-freeclk-exists-quirk;
243 snps,dis-u2-susphy-quirk;
245 #address-cells = <2>;
248 compatible = "usb-hub";
249 usb,device-class = <USB_CLASS_HUB>;
252 compatible = "rockchip,rk3399-usb3-phy";
253 reg = <0x0 0xff7c0000 0x0 0x40000>;
257 dwc3_typec1: usb@fe900000 {
258 compatible = "rockchip,rk3399-xhci";
259 reg = <0x0 0xfe900000 0x0 0x100000>;
261 rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
262 snps,dis-enblslpm-quirk;
263 snps,phyif-utmi-bits = <16>;
264 snps,dis-u2-freeclk-exists-quirk;
265 snps,dis-u2-susphy-quirk;
267 #address-cells = <2>;
270 compatible = "usb-hub";
271 usb,device-class = <USB_CLASS_HUB>;
274 compatible = "rockchip,rk3399-usb3-phy";
275 reg = <0x0 0xff800000 0x0 0x40000>;
279 gic: interrupt-controller@fee00000 {
280 compatible = "arm,gic-v3";
281 #interrupt-cells = <3>;
282 #address-cells = <2>;
285 interrupt-controller;
287 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
288 <0x0 0xfef00000 0 0xc0000>, /* GICR */
289 <0x0 0xfff00000 0 0x10000>, /* GICC */
290 <0x0 0xfff10000 0 0x10000>, /* GICH */
291 <0x0 0xfff20000 0 0x10000>; /* GICV */
292 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
293 its: interrupt-controller@fee20000 {
294 compatible = "arm,gic-v3-its";
296 reg = <0x0 0xfee20000 0x0 0x20000>;
300 uart0: serial@ff180000 {
301 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
302 reg = <0x0 0xff180000 0x0 0x100>;
303 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
304 clock-names = "baudclk", "apb_pclk";
305 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
308 pinctrl-names = "default";
309 pinctrl-0 = <&uart0_xfer>;
313 uart1: serial@ff190000 {
314 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
315 reg = <0x0 0xff190000 0x0 0x100>;
316 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
317 clock-names = "baudclk", "apb_pclk";
318 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&uart1_xfer>;
326 uart2: serial@ff1a0000 {
327 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
328 reg = <0x0 0xff1a0000 0x0 0x100>;
329 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
330 clock-names = "baudclk", "apb_pclk";
331 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
332 clock-frequency = <24000000>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&uart2c_xfer>;
340 uart3: serial@ff1b0000 {
341 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
342 reg = <0x0 0xff1b0000 0x0 0x100>;
343 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
344 clock-names = "baudclk", "apb_pclk";
345 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&uart3_xfer>;
354 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
355 reg = <0x0 0xff1c0000 0x0 0x1000>;
356 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
357 clock-names = "spiclk", "apb_pclk";
358 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
361 #address-cells = <1>;
367 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
368 reg = <0x0 0xff1d0000 0x0 0x1000>;
369 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
370 clock-names = "spiclk", "apb_pclk";
371 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
374 #address-cells = <1>;
380 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
381 reg = <0x0 0xff1e0000 0x0 0x1000>;
382 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
383 clock-names = "spiclk", "apb_pclk";
384 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
387 #address-cells = <1>;
393 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
394 reg = <0x0 0xff1f0000 0x0 0x1000>;
395 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
396 clock-names = "spiclk", "apb_pclk";
397 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
400 #address-cells = <1>;
406 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
407 reg = <0x0 0xff200000 0x0 0x1000>;
408 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
409 clock-names = "spiclk", "apb_pclk";
410 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
413 #address-cells = <1>;
418 pmugrf: syscon@ff320000 {
419 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
420 reg = <0x0 0xff320000 0x0 0x1000>;
421 #address-cells = <1>;
424 pmu_io_domains: io-domains {
425 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
431 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
432 reg = <0x0 0xff350000 0x0 0x1000>;
433 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
434 clock-names = "spiclk", "apb_pclk";
435 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
438 #address-cells = <1>;
443 uart4: serial@ff370000 {
444 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
445 reg = <0x0 0xff370000 0x0 0x100>;
446 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
447 clock-names = "baudclk", "apb_pclk";
448 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&uart4_xfer>;
457 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
458 reg = <0x0 0xff420000 0x0 0x10>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&pwm0_pin>;
462 clocks = <&pmucru PCLK_RKPWM_PMU>;
468 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
469 reg = <0x0 0xff420010 0x0 0x10>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&pwm1_pin>;
473 clocks = <&pmucru PCLK_RKPWM_PMU>;
479 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
480 reg = <0x0 0xff420020 0x0 0x10>;
482 pinctrl-names = "default";
483 pinctrl-0 = <&pwm2_pin>;
484 clocks = <&pmucru PCLK_RKPWM_PMU>;
490 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
491 reg = <0x0 0xff420030 0x0 0x10>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&pwm3a_pin>;
495 clocks = <&pmucru PCLK_RKPWM_PMU>;
500 pmucru: pmu-clock-controller@ff750000 {
501 compatible = "rockchip,rk3399-pmucru";
502 reg = <0x0 0xff750000 0x0 0x1000>;
505 assigned-clocks = <&pmucru PLL_PPLL>;
506 assigned-clock-rates = <676000000>;
509 cru: clock-controller@ff760000 {
510 compatible = "rockchip,rk3399-cru";
511 reg = <0x0 0xff760000 0x0 0x1000>;
515 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
517 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
519 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
521 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
522 assigned-clock-rates =
523 <594000000>, <800000000>,
525 <150000000>, <75000000>,
527 <100000000>, <100000000>,
529 <100000000>, <50000000>;
532 grf: syscon@ff770000 {
533 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
534 reg = <0x0 0xff770000 0x0 0x10000>;
535 #address-cells = <1>;
538 io_domains: io-domains {
539 compatible = "rockchip,rk3399-io-voltage-domain";
544 compatible = "rockchip,rk3399-emmc-phy";
552 compatible = "snps,dw-wdt";
553 reg = <0x0 0xff840000 0x0 0x100>;
554 clocks = <&cru PCLK_WDT>;
555 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
558 spdif: spdif@ff870000 {
559 compatible = "rockchip,rk3399-spdif";
560 reg = <0x0 0xff870000 0x0 0x1000>;
561 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
562 dmas = <&dmac_bus 7>;
564 clock-names = "mclk", "hclk";
565 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&spdif_bus>;
572 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
573 reg = <0x0 0xff880000 0x0 0x1000>;
574 rockchip,grf = <&grf>;
575 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
576 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
577 dma-names = "tx", "rx";
578 clock-names = "i2s_clk", "i2s_hclk";
579 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
580 pinctrl-names = "default";
581 pinctrl-0 = <&i2s0_8ch_bus>;
586 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
587 reg = <0x0 0xff890000 0x0 0x1000>;
588 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
589 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
590 dma-names = "tx", "rx";
591 clock-names = "i2s_clk", "i2s_hclk";
592 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&i2s1_2ch_bus>;
599 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
600 reg = <0x0 0xff8a0000 0x0 0x1000>;
601 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
602 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
603 dma-names = "tx", "rx";
604 clock-names = "i2s_clk", "i2s_hclk";
605 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
610 compatible = "rockchip,rk3399-pinctrl";
611 rockchip,grf = <&grf>;
612 rockchip,pmu = <&pmugrf>;
613 #address-cells = <2>;
617 gpio0: gpio0@ff720000 {
618 compatible = "rockchip,gpio-bank";
619 reg = <0x0 0xff720000 0x0 0x100>;
620 clocks = <&pmucru PCLK_GPIO0_PMU>;
621 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
626 interrupt-controller;
627 #interrupt-cells = <0x2>;
630 gpio1: gpio1@ff730000 {
631 compatible = "rockchip,gpio-bank";
632 reg = <0x0 0xff730000 0x0 0x100>;
633 clocks = <&pmucru PCLK_GPIO1_PMU>;
634 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
639 interrupt-controller;
640 #interrupt-cells = <0x2>;
643 gpio2: gpio2@ff780000 {
644 compatible = "rockchip,gpio-bank";
645 reg = <0x0 0xff780000 0x0 0x100>;
646 clocks = <&cru PCLK_GPIO2>;
647 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
652 interrupt-controller;
653 #interrupt-cells = <0x2>;
656 gpio3: gpio3@ff788000 {
657 compatible = "rockchip,gpio-bank";
658 reg = <0x0 0xff788000 0x0 0x100>;
659 clocks = <&cru PCLK_GPIO3>;
660 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
665 interrupt-controller;
666 #interrupt-cells = <0x2>;
669 gpio4: gpio4@ff790000 {
670 compatible = "rockchip,gpio-bank";
671 reg = <0x0 0xff790000 0x0 0x100>;
672 clocks = <&cru PCLK_GPIO4>;
673 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
678 interrupt-controller;
679 #interrupt-cells = <0x2>;
682 pcfg_pull_up: pcfg-pull-up {
686 pcfg_pull_down: pcfg-pull-down {
690 pcfg_pull_none: pcfg-pull-none {
694 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
696 drive-strength = <12>;
699 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
701 drive-strength = <8>;
704 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
706 drive-strength = <4>;
709 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
711 drive-strength = <2>;
714 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
716 drive-strength = <12>;
719 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
721 drive-strength = <13>;
725 i2c0_xfer: i2c0-xfer {
727 <1 15 RK_FUNC_2 &pcfg_pull_none>,
728 <1 16 RK_FUNC_2 &pcfg_pull_none>;
733 i2c1_xfer: i2c1-xfer {
735 <4 2 RK_FUNC_1 &pcfg_pull_none>,
736 <4 1 RK_FUNC_1 &pcfg_pull_none>;
741 i2c2_xfer: i2c2-xfer {
743 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
744 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
749 i2c3_xfer: i2c3-xfer {
751 <4 17 RK_FUNC_1 &pcfg_pull_none>,
752 <4 16 RK_FUNC_1 &pcfg_pull_none>;
757 i2c4_xfer: i2c4-xfer {
759 <1 12 RK_FUNC_1 &pcfg_pull_none>,
760 <1 11 RK_FUNC_1 &pcfg_pull_none>;
765 i2c5_xfer: i2c5-xfer {
767 <3 11 RK_FUNC_2 &pcfg_pull_none>,
768 <3 10 RK_FUNC_2 &pcfg_pull_none>;
773 i2c6_xfer: i2c6-xfer {
775 <2 10 RK_FUNC_2 &pcfg_pull_none>,
776 <2 9 RK_FUNC_2 &pcfg_pull_none>;
781 i2c7_xfer: i2c7-xfer {
783 <2 8 RK_FUNC_2 &pcfg_pull_none>,
784 <2 7 RK_FUNC_2 &pcfg_pull_none>;
789 i2c8_xfer: i2c8-xfer {
791 <1 21 RK_FUNC_1 &pcfg_pull_none>,
792 <1 20 RK_FUNC_1 &pcfg_pull_none>;
797 i2s0_8ch_bus: i2s0-8ch-bus {
799 <3 24 RK_FUNC_1 &pcfg_pull_none>,
800 <3 25 RK_FUNC_1 &pcfg_pull_none>,
801 <3 26 RK_FUNC_1 &pcfg_pull_none>,
802 <3 27 RK_FUNC_1 &pcfg_pull_none>,
803 <3 28 RK_FUNC_1 &pcfg_pull_none>,
804 <3 29 RK_FUNC_1 &pcfg_pull_none>,
805 <3 30 RK_FUNC_1 &pcfg_pull_none>,
806 <3 31 RK_FUNC_1 &pcfg_pull_none>,
807 <4 0 RK_FUNC_1 &pcfg_pull_none>;
812 i2s1_2ch_bus: i2s1-2ch-bus {
814 <4 3 RK_FUNC_1 &pcfg_pull_none>,
815 <4 4 RK_FUNC_1 &pcfg_pull_none>,
816 <4 5 RK_FUNC_1 &pcfg_pull_none>,
817 <4 6 RK_FUNC_1 &pcfg_pull_none>,
818 <4 7 RK_FUNC_1 &pcfg_pull_none>;
823 sdmmc_bus1: sdmmc-bus1 {
825 <4 8 RK_FUNC_1 &pcfg_pull_up>;
828 sdmmc_bus4: sdmmc-bus4 {
830 <4 8 RK_FUNC_1 &pcfg_pull_up>,
831 <4 9 RK_FUNC_1 &pcfg_pull_up>,
832 <4 10 RK_FUNC_1 &pcfg_pull_up>,
833 <4 11 RK_FUNC_1 &pcfg_pull_up>;
836 sdmmc_clk: sdmmc-clk {
838 <4 12 RK_FUNC_1 &pcfg_pull_none>;
841 sdmmc_cmd: sdmmc-cmd {
843 <4 13 RK_FUNC_1 &pcfg_pull_up>;
848 <0 7 RK_FUNC_1 &pcfg_pull_up>;
853 <0 8 RK_FUNC_1 &pcfg_pull_up>;
858 spdif_bus: spdif-bus {
860 <4 21 RK_FUNC_1 &pcfg_pull_none>;
867 <3 6 RK_FUNC_2 &pcfg_pull_up>;
871 <3 7 RK_FUNC_2 &pcfg_pull_up>;
875 <3 8 RK_FUNC_2 &pcfg_pull_up>;
879 <3 5 RK_FUNC_2 &pcfg_pull_up>;
883 <3 4 RK_FUNC_2 &pcfg_pull_up>;
890 <1 9 RK_FUNC_2 &pcfg_pull_up>;
894 <1 10 RK_FUNC_2 &pcfg_pull_up>;
898 <1 7 RK_FUNC_2 &pcfg_pull_up>;
902 <1 8 RK_FUNC_2 &pcfg_pull_up>;
909 <2 11 RK_FUNC_1 &pcfg_pull_up>;
913 <2 12 RK_FUNC_1 &pcfg_pull_up>;
917 <2 9 RK_FUNC_1 &pcfg_pull_up>;
921 <2 10 RK_FUNC_1 &pcfg_pull_up>;
928 <1 17 RK_FUNC_1 &pcfg_pull_up>;
932 <1 18 RK_FUNC_1 &pcfg_pull_up>;
936 <1 15 RK_FUNC_1 &pcfg_pull_up>;
940 <1 16 RK_FUNC_1 &pcfg_pull_up>;
947 <3 2 RK_FUNC_2 &pcfg_pull_up>;
951 <3 3 RK_FUNC_2 &pcfg_pull_up>;
955 <3 0 RK_FUNC_2 &pcfg_pull_up>;
959 <3 1 RK_FUNC_2 &pcfg_pull_up>;
966 <2 22 RK_FUNC_2 &pcfg_pull_up>;
970 <2 23 RK_FUNC_2 &pcfg_pull_up>;
974 <2 20 RK_FUNC_2 &pcfg_pull_up>;
978 <2 21 RK_FUNC_2 &pcfg_pull_up>;
983 uart0_xfer: uart0-xfer {
985 <2 16 RK_FUNC_1 &pcfg_pull_up>,
986 <2 17 RK_FUNC_1 &pcfg_pull_none>;
989 uart0_cts: uart0-cts {
991 <2 18 RK_FUNC_1 &pcfg_pull_none>;
994 uart0_rts: uart0-rts {
996 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1001 uart1_xfer: uart1-xfer {
1003 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1004 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1009 uart2a_xfer: uart2a-xfer {
1011 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1012 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1017 uart2b_xfer: uart2b-xfer {
1019 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1020 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1025 uart2c_xfer: uart2c-xfer {
1027 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1028 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1033 uart3_xfer: uart3-xfer {
1035 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1036 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1039 uart3_cts: uart3-cts {
1041 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1044 uart3_rts: uart3-rts {
1046 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1051 uart4_xfer: uart4-xfer {
1053 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1054 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1059 uarthdcp_xfer: uarthdcp-xfer {
1061 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1062 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1067 pwm0_pin: pwm0-pin {
1069 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1072 vop0_pwm_pin: vop0-pwm-pin {
1074 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1079 pwm1_pin: pwm1-pin {
1081 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1084 vop1_pwm_pin: vop1-pwm-pin {
1086 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1091 pwm2_pin: pwm2-pin {
1093 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1098 pwm3a_pin: pwm3a-pin {
1100 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1105 pwm3b_pin: pwm3b-pin {
1107 <1 14 RK_FUNC_1 &pcfg_pull_none>;