1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #define USB_CLASS_HUB 9
16 compatible = "rockchip,rk3399";
18 interrupt-parent = <&gic>;
73 compatible = "arm,cortex-a53", "arm,armv8";
75 enable-method = "psci";
76 #cooling-cells = <2>; /* min followed by max */
77 clocks = <&cru ARMCLKL>;
82 compatible = "arm,cortex-a53", "arm,armv8";
84 enable-method = "psci";
85 clocks = <&cru ARMCLKL>;
90 compatible = "arm,cortex-a53", "arm,armv8";
92 enable-method = "psci";
93 clocks = <&cru ARMCLKL>;
98 compatible = "arm,cortex-a53", "arm,armv8";
100 enable-method = "psci";
101 clocks = <&cru ARMCLKL>;
106 compatible = "arm,cortex-a72", "arm,armv8";
108 enable-method = "psci";
109 #cooling-cells = <2>; /* min followed by max */
110 clocks = <&cru ARMCLKB>;
115 compatible = "arm,cortex-a72", "arm,armv8";
117 enable-method = "psci";
118 clocks = <&cru ARMCLKB>;
123 compatible = "arm,cortex-a53-pmu";
124 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
128 compatible = "arm,cortex-a72-pmu";
129 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
133 compatible = "arm,psci-1.0";
138 compatible = "arm,armv8-timer";
139 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
140 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
141 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
142 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
143 arm,no-tick-in-suspend;
147 compatible = "fixed-clock";
148 clock-frequency = <24000000>;
149 clock-output-names = "xin24m";
154 compatible = "simple-bus";
155 #address-cells = <2>;
159 dmac_bus: dma-controller@ff6d0000 {
160 compatible = "arm,pl330", "arm,primecell";
161 reg = <0x0 0xff6d0000 0x0 0x4000>;
162 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
163 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
165 clocks = <&cru ACLK_DMAC0_PERILP>;
166 clock-names = "apb_pclk";
169 dmac_peri: dma-controller@ff6e0000 {
170 compatible = "arm,pl330", "arm,primecell";
171 reg = <0x0 0xff6e0000 0x0 0x4000>;
172 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
173 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
175 clocks = <&cru ACLK_DMAC1_PERILP>;
176 clock-names = "apb_pclk";
180 pcie0: pcie@f8000000 {
181 compatible = "rockchip,rk3399-pcie";
182 reg = <0x0 0xf8000000 0x0 0x2000000>,
183 <0x0 0xfd000000 0x0 0x1000000>;
184 reg-names = "axi-base", "apb-base";
185 #address-cells = <3>;
187 #interrupt-cells = <1>;
189 bus-range = <0x0 0x1>;
190 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
191 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
192 clock-names = "aclk", "aclk-perf",
194 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
195 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
196 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
197 interrupt-names = "sys", "legacy", "client";
198 interrupt-map-mask = <0 0 0 7>;
199 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
200 <0 0 0 2 &pcie0_intc 1>,
201 <0 0 0 3 &pcie0_intc 2>,
202 <0 0 0 4 &pcie0_intc 3>;
203 linux,pci-domain = <0>;
204 max-link-speed = <1>;
205 msi-map = <0x0 &its 0x0 0x1000>;
207 phy-names = "pcie-phy";
208 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
209 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
210 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
211 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
212 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
214 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
215 "pm", "pclk", "aclk";
218 pcie0_intc: interrupt-controller {
219 interrupt-controller;
220 #address-cells = <0>;
221 #interrupt-cells = <1>;
225 gmac: ethernet@fe300000 {
226 compatible = "rockchip,rk3399-gmac";
227 reg = <0x0 0xfe300000 0x0 0x10000>;
228 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
229 interrupt-names = "macirq";
230 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
231 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
232 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
234 clock-names = "stmmaceth", "mac_clk_rx",
235 "mac_clk_tx", "clk_mac_ref",
236 "clk_mac_refout", "aclk_mac",
238 power-domains = <&power RK3399_PD_GMAC>;
239 resets = <&cru SRST_A_GMAC>;
240 reset-names = "stmmaceth";
241 rockchip,grf = <&grf>;
245 sdio0: dwmmc@fe310000 {
246 compatible = "rockchip,rk3399-dw-mshc",
247 "rockchip,rk3288-dw-mshc";
248 reg = <0x0 0xfe310000 0x0 0x4000>;
249 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
250 max-frequency = <150000000>;
251 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
252 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
253 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
254 fifo-depth = <0x100>;
255 power-domains = <&power RK3399_PD_SDIOAUDIO>;
256 resets = <&cru SRST_SDIO0>;
257 reset-names = "reset";
261 sdmmc: dwmmc@fe320000 {
262 compatible = "rockchip,rk3399-dw-mshc",
263 "rockchip,rk3288-dw-mshc";
264 reg = <0x0 0xfe320000 0x0 0x4000>;
265 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
266 max-frequency = <150000000>;
267 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
268 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
269 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
270 fifo-depth = <0x100>;
271 power-domains = <&power RK3399_PD_SD>;
272 resets = <&cru SRST_SDMMC>;
273 reset-names = "reset";
277 sdhci: sdhci@fe330000 {
279 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
280 reg = <0x0 0xfe330000 0x0 0x10000>;
281 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
282 arasan,soc-ctl-syscon = <&grf>;
283 assigned-clocks = <&cru SCLK_EMMC>;
284 assigned-clock-rates = <200000000>;
285 max-frequency = <200000000>;
286 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
287 clock-names = "clk_xin", "clk_ahb";
288 clock-output-names = "emmc_cardclock";
291 phy-names = "phy_arasan";
292 power-domains = <&power RK3399_PD_EMMC>;
296 usb_host0_ehci: usb@fe380000 {
297 compatible = "generic-ehci";
298 reg = <0x0 0xfe380000 0x0 0x20000>;
299 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
300 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
302 clock-names = "usbhost", "arbiter",
304 phys = <&u2phy0_host>;
306 power-domains = <&power RK3399_PD_PERIHP>;
310 usb_host0_ohci: usb@fe3a0000 {
311 compatible = "generic-ohci";
312 reg = <0x0 0xfe3a0000 0x0 0x20000>;
313 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
314 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
316 clock-names = "usbhost", "arbiter",
318 phys = <&u2phy0_host>;
320 power-domains = <&power RK3399_PD_PERIHP>;
324 usb_host1_ehci: usb@fe3c0000 {
325 compatible = "generic-ehci";
326 reg = <0x0 0xfe3c0000 0x0 0x20000>;
327 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
328 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
330 clock-names = "usbhost", "arbiter",
332 phys = <&u2phy1_host>;
334 power-domains = <&power RK3399_PD_PERIHP>;
338 usb_host1_ohci: usb@fe3e0000 {
339 compatible = "generic-ohci";
340 reg = <0x0 0xfe3e0000 0x0 0x20000>;
341 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
342 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
344 clock-names = "usbhost", "arbiter",
346 phys = <&u2phy1_host>;
348 power-domains = <&power RK3399_PD_PERIHP>;
352 dwc3_typec0: usb@fe800000 {
353 compatible = "rockchip,rk3399-xhci";
354 reg = <0x0 0xfe800000 0x0 0x100000>;
356 snps,dis-enblslpm-quirk;
357 snps,phyif-utmi-bits = <16>;
358 snps,dis-u2-freeclk-exists-quirk;
359 snps,dis-u2-susphy-quirk;
361 #address-cells = <2>;
364 compatible = "usb-hub";
365 usb,device-class = <USB_CLASS_HUB>;
368 compatible = "rockchip,rk3399-usb3-phy";
369 reg = <0x0 0xff7c0000 0x0 0x40000>;
373 dwc3_typec1: usb@fe900000 {
374 compatible = "rockchip,rk3399-xhci";
375 reg = <0x0 0xfe900000 0x0 0x100000>;
377 snps,dis-enblslpm-quirk;
378 snps,phyif-utmi-bits = <16>;
379 snps,dis-u2-freeclk-exists-quirk;
380 snps,dis-u2-susphy-quirk;
382 #address-cells = <2>;
385 compatible = "usb-hub";
386 usb,device-class = <USB_CLASS_HUB>;
389 compatible = "rockchip,rk3399-usb3-phy";
390 reg = <0x0 0xff800000 0x0 0x40000>;
394 gic: interrupt-controller@fee00000 {
395 compatible = "arm,gic-v3";
396 #interrupt-cells = <4>;
397 #address-cells = <2>;
400 interrupt-controller;
402 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
403 <0x0 0xfef00000 0 0xc0000>, /* GICR */
404 <0x0 0xfff00000 0 0x10000>, /* GICC */
405 <0x0 0xfff10000 0 0x10000>, /* GICH */
406 <0x0 0xfff20000 0 0x10000>; /* GICV */
407 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
408 its: interrupt-controller@fee20000 {
409 compatible = "arm,gic-v3-its";
411 reg = <0x0 0xfee20000 0x0 0x20000>;
415 ppi_cluster0: interrupt-partition-0 {
416 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
419 ppi_cluster1: interrupt-partition-1 {
420 affinity = <&cpu_b0 &cpu_b1>;
425 saradc: saradc@ff100000 {
426 compatible = "rockchip,rk3399-saradc";
427 reg = <0x0 0xff100000 0x0 0x100>;
428 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
429 #io-channel-cells = <1>;
430 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
431 clock-names = "saradc", "apb_pclk";
432 resets = <&cru SRST_P_SARADC>;
433 reset-names = "saradc-apb";
438 compatible = "rockchip,rk3399-i2c";
439 reg = <0x0 0xff110000 0x0 0x1000>;
440 assigned-clocks = <&cru SCLK_I2C1>;
441 assigned-clock-rates = <200000000>;
442 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
443 clock-names = "i2c", "pclk";
444 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&i2c1_xfer>;
447 #address-cells = <1>;
453 compatible = "rockchip,rk3399-i2c";
454 reg = <0x0 0xff120000 0x0 0x1000>;
455 assigned-clocks = <&cru SCLK_I2C2>;
456 assigned-clock-rates = <200000000>;
457 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
458 clock-names = "i2c", "pclk";
459 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&i2c2_xfer>;
462 #address-cells = <1>;
468 compatible = "rockchip,rk3399-i2c";
469 reg = <0x0 0xff130000 0x0 0x1000>;
470 assigned-clocks = <&cru SCLK_I2C3>;
471 assigned-clock-rates = <200000000>;
472 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
473 clock-names = "i2c", "pclk";
474 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
475 pinctrl-names = "default";
476 pinctrl-0 = <&i2c3_xfer>;
477 #address-cells = <1>;
483 compatible = "rockchip,rk3399-i2c";
484 reg = <0x0 0xff140000 0x0 0x1000>;
485 assigned-clocks = <&cru SCLK_I2C5>;
486 assigned-clock-rates = <200000000>;
487 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
488 clock-names = "i2c", "pclk";
489 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&i2c5_xfer>;
492 #address-cells = <1>;
498 compatible = "rockchip,rk3399-i2c";
499 reg = <0x0 0xff150000 0x0 0x1000>;
500 assigned-clocks = <&cru SCLK_I2C6>;
501 assigned-clock-rates = <200000000>;
502 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
503 clock-names = "i2c", "pclk";
504 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
505 pinctrl-names = "default";
506 pinctrl-0 = <&i2c6_xfer>;
507 #address-cells = <1>;
513 compatible = "rockchip,rk3399-i2c";
514 reg = <0x0 0xff160000 0x0 0x1000>;
515 assigned-clocks = <&cru SCLK_I2C7>;
516 assigned-clock-rates = <200000000>;
517 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
518 clock-names = "i2c", "pclk";
519 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c7_xfer>;
522 #address-cells = <1>;
527 uart0: serial@ff180000 {
528 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
529 reg = <0x0 0xff180000 0x0 0x100>;
530 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
531 clock-names = "baudclk", "apb_pclk";
532 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&uart0_xfer>;
540 uart1: serial@ff190000 {
541 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
542 reg = <0x0 0xff190000 0x0 0x100>;
543 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
544 clock-names = "baudclk", "apb_pclk";
545 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
548 pinctrl-names = "default";
549 pinctrl-0 = <&uart1_xfer>;
553 uart2: serial@ff1a0000 {
554 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
555 reg = <0x0 0xff1a0000 0x0 0x100>;
556 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
557 clock-names = "baudclk", "apb_pclk";
558 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
559 clock-frequency = <24000000>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&uart2c_xfer>;
567 uart3: serial@ff1b0000 {
568 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
569 reg = <0x0 0xff1b0000 0x0 0x100>;
570 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
571 clock-names = "baudclk", "apb_pclk";
572 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
575 pinctrl-names = "default";
576 pinctrl-0 = <&uart3_xfer>;
581 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
582 reg = <0x0 0xff1c0000 0x0 0x1000>;
583 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
584 clock-names = "spiclk", "apb_pclk";
585 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
588 #address-cells = <1>;
594 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
595 reg = <0x0 0xff1d0000 0x0 0x1000>;
596 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
597 clock-names = "spiclk", "apb_pclk";
598 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
599 pinctrl-names = "default";
600 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
601 #address-cells = <1>;
607 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
608 reg = <0x0 0xff1e0000 0x0 0x1000>;
609 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
610 clock-names = "spiclk", "apb_pclk";
611 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
612 pinctrl-names = "default";
613 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
614 #address-cells = <1>;
620 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
621 reg = <0x0 0xff1f0000 0x0 0x1000>;
622 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
623 clock-names = "spiclk", "apb_pclk";
624 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
625 pinctrl-names = "default";
626 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
627 #address-cells = <1>;
633 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
634 reg = <0x0 0xff200000 0x0 0x1000>;
635 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
636 clock-names = "spiclk", "apb_pclk";
637 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
638 pinctrl-names = "default";
639 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
640 #address-cells = <1>;
645 thermal_zones: thermal-zones {
647 polling-delay-passive = <100>;
648 polling-delay = <1000>;
650 thermal-sensors = <&tsadc 0>;
653 cpu_alert0: cpu_alert0 {
654 temperature = <70000>;
658 cpu_alert1: cpu_alert1 {
659 temperature = <75000>;
664 temperature = <95000>;
672 trip = <&cpu_alert0>;
674 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
677 trip = <&cpu_alert1>;
679 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
680 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
686 polling-delay-passive = <100>;
687 polling-delay = <1000>;
689 thermal-sensors = <&tsadc 1>;
692 gpu_alert0: gpu_alert0 {
693 temperature = <75000>;
698 temperature = <95000>;
706 trip = <&gpu_alert0>;
708 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
714 tsadc: tsadc@ff260000 {
715 compatible = "rockchip,rk3399-tsadc";
716 reg = <0x0 0xff260000 0x0 0x100>;
717 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
718 assigned-clocks = <&cru SCLK_TSADC>;
719 assigned-clock-rates = <750000>;
720 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
721 clock-names = "tsadc", "apb_pclk";
722 resets = <&cru SRST_TSADC>;
723 reset-names = "tsadc-apb";
724 rockchip,grf = <&grf>;
725 rockchip,hw-tshut-temp = <95000>;
726 pinctrl-names = "init", "default", "sleep";
727 pinctrl-0 = <&otp_gpio>;
728 pinctrl-1 = <&otp_out>;
729 pinctrl-2 = <&otp_gpio>;
730 #thermal-sensor-cells = <1>;
734 qos_emmc: qos@ffa58000 {
735 compatible = "syscon";
736 reg = <0x0 0xffa58000 0x0 0x20>;
739 qos_gmac: qos@ffa5c000 {
740 compatible = "syscon";
741 reg = <0x0 0xffa5c000 0x0 0x20>;
744 qos_pcie: qos@ffa60080 {
745 compatible = "syscon";
746 reg = <0x0 0xffa60080 0x0 0x20>;
749 qos_usb_host0: qos@ffa60100 {
750 compatible = "syscon";
751 reg = <0x0 0xffa60100 0x0 0x20>;
754 qos_usb_host1: qos@ffa60180 {
755 compatible = "syscon";
756 reg = <0x0 0xffa60180 0x0 0x20>;
759 qos_usb_otg0: qos@ffa70000 {
760 compatible = "syscon";
761 reg = <0x0 0xffa70000 0x0 0x20>;
764 qos_usb_otg1: qos@ffa70080 {
765 compatible = "syscon";
766 reg = <0x0 0xffa70080 0x0 0x20>;
769 qos_sd: qos@ffa74000 {
770 compatible = "syscon";
771 reg = <0x0 0xffa74000 0x0 0x20>;
774 qos_sdioaudio: qos@ffa76000 {
775 compatible = "syscon";
776 reg = <0x0 0xffa76000 0x0 0x20>;
779 qos_hdcp: qos@ffa90000 {
780 compatible = "syscon";
781 reg = <0x0 0xffa90000 0x0 0x20>;
784 qos_iep: qos@ffa98000 {
785 compatible = "syscon";
786 reg = <0x0 0xffa98000 0x0 0x20>;
789 qos_isp0_m0: qos@ffaa0000 {
790 compatible = "syscon";
791 reg = <0x0 0xffaa0000 0x0 0x20>;
794 qos_isp0_m1: qos@ffaa0080 {
795 compatible = "syscon";
796 reg = <0x0 0xffaa0080 0x0 0x20>;
799 qos_isp1_m0: qos@ffaa8000 {
800 compatible = "syscon";
801 reg = <0x0 0xffaa8000 0x0 0x20>;
804 qos_isp1_m1: qos@ffaa8080 {
805 compatible = "syscon";
806 reg = <0x0 0xffaa8080 0x0 0x20>;
809 qos_rga_r: qos@ffab0000 {
810 compatible = "syscon";
811 reg = <0x0 0xffab0000 0x0 0x20>;
814 qos_rga_w: qos@ffab0080 {
815 compatible = "syscon";
816 reg = <0x0 0xffab0080 0x0 0x20>;
819 qos_video_m0: qos@ffab8000 {
820 compatible = "syscon";
821 reg = <0x0 0xffab8000 0x0 0x20>;
824 qos_video_m1_r: qos@ffac0000 {
825 compatible = "syscon";
826 reg = <0x0 0xffac0000 0x0 0x20>;
829 qos_video_m1_w: qos@ffac0080 {
830 compatible = "syscon";
831 reg = <0x0 0xffac0080 0x0 0x20>;
834 qos_vop_big_r: qos@ffac8000 {
835 compatible = "syscon";
836 reg = <0x0 0xffac8000 0x0 0x20>;
839 qos_vop_big_w: qos@ffac8080 {
840 compatible = "syscon";
841 reg = <0x0 0xffac8080 0x0 0x20>;
844 qos_vop_little: qos@ffad0000 {
845 compatible = "syscon";
846 reg = <0x0 0xffad0000 0x0 0x20>;
849 qos_perihp: qos@ffad8080 {
850 compatible = "syscon";
851 reg = <0x0 0xffad8080 0x0 0x20>;
854 qos_gpu: qos@ffae0000 {
855 compatible = "syscon";
856 reg = <0x0 0xffae0000 0x0 0x20>;
859 pmu: power-management@ff310000 {
860 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
861 reg = <0x0 0xff310000 0x0 0x1000>;
864 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
865 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
866 * Some of the power domains are grouped together for every
868 * The detail contents as below.
870 power: power-controller {
871 compatible = "rockchip,rk3399-power-controller";
872 #power-domain-cells = <1>;
873 #address-cells = <1>;
876 /* These power domains are grouped by VD_CENTER */
877 pd_iep@RK3399_PD_IEP {
878 reg = <RK3399_PD_IEP>;
879 clocks = <&cru ACLK_IEP>,
883 pd_rga@RK3399_PD_RGA {
884 reg = <RK3399_PD_RGA>;
885 clocks = <&cru ACLK_RGA>,
887 pm_qos = <&qos_rga_r>,
890 pd_vcodec@RK3399_PD_VCODEC {
891 reg = <RK3399_PD_VCODEC>;
892 clocks = <&cru ACLK_VCODEC>,
894 pm_qos = <&qos_video_m0>;
896 pd_vdu@RK3399_PD_VDU {
897 reg = <RK3399_PD_VDU>;
898 clocks = <&cru ACLK_VDU>,
900 pm_qos = <&qos_video_m1_r>,
904 /* These power domains are grouped by VD_GPU */
905 pd_gpu@RK3399_PD_GPU {
906 reg = <RK3399_PD_GPU>;
907 clocks = <&cru ACLK_GPU>;
911 /* These power domains are grouped by VD_LOGIC */
912 pd_edp@RK3399_PD_EDP {
913 reg = <RK3399_PD_EDP>;
914 clocks = <&cru PCLK_EDP_CTRL>;
916 pd_emmc@RK3399_PD_EMMC {
917 reg = <RK3399_PD_EMMC>;
918 clocks = <&cru ACLK_EMMC>;
919 pm_qos = <&qos_emmc>;
921 pd_gmac@RK3399_PD_GMAC {
922 reg = <RK3399_PD_GMAC>;
923 clocks = <&cru ACLK_GMAC>,
925 pm_qos = <&qos_gmac>;
927 pd_perihp@RK3399_PD_PERIHP {
928 reg = <RK3399_PD_PERIHP>;
929 #address-cells = <1>;
931 clocks = <&cru ACLK_PERIHP>;
932 pm_qos = <&qos_perihp>,
938 reg = <RK3399_PD_SD>;
939 clocks = <&cru HCLK_SDMMC>,
944 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
945 reg = <RK3399_PD_SDIOAUDIO>;
946 clocks = <&cru HCLK_SDIO>;
947 pm_qos = <&qos_sdioaudio>;
949 pd_usb3@RK3399_PD_USB3 {
950 reg = <RK3399_PD_USB3>;
951 clocks = <&cru ACLK_USB3>;
952 pm_qos = <&qos_usb_otg0>,
955 pd_vio@RK3399_PD_VIO {
956 reg = <RK3399_PD_VIO>;
957 #address-cells = <1>;
960 pd_hdcp@RK3399_PD_HDCP {
961 reg = <RK3399_PD_HDCP>;
962 clocks = <&cru ACLK_HDCP>,
965 pm_qos = <&qos_hdcp>;
967 pd_isp0@RK3399_PD_ISP0 {
968 reg = <RK3399_PD_ISP0>;
969 clocks = <&cru ACLK_ISP0>,
971 pm_qos = <&qos_isp0_m0>,
974 pd_isp1@RK3399_PD_ISP1 {
975 reg = <RK3399_PD_ISP1>;
976 clocks = <&cru ACLK_ISP1>,
978 pm_qos = <&qos_isp1_m0>,
981 pd_tcpc0@RK3399_PD_TCPC0 {
982 reg = <RK3399_PD_TCPD0>;
983 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
984 <&cru SCLK_UPHY0_TCPDPHY_REF>;
986 pd_tcpc1@RK3399_PD_TCPC1 {
987 reg = <RK3399_PD_TCPD1>;
988 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
989 <&cru SCLK_UPHY1_TCPDPHY_REF>;
992 reg = <RK3399_PD_VO>;
993 #address-cells = <1>;
996 pd_vopb@RK3399_PD_VOPB {
997 reg = <RK3399_PD_VOPB>;
998 clocks = <&cru ACLK_VOP0>,
1000 pm_qos = <&qos_vop_big_r>,
1003 pd_vopl@RK3399_PD_VOPL {
1004 reg = <RK3399_PD_VOPL>;
1005 clocks = <&cru ACLK_VOP1>,
1007 pm_qos = <&qos_vop_little>;
1014 pmugrf: syscon@ff320000 {
1015 u-boot,dm-pre-reloc;
1016 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1017 reg = <0x0 0xff320000 0x0 0x1000>;
1019 pmu_io_domains: io-domains {
1020 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1021 status = "disabled";
1025 pmusgrf: syscon@ff330000 {
1026 u-boot,dm-pre-reloc;
1027 compatible = "rockchip,rk3399-pmusgrf", "syscon";
1028 reg = <0x0 0xff330000 0x0 0xe3d4>;
1031 spi3: spi@ff350000 {
1032 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1033 reg = <0x0 0xff350000 0x0 0x1000>;
1034 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1035 clock-names = "spiclk", "apb_pclk";
1036 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1037 pinctrl-names = "default";
1038 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1039 #address-cells = <1>;
1041 status = "disabled";
1044 uart4: serial@ff370000 {
1045 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1046 reg = <0x0 0xff370000 0x0 0x100>;
1047 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1048 clock-names = "baudclk", "apb_pclk";
1049 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1052 pinctrl-names = "default";
1053 pinctrl-0 = <&uart4_xfer>;
1054 status = "disabled";
1057 i2c4: i2c@ff3d0000 {
1058 compatible = "rockchip,rk3399-i2c";
1059 reg = <0x0 0xff3d0000 0x0 0x1000>;
1060 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1061 assigned-clock-rates = <200000000>;
1062 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1063 clock-names = "i2c", "pclk";
1064 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1065 pinctrl-names = "default";
1066 pinctrl-0 = <&i2c4_xfer>;
1067 #address-cells = <1>;
1069 status = "disabled";
1072 i2c8: i2c@ff3e0000 {
1073 compatible = "rockchip,rk3399-i2c";
1074 reg = <0x0 0xff3e0000 0x0 0x1000>;
1075 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1076 assigned-clock-rates = <200000000>;
1077 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1078 clock-names = "i2c", "pclk";
1079 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1080 pinctrl-names = "default";
1081 pinctrl-0 = <&i2c8_xfer>;
1082 #address-cells = <1>;
1084 status = "disabled";
1087 pwm0: pwm@ff420000 {
1088 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1089 reg = <0x0 0xff420000 0x0 0x10>;
1091 pinctrl-names = "default";
1092 pinctrl-0 = <&pwm0_pin>;
1093 clocks = <&pmucru PCLK_RKPWM_PMU>;
1094 clock-names = "pwm";
1095 status = "disabled";
1098 pwm1: pwm@ff420010 {
1099 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1100 reg = <0x0 0xff420010 0x0 0x10>;
1102 pinctrl-names = "default";
1103 pinctrl-0 = <&pwm1_pin>;
1104 clocks = <&pmucru PCLK_RKPWM_PMU>;
1105 clock-names = "pwm";
1106 status = "disabled";
1109 pwm2: pwm@ff420020 {
1110 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1111 reg = <0x0 0xff420020 0x0 0x10>;
1113 pinctrl-names = "default";
1114 pinctrl-0 = <&pwm2_pin>;
1115 clocks = <&pmucru PCLK_RKPWM_PMU>;
1116 clock-names = "pwm";
1117 status = "disabled";
1120 pwm3: pwm@ff420030 {
1121 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1122 reg = <0x0 0xff420030 0x0 0x10>;
1124 pinctrl-names = "default";
1125 pinctrl-0 = <&pwm3a_pin>;
1126 clocks = <&pmucru PCLK_RKPWM_PMU>;
1127 clock-names = "pwm";
1128 status = "disabled";
1131 cic: syscon@ff620000 {
1132 u-boot,dm-pre-reloc;
1133 compatible = "rockchip,rk3399-cic", "syscon";
1134 reg = <0x0 0xff620000 0x0 0x100>;
1138 reg = <0x00 0xff630000 0x00 0x4000>;
1139 compatible = "rockchip,rk3399-dfi";
1140 rockchip,pmu = <&pmugrf>;
1141 clocks = <&cru PCLK_DDR_MON>;
1142 clock-names = "pclk_ddr_mon";
1143 status = "disabled";
1147 u-boot,dm-pre-reloc;
1148 compatible = "rockchip,rk3399-dmc";
1149 devfreq-events = <&dfi>;
1150 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1151 clocks = <&cru SCLK_DDRCLK>;
1152 clock-names = "dmc_clk";
1153 reg = <0x0 0xffa80000 0x0 0x0800
1154 0x0 0xffa80800 0x0 0x1800
1155 0x0 0xffa82000 0x0 0x2000
1156 0x0 0xffa84000 0x0 0x1000
1157 0x0 0xffa88000 0x0 0x0800
1158 0x0 0xffa88800 0x0 0x1800
1159 0x0 0xffa8a000 0x0 0x2000
1160 0x0 0xffa8c000 0x0 0x1000>;
1163 efuse0: efuse@ff690000 {
1164 compatible = "rockchip,rk3399-efuse";
1165 reg = <0x0 0xff690000 0x0 0x80>;
1166 #address-cells = <1>;
1168 clocks = <&cru PCLK_EFUSE1024NS>;
1169 clock-names = "pclk_efuse";
1175 cpub_leakage: cpu-leakage@17 {
1178 gpu_leakage: gpu-leakage@18 {
1181 center_leakage: center-leakage@19 {
1184 cpul_leakage: cpu-leakage@1a {
1187 logic_leakage: logic-leakage@1b {
1190 wafer_info: wafer-info@1c {
1195 pmucru: pmu-clock-controller@ff750000 {
1196 u-boot,dm-pre-reloc;
1197 compatible = "rockchip,rk3399-pmucru";
1198 reg = <0x0 0xff750000 0x0 0x1000>;
1199 rockchip,grf = <&pmugrf>;
1202 assigned-clocks = <&pmucru PLL_PPLL>;
1203 assigned-clock-rates = <676000000>;
1206 cru: clock-controller@ff760000 {
1207 u-boot,dm-pre-reloc;
1208 compatible = "rockchip,rk3399-cru";
1209 reg = <0x0 0xff760000 0x0 0x1000>;
1210 rockchip,grf = <&grf>;
1214 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1216 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1218 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1219 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1220 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1221 assigned-clock-rates =
1222 <594000000>, <800000000>,
1224 <150000000>, <75000000>,
1226 <100000000>, <100000000>,
1227 <50000000>, <600000000>,
1228 <100000000>, <50000000>;
1231 grf: syscon@ff770000 {
1232 u-boot,dm-pre-reloc;
1233 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1234 reg = <0x0 0xff770000 0x0 0x10000>;
1235 #address-cells = <1>;
1238 io_domains: io-domains {
1239 compatible = "rockchip,rk3399-io-voltage-domain";
1240 status = "disabled";
1243 u2phy0: usb2-phy@e450 {
1244 compatible = "rockchip,rk3399-usb2phy";
1245 reg = <0xe450 0x10>;
1246 clocks = <&cru SCLK_USB2PHY0_REF>;
1247 clock-names = "phyclk";
1249 clock-output-names = "clk_usbphy0_480m";
1250 status = "disabled";
1252 u2phy0_host: host-port {
1254 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1255 interrupt-names = "linestate";
1256 status = "disabled";
1259 u2phy0_otg: otg-port {
1261 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1262 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1263 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1264 interrupt-names = "otg-bvalid", "otg-id",
1266 status = "disabled";
1270 u2phy1: usb2-phy@e460 {
1271 compatible = "rockchip,rk3399-usb2phy";
1272 reg = <0xe460 0x10>;
1273 clocks = <&cru SCLK_USB2PHY1_REF>;
1274 clock-names = "phyclk";
1276 clock-output-names = "clk_usbphy1_480m";
1277 status = "disabled";
1279 u2phy1_host: host-port {
1281 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1282 interrupt-names = "linestate";
1283 status = "disabled";
1286 u2phy1_otg: otg-port {
1288 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1289 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1290 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1291 interrupt-names = "otg-bvalid", "otg-id",
1293 status = "disabled";
1297 emmc_phy: phy@f780 {
1298 compatible = "rockchip,rk3399-emmc-phy";
1299 reg = <0xf780 0x24>;
1301 clock-names = "emmcclk";
1303 status = "disabled";
1306 pcie_phy: pcie-phy {
1307 compatible = "rockchip,rk3399-pcie-phy";
1308 clocks = <&cru SCLK_PCIEPHY_REF>;
1309 clock-names = "refclk";
1311 resets = <&cru SRST_PCIEPHY>;
1312 reset-names = "phy";
1313 status = "disabled";
1318 compatible = "snps,dw-wdt";
1319 reg = <0x0 0xff848000 0x0 0x100>;
1320 clocks = <&cru PCLK_WDT>;
1321 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1324 rktimer: rktimer@ff850000 {
1325 compatible = "rockchip,rk3399-timer";
1326 reg = <0x0 0xff850000 0x0 0x1000>;
1327 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1328 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1329 clock-names = "pclk", "timer";
1332 spdif: spdif@ff870000 {
1333 compatible = "rockchip,rk3399-spdif";
1334 reg = <0x0 0xff870000 0x0 0x1000>;
1335 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1336 dmas = <&dmac_bus 7>;
1338 clock-names = "mclk", "hclk";
1339 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1340 pinctrl-names = "default";
1341 pinctrl-0 = <&spdif_bus>;
1342 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1343 status = "disabled";
1346 i2s0: i2s@ff880000 {
1347 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1348 reg = <0x0 0xff880000 0x0 0x1000>;
1349 rockchip,grf = <&grf>;
1350 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1351 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1352 dma-names = "tx", "rx";
1353 clock-names = "i2s_clk", "i2s_hclk";
1354 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1355 pinctrl-names = "default";
1356 pinctrl-0 = <&i2s0_8ch_bus>;
1357 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1358 status = "disabled";
1361 i2s1: i2s@ff890000 {
1362 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1363 reg = <0x0 0xff890000 0x0 0x1000>;
1364 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1365 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1366 dma-names = "tx", "rx";
1367 clock-names = "i2s_clk", "i2s_hclk";
1368 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1369 pinctrl-names = "default";
1370 pinctrl-0 = <&i2s1_2ch_bus>;
1371 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1372 status = "disabled";
1375 i2s2: i2s@ff8a0000 {
1376 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1377 reg = <0x0 0xff8a0000 0x0 0x1000>;
1378 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1379 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1380 dma-names = "tx", "rx";
1381 clock-names = "i2s_clk", "i2s_hclk";
1382 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1383 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1384 status = "disabled";
1387 i2c0: i2c@ff3c0000 {
1388 compatible = "rockchip,rk3399-i2c";
1389 reg = <0x0 0xff3c0000 0x0 0x1000>;
1390 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1391 assigned-clock-rates = <200000000>;
1392 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1393 clock-names = "i2c", "pclk";
1394 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1395 pinctrl-names = "default";
1396 pinctrl-0 = <&i2c0_xfer>;
1397 #address-cells = <1>;
1399 status = "disabled";
1402 vopl: vop@ff8f0000 {
1403 u-boot,dm-pre-reloc;
1404 compatible = "rockchip,rk3399-vop-lit";
1405 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1406 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1407 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1408 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1409 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1410 reset-names = "axi", "ahb", "dclk";
1411 status = "disabled";
1413 #address-cells = <1>;
1415 vopl_out_mipi: endpoint@0 {
1417 remote-endpoint = <&mipi_in_vopl>;
1420 vopl_out_hdmi: endpoint@1 {
1422 remote-endpoint = <&hdmi_in_vopl>;
1427 vopb: vop@ff900000 {
1428 u-boot,dm-pre-reloc;
1429 compatible = "rockchip,rk3399-vop-big";
1430 reg = <0x0 0xff900000 0x0 0x3efc>;
1431 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1432 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1434 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1435 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1436 reset-names = "axi", "ahb", "dclk";
1437 status = "disabled";
1439 #address-cells = <1>;
1441 vopb_out_mipi: endpoint@0 {
1443 remote-endpoint = <&mipi_in_vopb>;
1446 vopb_out_hdmi: endpoint@1 {
1448 remote-endpoint = <&hdmi_in_vopb>;
1453 hdmi: hdmi@ff940000 {
1454 compatible = "rockchip,rk3399-dw-hdmi";
1455 reg = <0x0 0xff940000 0x0 0x20000>;
1457 rockchip,grf = <&grf>;
1458 pinctrl-names = "default";
1459 pinctrl-0 = <&hdmi_i2c_xfer>;
1460 power-domains = <&power RK3399_PD_HDCP>;
1461 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1462 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1463 clock-names = "iahb", "isfr", "vpll", "grf";
1464 status = "disabled";
1468 #address-cells = <1>;
1470 hdmi_in_vopb: endpoint@0 {
1472 remote-endpoint = <&vopb_out_hdmi>;
1474 hdmi_in_vopl: endpoint@1 {
1476 remote-endpoint = <&vopl_out_hdmi>;
1482 mipi_dsi: mipi@ff960000 {
1483 compatible = "rockchip,rk3399_mipi_dsi";
1484 reg = <0x0 0xff960000 0x0 0x8000>;
1485 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1486 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1487 <&cru SCLK_DPHY_TX0_CFG>;
1488 clock-names = "ref", "pclk", "phy_cfg";
1489 rockchip,grf = <&grf>;
1490 #address-cells = <1>;
1492 status = "disabled";
1496 #address-cells = <1>;
1498 mipi_in_vopb: endpoint@0 {
1500 remote-endpoint = <&vopb_out_mipi>;
1502 mipi_in_vopl: endpoint@1 {
1504 remote-endpoint = <&vopl_out_mipi>;
1511 u-boot,dm-pre-reloc;
1512 compatible = "rockchip,rk3399-pinctrl";
1513 rockchip,grf = <&grf>;
1514 rockchip,pmu = <&pmugrf>;
1515 #address-cells = <2>;
1519 gpio0: gpio0@ff720000 {
1520 compatible = "rockchip,gpio-bank";
1521 reg = <0x0 0xff720000 0x0 0x100>;
1522 clocks = <&pmucru PCLK_GPIO0_PMU>;
1523 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1526 #gpio-cells = <0x2>;
1528 interrupt-controller;
1529 #interrupt-cells = <0x2>;
1532 gpio1: gpio1@ff730000 {
1533 compatible = "rockchip,gpio-bank";
1534 reg = <0x0 0xff730000 0x0 0x100>;
1535 clocks = <&pmucru PCLK_GPIO1_PMU>;
1536 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1539 #gpio-cells = <0x2>;
1541 interrupt-controller;
1542 #interrupt-cells = <0x2>;
1545 gpio2: gpio2@ff780000 {
1546 compatible = "rockchip,gpio-bank";
1547 reg = <0x0 0xff780000 0x0 0x100>;
1548 clocks = <&cru PCLK_GPIO2>;
1549 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1552 #gpio-cells = <0x2>;
1554 interrupt-controller;
1555 #interrupt-cells = <0x2>;
1558 gpio3: gpio3@ff788000 {
1559 compatible = "rockchip,gpio-bank";
1560 reg = <0x0 0xff788000 0x0 0x100>;
1561 clocks = <&cru PCLK_GPIO3>;
1562 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1565 #gpio-cells = <0x2>;
1567 interrupt-controller;
1568 #interrupt-cells = <0x2>;
1571 gpio4: gpio4@ff790000 {
1572 compatible = "rockchip,gpio-bank";
1573 reg = <0x0 0xff790000 0x0 0x100>;
1574 clocks = <&cru PCLK_GPIO4>;
1575 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1578 #gpio-cells = <0x2>;
1580 interrupt-controller;
1581 #interrupt-cells = <0x2>;
1584 pcfg_pull_up: pcfg-pull-up {
1588 pcfg_pull_down: pcfg-pull-down {
1592 pcfg_pull_none: pcfg-pull-none {
1596 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1598 drive-strength = <12>;
1601 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1603 drive-strength = <13>;
1606 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1608 drive-strength = <18>;
1611 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1613 drive-strength = <20>;
1616 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1618 drive-strength = <2>;
1621 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1623 drive-strength = <8>;
1626 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
1628 drive-strength = <18>;
1631 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1633 drive-strength = <20>;
1636 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1638 drive-strength = <4>;
1641 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
1643 drive-strength = <8>;
1646 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1648 drive-strength = <12>;
1651 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
1653 drive-strength = <18>;
1656 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
1658 drive-strength = <20>;
1661 pcfg_output_high: pcfg-output-high {
1665 pcfg_output_low: pcfg-output-low {
1671 rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>;
1678 <4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>;
1683 rgmii_pins: rgmii-pins {
1686 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1688 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
1690 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
1692 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1694 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
1696 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
1698 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
1700 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
1702 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
1704 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1706 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1708 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
1710 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
1712 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1714 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1717 rmii_pins: rmii-pins {
1720 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
1722 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1724 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
1726 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
1728 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
1730 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
1732 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
1734 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
1736 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1738 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1743 i2c0_xfer: i2c0-xfer {
1745 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
1746 <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>;
1751 i2c1_xfer: i2c1-xfer {
1753 <4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
1754 <4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
1759 i2c2_xfer: i2c2-xfer {
1761 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1762 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1767 i2c3_xfer: i2c3-xfer {
1769 <4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
1770 <4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
1775 i2c4_xfer: i2c4-xfer {
1777 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
1778 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
1783 i2c5_xfer: i2c5-xfer {
1785 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>,
1786 <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>;
1791 i2c6_xfer: i2c6-xfer {
1793 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>,
1794 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
1799 i2c7_xfer: i2c7-xfer {
1801 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
1802 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
1807 i2c8_xfer: i2c8-xfer {
1809 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
1810 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
1815 i2s0_8ch_bus: i2s0-8ch-bus {
1817 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1818 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
1819 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
1820 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>,
1821 <3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>,
1822 <3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>,
1823 <3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>,
1824 <3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>,
1825 <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>;
1830 i2s1_2ch_bus: i2s1-2ch-bus {
1832 <4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
1833 <4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
1834 <4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
1835 <4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
1836 <4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
1841 sdio0_bus1: sdio0-bus1 {
1843 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
1846 sdio0_bus4: sdio0-bus4 {
1848 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
1849 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
1850 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
1851 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
1854 sdio0_cmd: sdio0-cmd {
1856 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
1859 sdio0_clk: sdio0-clk {
1861 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
1864 sdio0_cd: sdio0-cd {
1866 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
1869 sdio0_pwr: sdio0-pwr {
1871 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
1874 sdio0_bkpwr: sdio0-bkpwr {
1876 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
1879 sdio0_wp: sdio0-wp {
1881 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
1884 sdio0_int: sdio0-int {
1886 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
1891 sdmmc_bus1: sdmmc-bus1 {
1893 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
1896 sdmmc_bus4: sdmmc-bus4 {
1898 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
1899 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
1900 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
1901 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
1904 sdmmc_clk: sdmmc-clk {
1906 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
1909 sdmmc_cmd: sdmmc-cmd {
1911 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
1914 sdmmc_cd: sdmcc-cd {
1916 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
1919 sdmmc_wp: sdmmc-wp {
1921 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
1926 ap_pwroff: ap-pwroff {
1927 rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
1930 ddrio_pwroff: ddrio-pwroff {
1931 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
1936 spdif_bus: spdif-bus {
1938 <4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1941 spdif_bus_1: spdif-bus-1 {
1943 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
1948 spi0_clk: spi0-clk {
1950 <3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>;
1952 spi0_cs0: spi0-cs0 {
1954 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>;
1956 spi0_cs1: spi0-cs1 {
1958 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>;
1962 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>;
1966 <3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>;
1971 spi1_clk: spi1-clk {
1973 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>;
1975 spi1_cs0: spi1-cs0 {
1977 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>;
1981 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>;
1985 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>;
1990 spi2_clk: spi2-clk {
1992 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
1994 spi2_cs0: spi2-cs0 {
1996 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>;
2000 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>;
2004 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>;
2009 spi3_clk: spi3-clk {
2011 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>;
2013 spi3_cs0: spi3-cs0 {
2015 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>;
2019 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>;
2023 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>;
2028 spi4_clk: spi4-clk {
2030 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>;
2032 spi4_cs0: spi4-cs0 {
2034 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>;
2038 <3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>;
2042 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>;
2047 spi5_clk: spi5-clk {
2049 <2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>;
2051 spi5_cs0: spi5-cs0 {
2053 <2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
2057 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>;
2061 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>;
2066 otp_gpio: otp-gpio {
2067 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2071 rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
2076 uart0_xfer: uart0-xfer {
2078 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>,
2079 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
2082 uart0_cts: uart0-cts {
2084 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
2087 uart0_rts: uart0-rts {
2089 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
2094 uart1_xfer: uart1-xfer {
2096 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>,
2097 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>;
2102 uart2a_xfer: uart2a-xfer {
2104 <4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>,
2105 <4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
2110 uart2b_xfer: uart2b-xfer {
2112 <4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>,
2113 <4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>;
2118 uart2c_xfer: uart2c-xfer {
2120 <4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>,
2121 <4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
2126 uart3_xfer: uart3-xfer {
2128 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>,
2129 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>;
2132 uart3_cts: uart3-cts {
2134 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
2137 uart3_rts: uart3-rts {
2139 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
2144 uart4_xfer: uart4-xfer {
2146 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>,
2147 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
2152 uarthdcp_xfer: uarthdcp-xfer {
2154 <4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>,
2155 <4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
2160 pwm0_pin: pwm0-pin {
2162 <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
2165 vop0_pwm_pin: vop0-pwm-pin {
2167 <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
2172 pwm1_pin: pwm1-pin {
2174 <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
2177 vop1_pwm_pin: vop1-pwm-pin {
2179 <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
2184 pwm2_pin: pwm2-pin {
2186 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
2191 pwm3a_pin: pwm3a-pin {
2193 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
2198 pwm3b_pin: pwm3b-pin {
2200 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
2205 hdmi_i2c_xfer: hdmi-i2c-xfer {
2207 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2208 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2211 hdmi_cec: hdmi-cec {
2213 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2218 pcie_clkreqn: pci-clkreqn {
2220 <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>;
2223 pcie_clkreqnb: pci-clkreqnb {
2225 <4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
2228 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2230 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2233 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2235 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;