arch/arm/dts/rk3328.dtsi

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <dt-bindings/clock/rk3328-cru.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/pinctrl/rockchip.h>
  12
  13 / {
  14         compatible = "rockchip,rk3328";
  15
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 serial0 = &uart0;
  22                 serial1 = &uart1;
  23                 serial2 = &uart2;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <2>;
  32                 #size-cells = <0>;
  33
  34                 cpu0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a53", "arm,armv8";
  37                         reg = <0x0 0x0>;
  38                         enable-method = "psci";
  39 //                      clocks = <&cru ARMCLK>;
  40                         operating-points-v2 = <&cpu0_opp_table>;
  41                 };
  42                 cpu1: cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a53", "arm,armv8";
  45                         reg = <0x0 0x1>;
  46                         enable-method = "psci";
  47                 };
  48                 cpu2: cpu@2 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a53", "arm,armv8";
  51                         reg = <0x0 0x2>;
  52                         enable-method = "psci";
  53                 };
  54                 cpu3: cpu@3 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a53", "arm,armv8";
  57                         reg = <0x0 0x3>;
  58                         enable-method = "psci";
  59                 };
  60         };
  61
  62         cpu0_opp_table: opp_table0 {
  63                 compatible = "operating-points-v2";
  64                 opp-shared;
  65
  66                 opp@408000000 {
  67                         opp-hz = /bits/ 64 <408000000>;
  68                         opp-microvolt = <950000>;
  69                         clock-latency-ns = <40000>;
  70                         opp-suspend;
  71                 };
  72                 opp@600000000 {
  73                         opp-hz = /bits/ 64 <600000000>;
  74                         opp-microvolt = <950000>;
  75                         clock-latency-ns = <40000>;
  76                 };
  77                 opp@816000000 {
  78                         opp-hz = /bits/ 64 <816000000>;
  79                         opp-microvolt = <1000000>;
  80                         clock-latency-ns = <40000>;
  81                 };
  82                 opp@1008000000 {
  83                         opp-hz = /bits/ 64 <1008000000>;
  84                         opp-microvolt = <1100000>;
  85                         clock-latency-ns = <40000>;
  86                 };
  87                 opp@1200000000 {
  88                         opp-hz = /bits/ 64 <1200000000>;
  89                         opp-microvolt = <1225000>;
  90                         clock-latency-ns = <40000>;
  91                 };
  92                 opp@1296000000 {
  93                         opp-hz = /bits/ 64 <1296000000>;
  94                         opp-microvolt = <1300000>;
  95                         clock-latency-ns = <40000>;
  96                 };
  97         };
  98
  99         arm-pmu {
 100                 compatible = "arm,cortex-a53-pmu";
 101                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 102                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 103                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 104                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 105                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 106         };
 107
 108         psci {
 109                 compatible = "arm,psci-1.0";
 110                 method = "smc";
 111         };
 112
 113         timer {
 114                 compatible = "arm,armv8-timer";
 115                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 116                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 117                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 118                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 119         };
 120
 121         xin24m: xin24m {
 122                 compatible = "fixed-clock";
 123                 #clock-cells = <0>;
 124                 clock-frequency = <24000000>;
 125                 clock-output-names = "xin24m";
 126         };
 127
 128         i2s0: i2s@ff000000 {
 129                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 130                 reg = <0x0 0xff000000 0x0 0x1000>;
 131                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 132                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 133                 clock-names = "i2s_clk", "i2s_hclk";
 134                 dmas = <&dmac 11>, <&dmac 12>;
 135                 #dma-cells = <2>;
 136                 dma-names = "tx", "rx";
 137                 status = "disabled";
 138         };
 139
 140         i2s1: i2s@ff010000 {
 141                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 142                 reg = <0x0 0xff010000 0x0 0x1000>;
 143                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 144                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 145                 clock-names = "i2s_clk", "i2s_hclk";
 146                 dmas = <&dmac 14>, <&dmac 15>;
 147                 #dma-cells = <2>;
 148                 dma-names = "tx", "rx";
 149                 status = "disabled";
 150         };
 151
 152         i2s2: i2s@ff020000 {
 153                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 154                 reg = <0x0 0xff020000 0x0 0x1000>;
 155                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 156                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 157                 clock-names = "i2s_clk", "i2s_hclk";
 158                 dmas = <&dmac 0>, <&dmac 1>;
 159                 #dma-cells = <2>;
 160                 dma-names = "tx", "rx";
 161                 pinctrl-names = "default", "sleep";
 162                 pinctrl-0 = <&i2s2m0_mclk
 163                              &i2s2m0_sclk
 164                              &i2s2m0_lrcktx
 165                              &i2s2m0_lrckrx
 166                              &i2s2m0_sdo
 167                              &i2s2m0_sdi>;
 168                 pinctrl-1 = <&i2s2m0_sleep>;
 169                 status = "disabled";
 170         };
 171
 172         spdif: spdif@ff030000 {
 173                 compatible = "rockchip,rk3328-spdif";
 174                 reg = <0x0 0xff030000 0x0 0x1000>;
 175                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 177                 clock-names = "mclk", "hclk";
 178                 dmas = <&dmac 10>;
 179                 #dma-cells = <1>;
 180                 dma-names = "tx";
 181                 pinctrl-names = "default";
 182                 pinctrl-0 = <&spdifm2_tx>;
 183                 status = "disabled";
 184         };
 185
 186         grf: syscon@ff100000 {
 187                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 188                 reg = <0x0 0xff100000 0x0 0x1000>;
 189                 #address-cells = <1>;
 190                 #size-cells = <1>;
 191
 192                 io_domains: io-domains {
 193                         compatible = "rockchip,rk3328-io-voltage-domain";
 194                         status = "disabled";
 195                 };
 196         };
 197
 198         uart0: serial@ff110000 {
 199                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 200                 reg = <0x0 0xff110000 0x0 0x100>;
 201                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 202                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 203                 clock-names = "baudclk", "apb_pclk";
 204                 reg-shift = <2>;
 205                 reg-io-width = <4>;
 206                 dmas = <&dmac 2>, <&dmac 3>;
 207                 #dma-cells = <2>;
 208                 pinctrl-names = "default";
 209                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 210                 status = "disabled";
 211         };
 212
 213         uart1: serial@ff120000 {
 214                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 215                 reg = <0x0 0xff120000 0x0 0x100>;
 216                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 217                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 218                 clock-names = "sclk_uart", "pclk_uart";
 219                 reg-shift = <2>;
 220                 reg-io-width = <4>;
 221                 dmas = <&dmac 4>, <&dmac 5>;
 222                 #dma-cells = <2>;
 223                 pinctrl-names = "default";
 224                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 225                 status = "disabled";
 226         };
 227
 228         uart2: serial@ff130000 {
 229                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 230                 reg = <0x0 0xff130000 0x0 0x100>;
 231                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 232                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 233                 clock-names = "baudclk", "apb_pclk";
 234                 clock-frequency = <24000000>;
 235                 reg-shift = <2>;
 236                 reg-io-width = <4>;
 237                 dmas = <&dmac 6>, <&dmac 7>;
 238                 #dma-cells = <2>;
 239                 pinctrl-names = "default";
 240                 pinctrl-0 = <&uart2m1_xfer>;
 241                 status = "disabled";
 242         };
 243
 244         pmu: power-management@ff140000 {
 245                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 246                 reg = <0x0 0xff140000 0x0 0x1000>;
 247         };
 248
 249         i2c0: i2c@ff150000 {
 250                 compatible = "rockchip,rk3328-i2c";
 251                 reg = <0x0 0xff150000 0x0 0x1000>;
 252                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 253                 #address-cells = <1>;
 254                 #size-cells = <0>;
 255                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 256                 clock-names = "i2c", "pclk";
 257                 pinctrl-names = "default";
 258                 pinctrl-0 = <&i2c0_xfer>;
 259                 status = "disabled";
 260         };
 261
 262         i2c1: i2c@ff160000 {
 263                 compatible = "rockchip,rk3328-i2c";
 264                 reg = <0x0 0xff160000 0x0 0x1000>;
 265                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 266                 #address-cells = <1>;
 267                 #size-cells = <0>;
 268                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 269                 clock-names = "i2c", "pclk";
 270                 pinctrl-names = "default";
 271                 pinctrl-0 = <&i2c1_xfer>;
 272                 status = "disabled";
 273         };
 274
 275         i2c2: i2c@ff170000 {
 276                 compatible = "rockchip,rk3328-i2c";
 277                 reg = <0x0 0xff170000 0x0 0x1000>;
 278                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 279                 #address-cells = <1>;
 280                 #size-cells = <0>;
 281                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 282                 clock-names = "i2c", "pclk";
 283                 pinctrl-names = "default";
 284                 pinctrl-0 = <&i2c2_xfer>;
 285                 status = "disabled";
 286         };
 287
 288         i2c3: i2c@ff180000 {
 289                 compatible = "rockchip,rk3328-i2c";
 290                 reg = <0x0 0xff180000 0x0 0x1000>;
 291                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 295                 clock-names = "i2c", "pclk";
 296                 pinctrl-names = "default";
 297                 pinctrl-0 = <&i2c3_xfer>;
 298                 status = "disabled";
 299         };
 300
 301         spi0: spi@ff190000 {
 302                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 303                 reg = <0x0 0xff190000 0x0 0x1000>;
 304                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 305                 #address-cells = <1>;
 306                 #size-cells = <0>;
 307                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 308                 clock-names = "spiclk", "apb_pclk";
 309                 dmas = <&dmac 8>, <&dmac 9>;
 310                 #dma-cells = <2>;
 311                 dma-names = "tx", "rx";
 312                 pinctrl-names = "default";
 313                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 314                 status = "disabled";
 315         };
 316
 317         wdt: watchdog@ff1a0000 {
 318                 compatible = "snps,dw-wdt";
 319                 reg = <0x0 0xff1a0000 0x0 0x100>;
 320                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 321                 status = "disabled";
 322         };
 323
 324         amba {
 325                 compatible = "simple-bus";
 326                 #address-cells = <2>;
 327                 #size-cells = <2>;
 328                 ranges;
 329
 330                 dmac: dmac@ff1f0000 {
 331                         compatible = "arm,pl330", "arm,primecell";
 332                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 333                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 334                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 335                         clocks = <&cru ACLK_DMAC>;
 336                         clock-names = "apb_pclk";
 337                         #dma-cells = <1>;
 338                 };
 339         };
 340
 341         saradc: saradc@ff280000 {
 342                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 343                 reg = <0x0 0xff280000 0x0 0x100>;
 344                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 345                 #io-channel-cells = <1>;
 346                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 347                 clock-names = "saradc", "apb_pclk";
 348                 resets = <&cru SRST_SARADC_P>;
 349                 reset-names = "saradc-apb";
 350                 status = "disabled";
 351         };
 352
 353         cru: clock-controller@ff440000 {
 354                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 355                 reg = <0x0 0xff440000 0x0 0x1000>;
 356                 rockchip,grf = <&grf>;
 357                 #clock-cells = <1>;
 358                 #reset-cells = <1>;
 359                 assigned-clocks =
 360                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 361                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 362                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 363                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 364                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 365                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 366                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 367                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 368                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 369                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 370                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 371                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 372                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 373                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 374                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 375                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 376                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 377                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 378                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 379                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 380                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 381                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 382                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 383                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 384                 assigned-clock-parents =
 385                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 386                         <&cru PLL_GPLL>, <&xin24m>,
 387                         <&xin24m>, <&xin24m>;
 388                 assigned-clock-rates =
 389                         <0>, <61440000>,
 390                         <0>, <24000000>,
 391                         <24000000>, <24000000>,
 392                         <15000000>, <15000000>,
 393                         <100000000>, <100000000>,
 394                         <100000000>, <100000000>,
 395                         <50000000>, <100000000>,
 396                         <100000000>, <100000000>,
 397                         <50000000>, <50000000>,
 398                         <50000000>, <50000000>,
 399                         <24000000>, <600000000>,
 400                         <491520000>, <1200000000>,
 401                         <150000000>, <75000000>,
 402                         <75000000>, <150000000>,
 403                         <75000000>, <75000000>,
 404                         <300000000>, <100000000>,
 405                         <300000000>, <200000000>,
 406                         <400000000>, <500000000>,
 407                         <200000000>, <300000000>,
 408                         <300000000>, <250000000>,
 409                         <200000000>, <100000000>,
 410                         <24000000>, <100000000>,
 411                         <150000000>, <50000000>,
 412                         <32768>, <32768>;
 413         };
 414
 415         sdmmc: rksdmmc@ff500000 {
 416                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 417                 reg = <0x0 0xff500000 0x0 0x4000>;
 418                 clock-freq-min-max = <400000 150000000>;
 419                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 420                 clock-names = "biu", "ciu";
 421                 fifo-depth = <0x100>;
 422                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 423                 status = "disabled";
 424         };
 425
 426         sdio: dwmmc@ff510000 {
 427                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 428                 reg = <0x0 0xff510000 0x0 0x4000>;
 429                 clock-freq-min-max = <400000 150000000>;
 430                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 431                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 432                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 433                 fifo-depth = <0x100>;
 434                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 435                 status = "disabled";
 436         };
 437
 438         emmc: rksdmmc@ff520000 {
 439                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 440                 reg = <0x0 0xff520000 0x0 0x4000>;
 441                 clock-freq-min-max = <400000 150000000>;
 442                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 443                 clock-names = "biu", "ciu";
 444                 fifo-depth = <0x100>;
 445                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 446                 status = "disabled";
 447         };
 448
 449         usb_host0_ehci: usb@ff5c0000 {
 450                 compatible = "generic-ehci";
 451                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 452                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 453                 status = "disabled";
 454         };
 455
 456         usb_host0_ohci: usb@ff5d0000 {
 457                 compatible = "generic-ohci";
 458                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 459                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 460                 status = "disabled";
 461         };
 462
 463         sdmmc_ext: rksdmmc@ff5f0000 {
 464                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 465                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 466                 clock-freq-min-max = <400000 150000000>;
 467                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 468                 clock-names = "biu", "ciu";
 469                 fifo-depth = <0x100>;
 470                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 471                 status = "disabled";
 472         };
 473
 474         gic: interrupt-controller@ffb70000 {
 475                 compatible = "arm,gic-400";
 476                 #interrupt-cells = <3>;
 477                 #address-cells = <0>;
 478                 interrupt-controller;
 479                 reg = <0x0 0xff811000 0 0x1000>,
 480                       <0x0 0xff812000 0 0x2000>,
 481                       <0x0 0xff814000 0 0x2000>,
 482                       <0x0 0xff816000 0 0x2000>;
 483                 interrupts = <GIC_PPI 9
 484                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 485         };
 486
 487         pinctrl: pinctrl {
 488                 compatible = "rockchip,rk3328-pinctrl";
 489                 rockchip,grf = <&grf>;
 490                 #address-cells = <2>;
 491                 #size-cells = <2>;
 492                 ranges;
 493
 494                 gpio0: gpio0@ff210000 {
 495                         compatible = "rockchip,gpio-bank";
 496                         reg = <0x0 0xff210000 0x0 0x100>;
 497                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 498                         clocks = <&cru PCLK_GPIO0>;
 499
 500                         gpio-controller;
 501                         #gpio-cells = <2>;
 502
 503                         interrupt-controller;
 504                         #interrupt-cells = <2>;
 505                 };
 506
 507                 gpio1: gpio1@ff220000 {
 508                         compatible = "rockchip,gpio-bank";
 509                         reg = <0x0 0xff220000 0x0 0x100>;
 510                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 511                         clocks = <&cru PCLK_GPIO1>;
 512
 513                         gpio-controller;
 514                         #gpio-cells = <2>;
 515
 516                         interrupt-controller;
 517                         #interrupt-cells = <2>;
 518                 };
 519
 520                 gpio2: gpio2@ff230000 {
 521                         compatible = "rockchip,gpio-bank";
 522                         reg = <0x0 0xff230000 0x0 0x100>;
 523                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 524                         clocks = <&cru PCLK_GPIO2>;
 525
 526                         gpio-controller;
 527                         #gpio-cells = <2>;
 528
 529                         interrupt-controller;
 530                         #interrupt-cells = <2>;
 531                 };
 532
 533                 gpio3: gpio3@ff240000 {
 534                         compatible = "rockchip,gpio-bank";
 535                         reg = <0x0 0xff240000 0x0 0x100>;
 536                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 537                         clocks = <&cru PCLK_GPIO3>;
 538
 539                         gpio-controller;
 540                         #gpio-cells = <2>;
 541
 542                         interrupt-controller;
 543                         #interrupt-cells = <2>;
 544                 };
 545
 546                 pcfg_pull_up: pcfg-pull-up {
 547                         bias-pull-up;
 548                 };
 549
 550                 pcfg_pull_down: pcfg-pull-down {
 551                         bias-pull-down;
 552                 };
 553
 554                 pcfg_pull_none: pcfg-pull-none {
 555                         bias-disable;
 556                 };
 557
 558                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 559                         bias-disable;
 560                         drive-strength = <2>;
 561                 };
 562
 563                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 564                         bias-pull-up;
 565                         drive-strength = <2>;
 566                 };
 567
 568                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 569                         bias-pull-up;
 570                         drive-strength = <4>;
 571                 };
 572
 573                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 574                         bias-disable;
 575                         drive-strength = <4>;
 576                 };
 577
 578                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 579                         bias-pull-down;
 580                         drive-strength = <4>;
 581                 };
 582
 583                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 584                         bias-disable;
 585                         drive-strength = <8>;
 586                 };
 587
 588                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 589                         bias-pull-up;
 590                         drive-strength = <8>;
 591                 };
 592
 593                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 594                         bias-disable;
 595                         drive-strength = <12>;
 596                 };
 597
 598                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 599                         bias-pull-up;
 600                         drive-strength = <12>;
 601                 };
 602
 603                 pcfg_output_high: pcfg-output-high {
 604                         output-high;
 605                 };
 606
 607                 pcfg_output_low: pcfg-output-low {
 608                         output-low;
 609                 };
 610
 611                 pcfg_input_high: pcfg-input-high {
 612                         bias-pull-up;
 613                         input-enable;
 614                 };
 615
 616                 pcfg_input: pcfg-input {
 617                         input-enable;
 618                 };
 619
 620                 i2c0 {
 621                         i2c0_xfer: i2c0-xfer {
 622                                 rockchip,pins =
 623                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 624                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 625                         };
 626                 };
 627
 628                 i2c1 {
 629                         i2c1_xfer: i2c1-xfer {
 630                                 rockchip,pins =
 631                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 632                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 633                         };
 634                 };
 635
 636                 i2c2 {
 637                         i2c2_xfer: i2c2-xfer {
 638                                 rockchip,pins =
 639                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 640                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 641                         };
 642                 };
 643
 644                 i2c3 {
 645                         i2c3_xfer: i2c3-xfer {
 646                                 rockchip,pins =
 647                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 648                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 649                         };
 650                         i2c3_gpio: i2c3-gpio {
 651                                 rockchip,pins =
 652                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 653                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 654                         };
 655                 };
 656
 657                 hdmi_i2c {
 658                         hdmii2c_xfer: hdmii2c-xfer {
 659                                 rockchip,pins =
 660                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 661                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 662                         };
 663                 };
 664
 665                 uart0 {
 666                         uart0_xfer: uart0-xfer {
 667                                 rockchip,pins =
 668                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
 669                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 670                         };
 671
 672                         uart0_cts: uart0-cts {
 673                                 rockchip,pins =
 674                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 675                         };
 676
 677                         uart0_rts: uart0-rts {
 678                                 rockchip,pins =
 679                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
 680                         };
 681
 682                         uart0_rts_gpio: uart0-rts-gpio {
 683                                 rockchip,pins =
 684                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
 685                         };
 686                 };
 687
 688                 uart1 {
 689                         uart1_xfer: uart1-xfer {
 690                                 rockchip,pins =
 691                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
 692                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
 693                         };
 694
 695                         uart1_cts: uart1-cts {
 696                                 rockchip,pins =
 697                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
 698                         };
 699
 700                         uart1_rts: uart1-rts {
 701                                 rockchip,pins =
 702                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
 703                         };
 704
 705                         uart1_rts_gpio: uart1-rts-gpio {
 706                                 rockchip,pins =
 707                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
 708                         };
 709                 };
 710
 711                 uart2-0 {
 712                         uart2m0_xfer: uart2m0-xfer {
 713                                 rockchip,pins =
 714                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
 715                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
 716                         };
 717                 };
 718
 719                 uart2-1 {
 720                         uart2m1_xfer: uart2m1-xfer {
 721                                 rockchip,pins =
 722                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
 723                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
 724                         };
 725                 };
 726
 727                 spi0-0 {
 728                         spi0m0_clk: spi0m0-clk {
 729                                 rockchip,pins =
 730                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
 731                         };
 732
 733                         spi0m0_cs0: spi0m0-cs0 {
 734                                 rockchip,pins =
 735                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 736                         };
 737
 738                         spi0m0_tx: spi0m0-tx {
 739                                 rockchip,pins =
 740                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 741                         };
 742
 743                         spi0m0_rx: spi0m0-rx {
 744                                 rockchip,pins =
 745                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 746                         };
 747
 748                         spi0m0_cs1: spi0m0-cs1 {
 749                                 rockchip,pins =
 750                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 751                         };
 752                 };
 753
 754                 spi0-1 {
 755                         spi0m1_clk: spi0m1-clk {
 756                                 rockchip,pins =
 757                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
 758                         };
 759
 760                         spi0m1_cs0: spi0m1-cs0 {
 761                                 rockchip,pins =
 762                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
 763                         };
 764
 765                         spi0m1_tx: spi0m1-tx {
 766                                 rockchip,pins =
 767                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
 768                         };
 769
 770                         spi0m1_rx: spi0m1-rx {
 771                                 rockchip,pins =
 772                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
 773                         };
 774
 775                         spi0m1_cs1: spi0m1-cs1 {
 776                                 rockchip,pins =
 777                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
 778                         };
 779                 };
 780
 781                 spi0-2 {
 782                         spi0m2_clk: spi0m2-clk {
 783                                 rockchip,pins =
 784                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
 785                         };
 786
 787                         spi0m2_cs0: spi0m2-cs0 {
 788                                 rockchip,pins =
 789                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
 790                         };
 791
 792                         spi0m2_tx: spi0m2-tx {
 793                                 rockchip,pins =
 794                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
 795                         };
 796
 797                         spi0m2_rx: spi0m2-rx {
 798                                 rockchip,pins =
 799                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
 800                         };
 801                 };
 802
 803                 i2s1 {
 804                         i2s1_mclk: i2s1-mclk {
 805                                 rockchip,pins =
 806                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
 807                         };
 808
 809                         i2s1_sclk: i2s1-sclk {
 810                                 rockchip,pins =
 811                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
 812                         };
 813
 814                         i2s1_lrckrx: i2s1-lrckrx {
 815                                 rockchip,pins =
 816                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
 817                         };
 818
 819                         i2s1_lrcktx: i2s1-lrcktx {
 820                                 rockchip,pins =
 821                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
 822                         };
 823
 824                         i2s1_sdi: i2s1-sdi {
 825                                 rockchip,pins =
 826                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
 827                         };
 828
 829                         i2s1_sdo: i2s1-sdo {
 830                                 rockchip,pins =
 831                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
 832                         };
 833
 834                         i2s1_sdio1: i2s1-sdio1 {
 835                                 rockchip,pins =
 836                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
 837                         };
 838
 839                         i2s1_sdio2: i2s1-sdio2 {
 840                                 rockchip,pins =
 841                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
 842                         };
 843
 844                         i2s1_sdio3: i2s1-sdio3 {
 845                                 rockchip,pins =
 846                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
 847                         };
 848
 849                         i2s1_sleep: i2s1-sleep {
 850                                 rockchip,pins =
 851                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
 852                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
 853                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
 854                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
 855                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
 856                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
 857                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
 858                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
 859                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
 860                         };
 861                 };
 862
 863                 i2s2-0 {
 864                         i2s2m0_mclk: i2s2m0-mclk {
 865                                 rockchip,pins =
 866                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 867                         };
 868
 869                         i2s2m0_sclk: i2s2m0-sclk {
 870                                 rockchip,pins =
 871                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
 872                         };
 873
 874                         i2s2m0_lrckrx: i2s2m0-lrckrx {
 875                                 rockchip,pins =
 876                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
 877                         };
 878
 879                         i2s2m0_lrcktx: i2s2m0-lrcktx {
 880                                 rockchip,pins =
 881                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
 882                         };
 883
 884                         i2s2m0_sdi: i2s2m0-sdi {
 885                                 rockchip,pins =
 886                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
 887                         };
 888
 889                         i2s2m0_sdo: i2s2m0-sdo {
 890                                 rockchip,pins =
 891                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
 892                         };
 893
 894                         i2s2m0_sleep: i2s2m0-sleep {
 895                                 rockchip,pins =
 896                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
 897                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
 898                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
 899                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
 900                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
 901                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
 902                         };
 903                 };
 904
 905                 i2s2-1 {
 906                         i2s2m1_mclk: i2s2m1-mclk {
 907                                 rockchip,pins =
 908                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 909                         };
 910
 911                         i2s2m1_sclk: i2s2m1-sclk {
 912                                 rockchip,pins =
 913                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
 914                         };
 915
 916                         i2s2m1_lrckrx: i2sm1-lrckrx {
 917                                 rockchip,pins =
 918                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
 919                         };
 920
 921                         i2s2m1_lrcktx: i2s2m1-lrcktx {
 922                                 rockchip,pins =
 923                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
 924                         };
 925
 926                         i2s2m1_sdi: i2s2m1-sdi {
 927                                 rockchip,pins =
 928                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
 929                         };
 930
 931                         i2s2m1_sdo: i2s2m1-sdo {
 932                                 rockchip,pins =
 933                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
 934                         };
 935
 936                         i2s2m1_sleep: i2s2m1-sleep {
 937                                 rockchip,pins =
 938                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
 939                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
 940                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
 941                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
 942                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
 943                         };
 944                 };
 945
 946                 spdif-0 {
 947                         spdifm0_tx: spdifm0-tx {
 948                                 rockchip,pins =
 949                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
 950                         };
 951                 };
 952
 953                 spdif-1 {
 954                         spdifm1_tx: spdifm1-tx {
 955                                 rockchip,pins =
 956                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
 957                         };
 958                 };
 959
 960                 spdif-2 {
 961                         spdifm2_tx: spdifm2-tx {
 962                                 rockchip,pins =
 963                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
 964                         };
 965                 };
 966
 967                 sdmmc0-0 {
 968                         sdmmc0m0_pwren: sdmmc0m0-pwren {
 969                                 rockchip,pins =
 970                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
 971                         };
 972
 973                         sdmmc0m0_gpio: sdmmc0m0-gpio {
 974                                 rockchip,pins =
 975                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
 976                         };
 977                 };
 978
 979                 sdmmc0-1 {
 980                         sdmmc0m1_pwren: sdmmc0m1-pwren {
 981                                 rockchip,pins =
 982                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
 983                         };
 984
 985                         sdmmc0m1_gpio: sdmmc0m1-gpio {
 986                                 rockchip,pins =
 987                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
 988                         };
 989                 };
 990
 991                 sdmmc0 {
 992                         sdmmc0_clk: sdmmc0-clk {
 993                                 rockchip,pins =
 994                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
 995                         };
 996
 997                         sdmmc0_cmd: sdmmc0-cmd {
 998                                 rockchip,pins =
 999                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1000                         };
1001
1002                         sdmmc0_dectn: sdmmc0-dectn {
1003                                 rockchip,pins =
1004                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1005                         };
1006
1007                         sdmmc0_wrprt: sdmmc0-wrprt {
1008                                 rockchip,pins =
1009                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1010                         };
1011
1012                         sdmmc0_bus1: sdmmc0-bus1 {
1013                                 rockchip,pins =
1014                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1015                         };
1016
1017                         sdmmc0_bus4: sdmmc0-bus4 {
1018                                 rockchip,pins =
1019                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1020                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1021                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1022                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1023                         };
1024
1025                         sdmmc0_gpio: sdmmc0-gpio {
1026                                 rockchip,pins =
1027                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1028                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1029                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1030                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1031                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1032                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1033                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1034                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1035                         };
1036                 };
1037
1038                 sdmmc0ext {
1039                         sdmmc0ext_clk: sdmmc0ext-clk {
1040                                 rockchip,pins =
1041                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1042                         };
1043
1044                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1045                                 rockchip,pins =
1046                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1047                         };
1048
1049                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1050                                 rockchip,pins =
1051                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1052                         };
1053
1054                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1055                                 rockchip,pins =
1056                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1057                         };
1058
1059                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1060                                 rockchip,pins =
1061                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1062                         };
1063
1064                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1065                                 rockchip,pins =
1066                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1067                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1068                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1069                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1070                         };
1071
1072                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1073                                 rockchip,pins =
1074                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1075                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1076                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1077                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1078                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1079                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1080                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1081                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1082                         };
1083                 };
1084
1085                 sdmmc1 {
1086                         sdmmc1_clk: sdmmc1-clk {
1087                                 rockchip,pins =
1088                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1089                         };
1090
1091                         sdmmc1_cmd: sdmmc1-cmd {
1092                                 rockchip,pins =
1093                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1094                         };
1095
1096                         sdmmc1_pwren: sdmmc1-pwren {
1097                                 rockchip,pins =
1098                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1099                         };
1100
1101                         sdmmc1_wrprt: sdmmc1-wrprt {
1102                                 rockchip,pins =
1103                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1104                         };
1105
1106                         sdmmc1_dectn: sdmmc1-dectn {
1107                                 rockchip,pins =
1108                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1109                         };
1110
1111                         sdmmc1_bus1: sdmmc1-bus1 {
1112                                 rockchip,pins =
1113                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1114                         };
1115
1116                         sdmmc1_bus4: sdmmc1-bus4 {
1117                                 rockchip,pins =
1118                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1119                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1120                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1121                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1122                         };
1123
1124                         sdmmc1_gpio: sdmmc1-gpio {
1125                                 rockchip,pins =
1126                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1127                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1128                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1129                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1130                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1131                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1132                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1133                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1134                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1135                         };
1136                 };
1137
1138                 emmc {
1139                         emmc_clk: emmc-clk {
1140                                 rockchip,pins =
1141                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1142                         };
1143
1144                         emmc_cmd: emmc-cmd {
1145                                 rockchip,pins =
1146                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1147                         };
1148
1149                         emmc_pwren: emmc-pwren {
1150                                 rockchip,pins =
1151                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1152                         };
1153
1154                         emmc_rstnout: emmc-rstnout {
1155                                 rockchip,pins =
1156                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1157                         };
1158
1159                         emmc_bus1: emmc-bus1 {
1160                                 rockchip,pins =
1161                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1162                         };
1163
1164                         emmc_bus4: emmc-bus4 {
1165                                 rockchip,pins =
1166                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1167                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1168                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1169                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1170                         };
1171
1172                         emmc_bus8: emmc-bus8 {
1173                                 rockchip,pins =
1174                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1175                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1176                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1177                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1178                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1179                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1180                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1181                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1182                         };
1183                 };
1184
1185                 pwm0 {
1186                         pwm0_pin: pwm0-pin {
1187                                 rockchip,pins =
1188                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1189                         };
1190                 };
1191
1192                 pwm1 {
1193                         pwm1_pin: pwm1-pin {
1194                                 rockchip,pins =
1195                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1196                         };
1197                 };
1198
1199                 pwm2 {
1200                         pwm2_pin: pwm2-pin {
1201                                 rockchip,pins =
1202                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1203                         };
1204                 };
1205
1206                 pwmir {
1207                         pwmir_pin: pwmir-pin {
1208                                 rockchip,pins =
1209                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1210                         };
1211                 };
1212
1213                 gmac-0 {
1214                         rgmiim0_pins: rgmiim0-pins {
1215                                 rockchip,pins =
1216                                         /* mac_txclk */
1217                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1218                                         /* mac_rxclk */
1219                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1220                                         /* mac_mdio */
1221                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1222                                         /* mac_txen */
1223                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1224                                         /* mac_clk */
1225                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1226                                         /* mac_rxdv */
1227                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1228                                         /* mac_mdc */
1229                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1230                                         /* mac_rxd1 */
1231                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1232                                         /* mac_rxd0 */
1233                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1234                                         /* mac_txd1 */
1235                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1236                                         /* mac_txd0 */
1237                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1238                                         /* mac_rxd3 */
1239                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1240                                         /* mac_rxd2 */
1241                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1242                                         /* mac_txd3 */
1243                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1244                                         /* mac_txd2 */
1245                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1246                         };
1247
1248                         rmiim0_pins: rmiim0-pins {
1249                                 rockchip,pins =
1250                                         /* mac_mdio */
1251                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1252                                         /* mac_txen */
1253                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1254                                         /* mac_clk */
1255                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1256                                         /* mac_rxer */
1257                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1258                                         /* mac_rxdv */
1259                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1260                                         /* mac_mdc */
1261                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1262                                         /* mac_rxd1 */
1263                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1264                                         /* mac_rxd0 */
1265                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1266                                         /* mac_txd1 */
1267                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1268                                         /* mac_txd0 */
1269                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1270                         };
1271                 };
1272
1273                 gmac-1 {
1274                         rgmiim1_pins: rgmiim1-pins {
1275                                 rockchip,pins =
1276                                         /* mac_txclk */
1277                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1278                                         /* mac_rxclk */
1279                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1280                                         /* mac_mdio */
1281                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1282                                         /* mac_txen */
1283                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1284                                         /* mac_clk */
1285                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1286                                         /* mac_rxdv */
1287                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1288                                         /* mac_mdc */
1289                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1290                                         /* mac_rxd1 */
1291                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1292                                         /* mac_rxd0 */
1293                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1294                                         /* mac_txd1 */
1295                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1296                                         /* mac_txd0 */
1297                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1298                                         /* mac_rxd3 */
1299                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1300                                         /* mac_rxd2 */
1301                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1302                                         /* mac_txd3 */
1303                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1304                                         /* mac_txd2 */
1305                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1306
1307                                         /* mac_txclk */
1308                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1309                                         /* mac_txen */
1310                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1311                                         /* mac_clk */
1312                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1313                                         /* mac_txd1 */
1314                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1315                                         /* mac_txd0 */
1316                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1317                                         /* mac_txd3 */
1318                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1319                                         /* mac_txd2 */
1320                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1321                         };
1322
1323                         rmiim1_pins: rmiim1-pins {
1324                                 rockchip,pins =
1325                                         /* mac_mdio */
1326                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1327                                         /* mac_txen */
1328                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1329                                         /* mac_clk */
1330                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1331                                         /* mac_rxer */
1332                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1333                                         /* mac_rxdv */
1334                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1335                                         /* mac_mdc */
1336                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1337                                         /* mac_rxd1 */
1338                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1339                                         /* mac_rxd0 */
1340                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1341                                         /* mac_txd1 */
1342                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1343                                         /* mac_txd0 */
1344                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1345
1346                                         /* mac_mdio */
1347                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1348                                         /* mac_txen */
1349                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1350                                         /* mac_clk */
1351                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1352                                         /* mac_mdc */
1353                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1354                                         /* mac_txd1 */
1355                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1356                                         /* mac_txd0 */
1357                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1358                         };
1359                 };
1360
1361                 gmac2phy {
1362                         fephyled_speed100: fephyled-speed100 {
1363                                 rockchip,pins =
1364                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1365                         };
1366
1367                         fephyled_speed10: fephyled-speed10 {
1368                                 rockchip,pins =
1369                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1370                         };
1371
1372                         fephyled_duplex: fephyled-duplex {
1373                                 rockchip,pins =
1374                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1375                         };
1376
1377                         fephyled_rxm0: fephyled-rxm0 {
1378                                 rockchip,pins =
1379                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1380                         };
1381
1382                         fephyled_txm0: fephyled-txm0 {
1383                                 rockchip,pins =
1384                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1385                         };
1386
1387                         fephyled_linkm0: fephyled-linkm0 {
1388                                 rockchip,pins =
1389                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1390                         };
1391
1392                         fephyled_rxm1: fephyled-rxm1 {
1393                                 rockchip,pins =
1394                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1395                         };
1396
1397                         fephyled_txm1: fephyled-txm1 {
1398                                 rockchip,pins =
1399                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1400                         };
1401
1402                         fephyled_linkm1: fephyled-linkm1 {
1403                                 rockchip,pins =
1404                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1405                         };
1406                 };
1407
1408                 tsadc_pin {
1409                         tsadc_int: tsadc-int {
1410                                 rockchip,pins =
1411                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1412                         };
1413                         tsadc_gpio: tsadc-gpio {
1414                                 rockchip,pins =
1415                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1416                         };
1417                 };
1418
1419                 hdmi_pin {
1420                         hdmi_cec: hdmi-cec {
1421                                 rockchip,pins =
1422                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1423                         };
1424
1425                         hdmi_hpd: hdmi-hpd {
1426                                 rockchip,pins =
1427                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1428                         };
1429                 };
1430
1431                 cif-0 {
1432                         dvp_d2d9_m0:dvp-d2d9-m0 {
1433                                 rockchip,pins =
1434                                         /* cif_d0 */
1435                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1436                                         /* cif_d1 */
1437                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1438                                         /* cif_d2 */
1439                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1440                                         /* cif_d3 */
1441                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1442                                         /* cif_d4 */
1443                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1444                                         /* cif_d5m0 */
1445                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1446                                         /* cif_d6m0 */
1447                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1448                                         /* cif_d7m0 */
1449                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1450                                         /* cif_href */
1451                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1452                                         /* cif_vsync */
1453                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1454                                         /* cif_clkoutm0 */
1455                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1456                                         /* cif_clkin */
1457                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1458                         };
1459                 };
1460
1461                 cif-1 {
1462                         dvp_d2d9_m1:dvp-d2d9-m1 {
1463                                 rockchip,pins =
1464                                         /* cif_d0 */
1465                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1466                                         /* cif_d1 */
1467                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1468                                         /* cif_d2 */
1469                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1470                                         /* cif_d3 */
1471                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1472                                         /* cif_d4 */
1473                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1474                                         /* cif_d5m1 */
1475                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1476                                         /* cif_d6m1 */
1477                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1478                                         /* cif_d7m1 */
1479                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1480                                         /* cif_href */
1481                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1482                                         /* cif_vsync */
1483                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1484                                         /* cif_clkoutm1 */
1485                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1486                                         /* cif_clkin */
1487                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1488                         };
1489                 };
1490         };
1491 };