arch/arm/dts/rk3328.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3328-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11
  12 / {
  13         compatible = "rockchip,rk3328";
  14
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 serial0 = &uart0;
  21                 serial1 = &uart1;
  22                 serial2 = &uart2;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 mmc0 = &emmc;
  28                 mmc1 = &sdmmc;
  29                 mmc2 = &sdmmc_ext;
  30         };
  31
  32         cpus {
  33                 #address-cells = <2>;
  34                 #size-cells = <0>;
  35
  36                 cpu0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a53", "arm,armv8";
  39                         reg = <0x0 0x0>;
  40                         enable-method = "psci";
  41 //                      clocks = <&cru ARMCLK>;
  42                         operating-points-v2 = <&cpu0_opp_table>;
  43                 };
  44                 cpu1: cpu@1 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a53", "arm,armv8";
  47                         reg = <0x0 0x1>;
  48                         enable-method = "psci";
  49                 };
  50                 cpu2: cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a53", "arm,armv8";
  53                         reg = <0x0 0x2>;
  54                         enable-method = "psci";
  55                 };
  56                 cpu3: cpu@3 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a53", "arm,armv8";
  59                         reg = <0x0 0x3>;
  60                         enable-method = "psci";
  61                 };
  62         };
  63
  64         cpu0_opp_table: opp_table0 {
  65                 compatible = "operating-points-v2";
  66                 opp-shared;
  67
  68                 opp@408000000 {
  69                         opp-hz = /bits/ 64 <408000000>;
  70                         opp-microvolt = <950000>;
  71                         clock-latency-ns = <40000>;
  72                         opp-suspend;
  73                 };
  74                 opp@600000000 {
  75                         opp-hz = /bits/ 64 <600000000>;
  76                         opp-microvolt = <950000>;
  77                         clock-latency-ns = <40000>;
  78                 };
  79                 opp@816000000 {
  80                         opp-hz = /bits/ 64 <816000000>;
  81                         opp-microvolt = <1000000>;
  82                         clock-latency-ns = <40000>;
  83                 };
  84                 opp@1008000000 {
  85                         opp-hz = /bits/ 64 <1008000000>;
  86                         opp-microvolt = <1100000>;
  87                         clock-latency-ns = <40000>;
  88                 };
  89                 opp@1200000000 {
  90                         opp-hz = /bits/ 64 <1200000000>;
  91                         opp-microvolt = <1225000>;
  92                         clock-latency-ns = <40000>;
  93                 };
  94                 opp@1296000000 {
  95                         opp-hz = /bits/ 64 <1296000000>;
  96                         opp-microvolt = <1300000>;
  97                         clock-latency-ns = <40000>;
  98                 };
  99         };
 100
 101         arm-pmu {
 102                 compatible = "arm,cortex-a53-pmu";
 103                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 104                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 105                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 106                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 107                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 108         };
 109
 110         psci {
 111                 compatible = "arm,psci-1.0";
 112                 method = "smc";
 113         };
 114
 115         timer {
 116                 compatible = "arm,armv8-timer";
 117                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 118                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 119                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 120                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 121         };
 122
 123         xin24m: xin24m {
 124                 compatible = "fixed-clock";
 125                 #clock-cells = <0>;
 126                 clock-frequency = <24000000>;
 127                 clock-output-names = "xin24m";
 128         };
 129
 130         i2s0: i2s@ff000000 {
 131                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 132                 reg = <0x0 0xff000000 0x0 0x1000>;
 133                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 134                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 135                 clock-names = "i2s_clk", "i2s_hclk";
 136                 dmas = <&dmac 11>, <&dmac 12>;
 137                 #dma-cells = <2>;
 138                 dma-names = "tx", "rx";
 139                 status = "disabled";
 140         };
 141
 142         i2s1: i2s@ff010000 {
 143                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 144                 reg = <0x0 0xff010000 0x0 0x1000>;
 145                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 146                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 147                 clock-names = "i2s_clk", "i2s_hclk";
 148                 dmas = <&dmac 14>, <&dmac 15>;
 149                 #dma-cells = <2>;
 150                 dma-names = "tx", "rx";
 151                 status = "disabled";
 152         };
 153
 154         i2s2: i2s@ff020000 {
 155                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 156                 reg = <0x0 0xff020000 0x0 0x1000>;
 157                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 158                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 159                 clock-names = "i2s_clk", "i2s_hclk";
 160                 dmas = <&dmac 0>, <&dmac 1>;
 161                 #dma-cells = <2>;
 162                 dma-names = "tx", "rx";
 163                 pinctrl-names = "default", "sleep";
 164                 pinctrl-0 = <&i2s2m0_mclk
 165                              &i2s2m0_sclk
 166                              &i2s2m0_lrcktx
 167                              &i2s2m0_lrckrx
 168                              &i2s2m0_sdo
 169                              &i2s2m0_sdi>;
 170                 pinctrl-1 = <&i2s2m0_sleep>;
 171                 status = "disabled";
 172         };
 173
 174         spdif: spdif@ff030000 {
 175                 compatible = "rockchip,rk3328-spdif";
 176                 reg = <0x0 0xff030000 0x0 0x1000>;
 177                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 178                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 179                 clock-names = "mclk", "hclk";
 180                 dmas = <&dmac 10>;
 181                 #dma-cells = <1>;
 182                 dma-names = "tx";
 183                 pinctrl-names = "default";
 184                 pinctrl-0 = <&spdifm2_tx>;
 185                 status = "disabled";
 186         };
 187
 188         grf: syscon@ff100000 {
 189                 u-boot,dm-pre-reloc;
 190                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 191                 reg = <0x0 0xff100000 0x0 0x1000>;
 192
 193                 io_domains: io-domains {
 194                         compatible = "rockchip,rk3328-io-voltage-domain";
 195                         status = "disabled";
 196                 };
 197         };
 198
 199         uart0: serial@ff110000 {
 200                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 201                 reg = <0x0 0xff110000 0x0 0x100>;
 202                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 203                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 204                 clock-names = "baudclk", "apb_pclk";
 205                 reg-shift = <2>;
 206                 reg-io-width = <4>;
 207                 dmas = <&dmac 2>, <&dmac 3>;
 208                 #dma-cells = <2>;
 209                 pinctrl-names = "default";
 210                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 211                 status = "disabled";
 212         };
 213
 214         uart1: serial@ff120000 {
 215                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 216                 reg = <0x0 0xff120000 0x0 0x100>;
 217                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 218                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 219                 clock-names = "sclk_uart", "pclk_uart";
 220                 reg-shift = <2>;
 221                 reg-io-width = <4>;
 222                 dmas = <&dmac 4>, <&dmac 5>;
 223                 #dma-cells = <2>;
 224                 pinctrl-names = "default";
 225                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 226                 status = "disabled";
 227         };
 228
 229         uart2: serial@ff130000 {
 230                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 231                 reg = <0x0 0xff130000 0x0 0x100>;
 232                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 234                 clock-names = "baudclk", "apb_pclk";
 235                 clock-frequency = <24000000>;
 236                 reg-shift = <2>;
 237                 reg-io-width = <4>;
 238                 dmas = <&dmac 6>, <&dmac 7>;
 239                 #dma-cells = <2>;
 240                 pinctrl-names = "default";
 241                 pinctrl-0 = <&uart2m1_xfer>;
 242                 status = "disabled";
 243         };
 244
 245         pmu: power-management@ff140000 {
 246                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 247                 reg = <0x0 0xff140000 0x0 0x1000>;
 248         };
 249
 250         i2c0: i2c@ff150000 {
 251                 compatible = "rockchip,rk3328-i2c";
 252                 reg = <0x0 0xff150000 0x0 0x1000>;
 253                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 254                 #address-cells = <1>;
 255                 #size-cells = <0>;
 256                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 257                 clock-names = "i2c", "pclk";
 258                 pinctrl-names = "default";
 259                 pinctrl-0 = <&i2c0_xfer>;
 260                 status = "disabled";
 261         };
 262
 263         i2c1: i2c@ff160000 {
 264                 compatible = "rockchip,rk3328-i2c";
 265                 reg = <0x0 0xff160000 0x0 0x1000>;
 266                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 267                 #address-cells = <1>;
 268                 #size-cells = <0>;
 269                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 270                 clock-names = "i2c", "pclk";
 271                 pinctrl-names = "default";
 272                 pinctrl-0 = <&i2c1_xfer>;
 273                 status = "disabled";
 274         };
 275
 276         i2c2: i2c@ff170000 {
 277                 compatible = "rockchip,rk3328-i2c";
 278                 reg = <0x0 0xff170000 0x0 0x1000>;
 279                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 280                 #address-cells = <1>;
 281                 #size-cells = <0>;
 282                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 283                 clock-names = "i2c", "pclk";
 284                 pinctrl-names = "default";
 285                 pinctrl-0 = <&i2c2_xfer>;
 286                 status = "disabled";
 287         };
 288
 289         i2c3: i2c@ff180000 {
 290                 compatible = "rockchip,rk3328-i2c";
 291                 reg = <0x0 0xff180000 0x0 0x1000>;
 292                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 293                 #address-cells = <1>;
 294                 #size-cells = <0>;
 295                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 296                 clock-names = "i2c", "pclk";
 297                 pinctrl-names = "default";
 298                 pinctrl-0 = <&i2c3_xfer>;
 299                 status = "disabled";
 300         };
 301
 302         spi0: spi@ff190000 {
 303                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 304                 reg = <0x0 0xff190000 0x0 0x1000>;
 305                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 306                 #address-cells = <1>;
 307                 #size-cells = <0>;
 308                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 309                 clock-names = "spiclk", "apb_pclk";
 310                 dmas = <&dmac 8>, <&dmac 9>;
 311                 #dma-cells = <2>;
 312                 dma-names = "tx", "rx";
 313                 pinctrl-names = "default";
 314                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 315                 status = "disabled";
 316         };
 317
 318         wdt: watchdog@ff1a0000 {
 319                 compatible = "snps,dw-wdt";
 320                 reg = <0x0 0xff1a0000 0x0 0x100>;
 321                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 322                 status = "disabled";
 323         };
 324
 325         amba {
 326                 compatible = "simple-bus";
 327                 #address-cells = <2>;
 328                 #size-cells = <2>;
 329                 ranges;
 330
 331                 dmac: dmac@ff1f0000 {
 332                         compatible = "arm,pl330", "arm,primecell";
 333                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 334                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 335                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 336                         clocks = <&cru ACLK_DMAC>;
 337                         clock-names = "apb_pclk";
 338                         #dma-cells = <1>;
 339                 };
 340         };
 341
 342         saradc: saradc@ff280000 {
 343                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 344                 reg = <0x0 0xff280000 0x0 0x100>;
 345                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 346                 #io-channel-cells = <1>;
 347                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 348                 clock-names = "saradc", "apb_pclk";
 349                 resets = <&cru SRST_SARADC_P>;
 350                 reset-names = "saradc-apb";
 351                 status = "disabled";
 352         };
 353
 354         dmc: dmc@ff400000 {
 355                 u-boot,dm-pre-reloc;
 356                 compatible = "rockchip,rk3328-dmc", "syscon";
 357                 reg = <0x0 0xff400000 0x0 0x1000>;
 358         };
 359
 360         cru: clock-controller@ff440000 {
 361                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 362                 reg = <0x0 0xff440000 0x0 0x1000>;
 363                 rockchip,grf = <&grf>;
 364                 #clock-cells = <1>;
 365                 #reset-cells = <1>;
 366                 assigned-clocks =
 367                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 368                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 369                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 370                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 371                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 372                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 373                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 374                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 375                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 376                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 377                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 378                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 379                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 380                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 381                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 382                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 383                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 384                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 385                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 386                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 387                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 388                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 389                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 390                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 391                 assigned-clock-parents =
 392                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 393                         <&cru PLL_GPLL>, <&xin24m>,
 394                         <&xin24m>, <&xin24m>;
 395                 assigned-clock-rates =
 396                         <0>, <61440000>,
 397                         <0>, <24000000>,
 398                         <24000000>, <24000000>,
 399                         <15000000>, <15000000>,
 400                         <100000000>, <100000000>,
 401                         <100000000>, <100000000>,
 402                         <50000000>, <100000000>,
 403                         <100000000>, <100000000>,
 404                         <50000000>, <50000000>,
 405                         <50000000>, <50000000>,
 406                         <24000000>, <600000000>,
 407                         <491520000>, <1200000000>,
 408                         <150000000>, <75000000>,
 409                         <75000000>, <150000000>,
 410                         <75000000>, <75000000>,
 411                         <300000000>, <100000000>,
 412                         <300000000>, <200000000>,
 413                         <400000000>, <500000000>,
 414                         <200000000>, <300000000>,
 415                         <300000000>, <250000000>,
 416                         <200000000>, <100000000>,
 417                         <24000000>, <100000000>,
 418                         <150000000>, <50000000>,
 419                         <32768>, <32768>;
 420         };
 421
 422         sdmmc: rksdmmc@ff500000 {
 423                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 424                 reg = <0x0 0xff500000 0x0 0x4000>;
 425                 max-frequency = <150000000>;
 426                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 427                 clock-names = "biu", "ciu";
 428                 fifo-depth = <0x100>;
 429                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 430                 status = "disabled";
 431         };
 432
 433         sdio: dwmmc@ff510000 {
 434                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 435                 reg = <0x0 0xff510000 0x0 0x4000>;
 436                 max-frequency = <150000000>;
 437                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 438                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 439                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 440                 fifo-depth = <0x100>;
 441                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 442                 status = "disabled";
 443         };
 444
 445         emmc: rksdmmc@ff520000 {
 446                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 447                 reg = <0x0 0xff520000 0x0 0x4000>;
 448                 max-frequency = <150000000>;
 449                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 450                 clock-names = "biu", "ciu";
 451                 fifo-depth = <0x100>;
 452                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 453                 status = "disabled";
 454         };
 455
 456         gmac2io: ethernet@ff540000 {
 457                 compatible = "rockchip,rk3328-gmac";
 458                 reg = <0x0 0xff540000 0x0 0x10000>;
 459                 rockchip,grf = <&grf>;
 460                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 461                 interrupt-names = "macirq";
 462                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 463                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 464                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 465                          <&cru PCLK_MAC2IO>;
 466                 clock-names = "stmmaceth", "mac_clk_rx",
 467                               "mac_clk_tx", "clk_mac_ref",
 468                               "clk_mac_refout", "aclk_mac",
 469                               "pclk_mac";
 470                 resets = <&cru SRST_GMAC2IO_A>;
 471                 reset-names = "stmmaceth";
 472                 status = "disabled";
 473         };
 474
 475         usb_host0_ehci: usb@ff5c0000 {
 476                 compatible = "generic-ehci";
 477                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 478                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 479                 status = "disabled";
 480         };
 481
 482         usb_host0_ohci: usb@ff5d0000 {
 483                 compatible = "generic-ohci";
 484                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 485                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 486                 status = "disabled";
 487         };
 488
 489         usb20_otg: usb@ff580000 {
 490                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 491                              "snps,dwc2";
 492                 reg = <0x0 0xff580000 0x0 0x40000>;
 493                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 494                 hnp-srp-disable;
 495                 dr_mode = "otg";
 496                 status = "disabled";
 497         };
 498
 499         sdmmc_ext: rksdmmc@ff5f0000 {
 500                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 501                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 502                 max-frequency = <150000000>;
 503                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 504                 clock-names = "biu", "ciu";
 505                 fifo-depth = <0x100>;
 506                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 507                 status = "disabled";
 508         };
 509
 510         usb_host0_xhci: usb@ff600000 {
 511                 compatible = "rockchip,rk3328-xhci";
 512                 reg = <0x0 0xff600000 0x0 0x100000>;
 513                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 514                 snps,dis-enblslpm-quirk;
 515                 snps,phyif-utmi-bits = <16>;
 516                 snps,dis-u2-freeclk-exists-quirk;
 517                 snps,dis-u2-susphy-quirk;
 518                 status = "disabled";
 519         };
 520
 521         gic: interrupt-controller@ffb70000 {
 522                 compatible = "arm,gic-400";
 523                 #interrupt-cells = <3>;
 524                 #address-cells = <0>;
 525                 interrupt-controller;
 526                 reg = <0x0 0xff811000 0 0x1000>,
 527                       <0x0 0xff812000 0 0x2000>,
 528                       <0x0 0xff814000 0 0x2000>,
 529                       <0x0 0xff816000 0 0x2000>;
 530                 interrupts = <GIC_PPI 9
 531                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 532         };
 533
 534         pinctrl: pinctrl {
 535                 compatible = "rockchip,rk3328-pinctrl";
 536                 rockchip,grf = <&grf>;
 537                 #address-cells = <2>;
 538                 #size-cells = <2>;
 539                 ranges;
 540
 541                 gpio0: gpio0@ff210000 {
 542                         compatible = "rockchip,gpio-bank";
 543                         reg = <0x0 0xff210000 0x0 0x100>;
 544                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 545                         clocks = <&cru PCLK_GPIO0>;
 546
 547                         gpio-controller;
 548                         #gpio-cells = <2>;
 549
 550                         interrupt-controller;
 551                         #interrupt-cells = <2>;
 552                 };
 553
 554                 gpio1: gpio1@ff220000 {
 555                         compatible = "rockchip,gpio-bank";
 556                         reg = <0x0 0xff220000 0x0 0x100>;
 557                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 558                         clocks = <&cru PCLK_GPIO1>;
 559
 560                         gpio-controller;
 561                         #gpio-cells = <2>;
 562
 563                         interrupt-controller;
 564                         #interrupt-cells = <2>;
 565                 };
 566
 567                 gpio2: gpio2@ff230000 {
 568                         compatible = "rockchip,gpio-bank";
 569                         reg = <0x0 0xff230000 0x0 0x100>;
 570                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 571                         clocks = <&cru PCLK_GPIO2>;
 572
 573                         gpio-controller;
 574                         #gpio-cells = <2>;
 575
 576                         interrupt-controller;
 577                         #interrupt-cells = <2>;
 578                 };
 579
 580                 gpio3: gpio3@ff240000 {
 581                         compatible = "rockchip,gpio-bank";
 582                         reg = <0x0 0xff240000 0x0 0x100>;
 583                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 584                         clocks = <&cru PCLK_GPIO3>;
 585
 586                         gpio-controller;
 587                         #gpio-cells = <2>;
 588
 589                         interrupt-controller;
 590                         #interrupt-cells = <2>;
 591                 };
 592
 593                 pcfg_pull_up: pcfg-pull-up {
 594                         bias-pull-up;
 595                 };
 596
 597                 pcfg_pull_down: pcfg-pull-down {
 598                         bias-pull-down;
 599                 };
 600
 601                 pcfg_pull_none: pcfg-pull-none {
 602                         bias-disable;
 603                 };
 604
 605                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 606                         bias-disable;
 607                         drive-strength = <2>;
 608                 };
 609
 610                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 611                         bias-pull-up;
 612                         drive-strength = <2>;
 613                 };
 614
 615                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 616                         bias-pull-up;
 617                         drive-strength = <4>;
 618                 };
 619
 620                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 621                         bias-disable;
 622                         drive-strength = <4>;
 623                 };
 624
 625                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 626                         bias-pull-down;
 627                         drive-strength = <4>;
 628                 };
 629
 630                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 631                         bias-disable;
 632                         drive-strength = <8>;
 633                 };
 634
 635                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 636                         bias-pull-up;
 637                         drive-strength = <8>;
 638                 };
 639
 640                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 641                         bias-disable;
 642                         drive-strength = <12>;
 643                 };
 644
 645                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 646                         bias-pull-up;
 647                         drive-strength = <12>;
 648                 };
 649
 650                 pcfg_output_high: pcfg-output-high {
 651                         output-high;
 652                 };
 653
 654                 pcfg_output_low: pcfg-output-low {
 655                         output-low;
 656                 };
 657
 658                 pcfg_input_high: pcfg-input-high {
 659                         bias-pull-up;
 660                         input-enable;
 661                 };
 662
 663                 pcfg_input: pcfg-input {
 664                         input-enable;
 665                 };
 666
 667                 i2c0 {
 668                         i2c0_xfer: i2c0-xfer {
 669                                 rockchip,pins =
 670                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 671                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 672                         };
 673                 };
 674
 675                 i2c1 {
 676                         i2c1_xfer: i2c1-xfer {
 677                                 rockchip,pins =
 678                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 679                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 680                         };
 681                 };
 682
 683                 i2c2 {
 684                         i2c2_xfer: i2c2-xfer {
 685                                 rockchip,pins =
 686                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 687                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 688                         };
 689                 };
 690
 691                 i2c3 {
 692                         i2c3_xfer: i2c3-xfer {
 693                                 rockchip,pins =
 694                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 695                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 696                         };
 697                         i2c3_gpio: i2c3-gpio {
 698                                 rockchip,pins =
 699                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 700                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 701                         };
 702                 };
 703
 704                 hdmi_i2c {
 705                         hdmii2c_xfer: hdmii2c-xfer {
 706                                 rockchip,pins =
 707                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 708                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 709                         };
 710                 };
 711
 712                 uart0 {
 713                         uart0_xfer: uart0-xfer {
 714                                 rockchip,pins =
 715                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
 716                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 717                         };
 718
 719                         uart0_cts: uart0-cts {
 720                                 rockchip,pins =
 721                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 722                         };
 723
 724                         uart0_rts: uart0-rts {
 725                                 rockchip,pins =
 726                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
 727                         };
 728
 729                         uart0_rts_gpio: uart0-rts-gpio {
 730                                 rockchip,pins =
 731                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
 732                         };
 733                 };
 734
 735                 uart1 {
 736                         uart1_xfer: uart1-xfer {
 737                                 rockchip,pins =
 738                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
 739                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
 740                         };
 741
 742                         uart1_cts: uart1-cts {
 743                                 rockchip,pins =
 744                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
 745                         };
 746
 747                         uart1_rts: uart1-rts {
 748                                 rockchip,pins =
 749                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
 750                         };
 751
 752                         uart1_rts_gpio: uart1-rts-gpio {
 753                                 rockchip,pins =
 754                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
 755                         };
 756                 };
 757
 758                 uart2-0 {
 759                         uart2m0_xfer: uart2m0-xfer {
 760                                 rockchip,pins =
 761                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
 762                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
 763                         };
 764                 };
 765
 766                 uart2-1 {
 767                         uart2m1_xfer: uart2m1-xfer {
 768                                 rockchip,pins =
 769                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
 770                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
 771                         };
 772                 };
 773
 774                 spi0-0 {
 775                         spi0m0_clk: spi0m0-clk {
 776                                 rockchip,pins =
 777                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
 778                         };
 779
 780                         spi0m0_cs0: spi0m0-cs0 {
 781                                 rockchip,pins =
 782                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 783                         };
 784
 785                         spi0m0_tx: spi0m0-tx {
 786                                 rockchip,pins =
 787                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 788                         };
 789
 790                         spi0m0_rx: spi0m0-rx {
 791                                 rockchip,pins =
 792                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 793                         };
 794
 795                         spi0m0_cs1: spi0m0-cs1 {
 796                                 rockchip,pins =
 797                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 798                         };
 799                 };
 800
 801                 spi0-1 {
 802                         spi0m1_clk: spi0m1-clk {
 803                                 rockchip,pins =
 804                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
 805                         };
 806
 807                         spi0m1_cs0: spi0m1-cs0 {
 808                                 rockchip,pins =
 809                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
 810                         };
 811
 812                         spi0m1_tx: spi0m1-tx {
 813                                 rockchip,pins =
 814                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
 815                         };
 816
 817                         spi0m1_rx: spi0m1-rx {
 818                                 rockchip,pins =
 819                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
 820                         };
 821
 822                         spi0m1_cs1: spi0m1-cs1 {
 823                                 rockchip,pins =
 824                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
 825                         };
 826                 };
 827
 828                 spi0-2 {
 829                         spi0m2_clk: spi0m2-clk {
 830                                 rockchip,pins =
 831                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
 832                         };
 833
 834                         spi0m2_cs0: spi0m2-cs0 {
 835                                 rockchip,pins =
 836                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
 837                         };
 838
 839                         spi0m2_tx: spi0m2-tx {
 840                                 rockchip,pins =
 841                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
 842                         };
 843
 844                         spi0m2_rx: spi0m2-rx {
 845                                 rockchip,pins =
 846                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
 847                         };
 848                 };
 849
 850                 i2s1 {
 851                         i2s1_mclk: i2s1-mclk {
 852                                 rockchip,pins =
 853                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
 854                         };
 855
 856                         i2s1_sclk: i2s1-sclk {
 857                                 rockchip,pins =
 858                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
 859                         };
 860
 861                         i2s1_lrckrx: i2s1-lrckrx {
 862                                 rockchip,pins =
 863                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
 864                         };
 865
 866                         i2s1_lrcktx: i2s1-lrcktx {
 867                                 rockchip,pins =
 868                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
 869                         };
 870
 871                         i2s1_sdi: i2s1-sdi {
 872                                 rockchip,pins =
 873                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
 874                         };
 875
 876                         i2s1_sdo: i2s1-sdo {
 877                                 rockchip,pins =
 878                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
 879                         };
 880
 881                         i2s1_sdio1: i2s1-sdio1 {
 882                                 rockchip,pins =
 883                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
 884                         };
 885
 886                         i2s1_sdio2: i2s1-sdio2 {
 887                                 rockchip,pins =
 888                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
 889                         };
 890
 891                         i2s1_sdio3: i2s1-sdio3 {
 892                                 rockchip,pins =
 893                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
 894                         };
 895
 896                         i2s1_sleep: i2s1-sleep {
 897                                 rockchip,pins =
 898                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
 899                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
 900                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
 901                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
 902                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
 903                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
 904                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
 905                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
 906                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
 907                         };
 908                 };
 909
 910                 i2s2-0 {
 911                         i2s2m0_mclk: i2s2m0-mclk {
 912                                 rockchip,pins =
 913                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 914                         };
 915
 916                         i2s2m0_sclk: i2s2m0-sclk {
 917                                 rockchip,pins =
 918                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
 919                         };
 920
 921                         i2s2m0_lrckrx: i2s2m0-lrckrx {
 922                                 rockchip,pins =
 923                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
 924                         };
 925
 926                         i2s2m0_lrcktx: i2s2m0-lrcktx {
 927                                 rockchip,pins =
 928                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
 929                         };
 930
 931                         i2s2m0_sdi: i2s2m0-sdi {
 932                                 rockchip,pins =
 933                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
 934                         };
 935
 936                         i2s2m0_sdo: i2s2m0-sdo {
 937                                 rockchip,pins =
 938                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
 939                         };
 940
 941                         i2s2m0_sleep: i2s2m0-sleep {
 942                                 rockchip,pins =
 943                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
 944                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
 945                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
 946                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
 947                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
 948                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
 949                         };
 950                 };
 951
 952                 i2s2-1 {
 953                         i2s2m1_mclk: i2s2m1-mclk {
 954                                 rockchip,pins =
 955                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 956                         };
 957
 958                         i2s2m1_sclk: i2s2m1-sclk {
 959                                 rockchip,pins =
 960                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
 961                         };
 962
 963                         i2s2m1_lrckrx: i2sm1-lrckrx {
 964                                 rockchip,pins =
 965                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
 966                         };
 967
 968                         i2s2m1_lrcktx: i2s2m1-lrcktx {
 969                                 rockchip,pins =
 970                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
 971                         };
 972
 973                         i2s2m1_sdi: i2s2m1-sdi {
 974                                 rockchip,pins =
 975                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
 976                         };
 977
 978                         i2s2m1_sdo: i2s2m1-sdo {
 979                                 rockchip,pins =
 980                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
 981                         };
 982
 983                         i2s2m1_sleep: i2s2m1-sleep {
 984                                 rockchip,pins =
 985                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
 986                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
 987                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
 988                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
 989                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
 990                         };
 991                 };
 992
 993                 spdif-0 {
 994                         spdifm0_tx: spdifm0-tx {
 995                                 rockchip,pins =
 996                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
 997                         };
 998                 };
 999
1000                 spdif-1 {
1001                         spdifm1_tx: spdifm1-tx {
1002                                 rockchip,pins =
1003                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1004                         };
1005                 };
1006
1007                 spdif-2 {
1008                         spdifm2_tx: spdifm2-tx {
1009                                 rockchip,pins =
1010                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
1011                         };
1012                 };
1013
1014                 sdmmc0-0 {
1015                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1016                                 rockchip,pins =
1017                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1018                         };
1019
1020                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1021                                 rockchip,pins =
1022                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1023                         };
1024                 };
1025
1026                 sdmmc0-1 {
1027                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1028                                 rockchip,pins =
1029                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1030                         };
1031
1032                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1033                                 rockchip,pins =
1034                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1035                         };
1036                 };
1037
1038                 sdmmc0 {
1039                         sdmmc0_clk: sdmmc0-clk {
1040                                 rockchip,pins =
1041                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1042                         };
1043
1044                         sdmmc0_cmd: sdmmc0-cmd {
1045                                 rockchip,pins =
1046                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1047                         };
1048
1049                         sdmmc0_dectn: sdmmc0-dectn {
1050                                 rockchip,pins =
1051                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1052                         };
1053
1054                         sdmmc0_wrprt: sdmmc0-wrprt {
1055                                 rockchip,pins =
1056                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1057                         };
1058
1059                         sdmmc0_bus1: sdmmc0-bus1 {
1060                                 rockchip,pins =
1061                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1062                         };
1063
1064                         sdmmc0_bus4: sdmmc0-bus4 {
1065                                 rockchip,pins =
1066                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1067                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1068                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1069                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1070                         };
1071
1072                         sdmmc0_gpio: sdmmc0-gpio {
1073                                 rockchip,pins =
1074                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1075                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1076                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1077                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1078                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1079                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1080                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1081                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1082                         };
1083                 };
1084
1085                 sdmmc0ext {
1086                         sdmmc0ext_clk: sdmmc0ext-clk {
1087                                 rockchip,pins =
1088                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1089                         };
1090
1091                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1092                                 rockchip,pins =
1093                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1094                         };
1095
1096                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1097                                 rockchip,pins =
1098                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1099                         };
1100
1101                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1102                                 rockchip,pins =
1103                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1104                         };
1105
1106                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1107                                 rockchip,pins =
1108                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1109                         };
1110
1111                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1112                                 rockchip,pins =
1113                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1114                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1115                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1116                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1117                         };
1118
1119                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1120                                 rockchip,pins =
1121                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1122                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1123                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1124                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1125                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1126                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1127                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1128                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1129                         };
1130                 };
1131
1132                 sdmmc1 {
1133                         sdmmc1_clk: sdmmc1-clk {
1134                                 rockchip,pins =
1135                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1136                         };
1137
1138                         sdmmc1_cmd: sdmmc1-cmd {
1139                                 rockchip,pins =
1140                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1141                         };
1142
1143                         sdmmc1_pwren: sdmmc1-pwren {
1144                                 rockchip,pins =
1145                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1146                         };
1147
1148                         sdmmc1_wrprt: sdmmc1-wrprt {
1149                                 rockchip,pins =
1150                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1151                         };
1152
1153                         sdmmc1_dectn: sdmmc1-dectn {
1154                                 rockchip,pins =
1155                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1156                         };
1157
1158                         sdmmc1_bus1: sdmmc1-bus1 {
1159                                 rockchip,pins =
1160                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1161                         };
1162
1163                         sdmmc1_bus4: sdmmc1-bus4 {
1164                                 rockchip,pins =
1165                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1166                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1167                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1168                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1169                         };
1170
1171                         sdmmc1_gpio: sdmmc1-gpio {
1172                                 rockchip,pins =
1173                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1174                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1175                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1176                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1177                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1178                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1179                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1180                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1181                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1182                         };
1183                 };
1184
1185                 emmc {
1186                         emmc_clk: emmc-clk {
1187                                 rockchip,pins =
1188                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1189                         };
1190
1191                         emmc_cmd: emmc-cmd {
1192                                 rockchip,pins =
1193                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1194                         };
1195
1196                         emmc_pwren: emmc-pwren {
1197                                 rockchip,pins =
1198                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1199                         };
1200
1201                         emmc_rstnout: emmc-rstnout {
1202                                 rockchip,pins =
1203                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1204                         };
1205
1206                         emmc_bus1: emmc-bus1 {
1207                                 rockchip,pins =
1208                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1209                         };
1210
1211                         emmc_bus4: emmc-bus4 {
1212                                 rockchip,pins =
1213                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1214                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1215                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1216                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1217                         };
1218
1219                         emmc_bus8: emmc-bus8 {
1220                                 rockchip,pins =
1221                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1222                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1223                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1224                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1225                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1226                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1227                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1228                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1229                         };
1230                 };
1231
1232                 pwm0 {
1233                         pwm0_pin: pwm0-pin {
1234                                 rockchip,pins =
1235                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1236                         };
1237                 };
1238
1239                 pwm1 {
1240                         pwm1_pin: pwm1-pin {
1241                                 rockchip,pins =
1242                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1243                         };
1244                 };
1245
1246                 pwm2 {
1247                         pwm2_pin: pwm2-pin {
1248                                 rockchip,pins =
1249                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1250                         };
1251                 };
1252
1253                 pwmir {
1254                         pwmir_pin: pwmir-pin {
1255                                 rockchip,pins =
1256                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1257                         };
1258                 };
1259
1260                 gmac-0 {
1261                         rgmiim0_pins: rgmiim0-pins {
1262                                 rockchip,pins =
1263                                         /* mac_txclk */
1264                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1265                                         /* mac_rxclk */
1266                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1267                                         /* mac_mdio */
1268                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1269                                         /* mac_txen */
1270                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1271                                         /* mac_clk */
1272                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1273                                         /* mac_rxdv */
1274                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1275                                         /* mac_mdc */
1276                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1277                                         /* mac_rxd1 */
1278                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1279                                         /* mac_rxd0 */
1280                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1281                                         /* mac_txd1 */
1282                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1283                                         /* mac_txd0 */
1284                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1285                                         /* mac_rxd3 */
1286                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1287                                         /* mac_rxd2 */
1288                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1289                                         /* mac_txd3 */
1290                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1291                                         /* mac_txd2 */
1292                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1293                         };
1294
1295                         rmiim0_pins: rmiim0-pins {
1296                                 rockchip,pins =
1297                                         /* mac_mdio */
1298                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1299                                         /* mac_txen */
1300                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1301                                         /* mac_clk */
1302                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1303                                         /* mac_rxer */
1304                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1305                                         /* mac_rxdv */
1306                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1307                                         /* mac_mdc */
1308                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1309                                         /* mac_rxd1 */
1310                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1311                                         /* mac_rxd0 */
1312                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1313                                         /* mac_txd1 */
1314                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1315                                         /* mac_txd0 */
1316                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1317                         };
1318                 };
1319
1320                 gmac-1 {
1321                         rgmiim1_pins: rgmiim1-pins {
1322                                 rockchip,pins =
1323                                         /* mac_txclk */
1324                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1325                                         /* mac_rxclk */
1326                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1327                                         /* mac_mdio */
1328                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1329                                         /* mac_txen */
1330                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1331                                         /* mac_clk */
1332                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1333                                         /* mac_rxdv */
1334                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1335                                         /* mac_mdc */
1336                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1337                                         /* mac_rxd1 */
1338                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1339                                         /* mac_rxd0 */
1340                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1341                                         /* mac_txd1 */
1342                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1343                                         /* mac_txd0 */
1344                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1345                                         /* mac_rxd3 */
1346                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1347                                         /* mac_rxd2 */
1348                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1349                                         /* mac_txd3 */
1350                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1351                                         /* mac_txd2 */
1352                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1353
1354                                         /* mac_txclk */
1355                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1356                                         /* mac_txen */
1357                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1358                                         /* mac_clk */
1359                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1360                                         /* mac_txd1 */
1361                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1362                                         /* mac_txd0 */
1363                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1364                                         /* mac_txd3 */
1365                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1366                                         /* mac_txd2 */
1367                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1368                         };
1369
1370                         rmiim1_pins: rmiim1-pins {
1371                                 rockchip,pins =
1372                                         /* mac_mdio */
1373                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1374                                         /* mac_txen */
1375                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1376                                         /* mac_clk */
1377                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1378                                         /* mac_rxer */
1379                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1380                                         /* mac_rxdv */
1381                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1382                                         /* mac_mdc */
1383                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1384                                         /* mac_rxd1 */
1385                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1386                                         /* mac_rxd0 */
1387                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1388                                         /* mac_txd1 */
1389                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1390                                         /* mac_txd0 */
1391                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1392
1393                                         /* mac_mdio */
1394                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1395                                         /* mac_txen */
1396                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1397                                         /* mac_clk */
1398                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1399                                         /* mac_mdc */
1400                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1401                                         /* mac_txd1 */
1402                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1403                                         /* mac_txd0 */
1404                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1405                         };
1406                 };
1407
1408                 gmac2phy {
1409                         fephyled_speed100: fephyled-speed100 {
1410                                 rockchip,pins =
1411                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1412                         };
1413
1414                         fephyled_speed10: fephyled-speed10 {
1415                                 rockchip,pins =
1416                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1417                         };
1418
1419                         fephyled_duplex: fephyled-duplex {
1420                                 rockchip,pins =
1421                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1422                         };
1423
1424                         fephyled_rxm0: fephyled-rxm0 {
1425                                 rockchip,pins =
1426                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1427                         };
1428
1429                         fephyled_txm0: fephyled-txm0 {
1430                                 rockchip,pins =
1431                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1432                         };
1433
1434                         fephyled_linkm0: fephyled-linkm0 {
1435                                 rockchip,pins =
1436                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1437                         };
1438
1439                         fephyled_rxm1: fephyled-rxm1 {
1440                                 rockchip,pins =
1441                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1442                         };
1443
1444                         fephyled_txm1: fephyled-txm1 {
1445                                 rockchip,pins =
1446                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1447                         };
1448
1449                         fephyled_linkm1: fephyled-linkm1 {
1450                                 rockchip,pins =
1451                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1452                         };
1453                 };
1454
1455                 tsadc_pin {
1456                         tsadc_int: tsadc-int {
1457                                 rockchip,pins =
1458                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1459                         };
1460                         tsadc_gpio: tsadc-gpio {
1461                                 rockchip,pins =
1462                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1463                         };
1464                 };
1465
1466                 hdmi_pin {
1467                         hdmi_cec: hdmi-cec {
1468                                 rockchip,pins =
1469                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1470                         };
1471
1472                         hdmi_hpd: hdmi-hpd {
1473                                 rockchip,pins =
1474                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1475                         };
1476                 };
1477
1478                 cif-0 {
1479                         dvp_d2d9_m0:dvp-d2d9-m0 {
1480                                 rockchip,pins =
1481                                         /* cif_d0 */
1482                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1483                                         /* cif_d1 */
1484                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1485                                         /* cif_d2 */
1486                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1487                                         /* cif_d3 */
1488                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1489                                         /* cif_d4 */
1490                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1491                                         /* cif_d5m0 */
1492                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1493                                         /* cif_d6m0 */
1494                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1495                                         /* cif_d7m0 */
1496                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1497                                         /* cif_href */
1498                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1499                                         /* cif_vsync */
1500                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1501                                         /* cif_clkoutm0 */
1502                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1503                                         /* cif_clkin */
1504                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1505                         };
1506                 };
1507
1508                 cif-1 {
1509                         dvp_d2d9_m1:dvp-d2d9-m1 {
1510                                 rockchip,pins =
1511                                         /* cif_d0 */
1512                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1513                                         /* cif_d1 */
1514                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1515                                         /* cif_d2 */
1516                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1517                                         /* cif_d3 */
1518                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1519                                         /* cif_d4 */
1520                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1521                                         /* cif_d5m1 */
1522                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1523                                         /* cif_d6m1 */
1524                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1525                                         /* cif_d7m1 */
1526                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1527                                         /* cif_href */
1528                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1529                                         /* cif_vsync */
1530                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1531                                         /* cif_clkoutm1 */
1532                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1533                                         /* cif_clkin */
1534                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1535                         };
1536                 };
1537         };
1538 };