1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3308";
17 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a35", "arm,armv8";
44 enable-method = "psci";
45 clocks = <&cru ARMCLK>;
47 dynamic-power-coefficient = <90>;
48 operating-points-v2 = <&cpu0_opp_table>;
49 cpu-idle-states = <&CPU_SLEEP>;
50 next-level-cache = <&l2>;
55 compatible = "arm,cortex-a35", "arm,armv8";
57 enable-method = "psci";
58 operating-points-v2 = <&cpu0_opp_table>;
59 cpu-idle-states = <&CPU_SLEEP>;
60 next-level-cache = <&l2>;
65 compatible = "arm,cortex-a35", "arm,armv8";
67 enable-method = "psci";
68 operating-points-v2 = <&cpu0_opp_table>;
69 cpu-idle-states = <&CPU_SLEEP>;
70 next-level-cache = <&l2>;
75 compatible = "arm,cortex-a35", "arm,armv8";
77 enable-method = "psci";
78 operating-points-v2 = <&cpu0_opp_table>;
79 cpu-idle-states = <&CPU_SLEEP>;
80 next-level-cache = <&l2>;
84 entry-method = "psci";
86 CPU_SLEEP: cpu-sleep {
87 compatible = "arm,idle-state";
89 arm,psci-suspend-param = <0x0010000>;
90 entry-latency-us = <120>;
91 exit-latency-us = <250>;
92 min-residency-us = <900>;
101 cpu0_opp_table: cpu0-opp-table {
102 compatible = "operating-points-v2";
106 opp-hz = /bits/ 64 <408000000>;
107 opp-microvolt = <950000 950000 1340000>;
108 clock-latency-ns = <40000>;
112 opp-hz = /bits/ 64 <600000000>;
113 opp-microvolt = <950000 950000 1340000>;
114 clock-latency-ns = <40000>;
117 opp-hz = /bits/ 64 <816000000>;
118 opp-microvolt = <1025000 1025000 1340000>;
119 clock-latency-ns = <40000>;
122 opp-hz = /bits/ 64 <1008000000>;
123 opp-microvolt = <1125000 1125000 1340000>;
124 clock-latency-ns = <40000>;
129 compatible = "arm,cortex-a53-pmu";
130 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
137 mac_clkin: external-mac-clock {
138 compatible = "fixed-clock";
139 clock-frequency = <50000000>;
140 clock-output-names = "mac_clkin";
145 compatible = "arm,psci-1.0";
150 compatible = "arm,armv8-timer";
151 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
152 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
153 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
154 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
158 compatible = "fixed-clock";
160 clock-frequency = <24000000>;
161 clock-output-names = "xin24m";
165 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
166 reg = <0x0 0xff000000 0x0 0x10000>;
169 dmc: dmc@0xff010000 {
170 compatible = "rockchip,rk3308-dmc";
171 reg = <0x0 0xff010000 0x0 0x10000>;
174 detect_grf: syscon@ff00b000 {
175 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
176 reg = <0x0 0xff00b000 0x0 0x1000>;
177 #address-cells = <1>;
181 core_grf: syscon@ff00c000 {
182 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
183 reg = <0x0 0xff00c000 0x0 0x1000>;
184 #address-cells = <1>;
190 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
191 reg = <0x0 0xff040000 0x0 0x1000>;
192 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
193 clock-names = "i2c", "pclk";
194 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&i2c0_xfer>;
197 #address-cells = <1>;
203 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
204 reg = <0x0 0xff050000 0x0 0x1000>;
205 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
206 clock-names = "i2c", "pclk";
207 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&i2c1_xfer>;
210 #address-cells = <1>;
216 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
217 reg = <0x0 0xff060000 0x0 0x1000>;
218 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
219 clock-names = "i2c", "pclk";
220 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&i2c2_xfer>;
223 #address-cells = <1>;
229 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
230 reg = <0x0 0xff070000 0x0 0x1000>;
231 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
232 clock-names = "i2c", "pclk";
233 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&i2c3m0_xfer>;
236 #address-cells = <1>;
241 wdt: watchdog@ff080000 {
242 compatible = "snps,dw-wdt";
243 reg = <0x0 0xff080000 0x0 0x100>;
244 clocks = <&cru PCLK_WDT>;
245 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
249 uart0: serial@ff0a0000 {
250 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
251 reg = <0x0 0xff0a0000 0x0 0x100>;
252 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
254 clock-names = "baudclk", "apb_pclk";
257 pinctrl-names = "default";
258 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
262 uart1: serial@ff0b0000 {
263 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
264 reg = <0x0 0xff0b0000 0x0 0x100>;
265 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
267 clock-names = "baudclk", "apb_pclk";
270 pinctrl-names = "default";
271 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
275 uart2: serial@ff0c0000 {
276 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
277 reg = <0x0 0xff0c0000 0x0 0x100>;
278 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
280 clock-names = "baudclk", "apb_pclk";
283 pinctrl-names = "default";
284 pinctrl-0 = <&uart2m0_xfer>;
288 uart3: serial@ff0d0000 {
289 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
290 reg = <0x0 0xff0d0000 0x0 0x100>;
291 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
293 clock-names = "baudclk", "apb_pclk";
296 pinctrl-names = "default";
297 pinctrl-0 = <&uart3_xfer>;
301 uart4: serial@ff0e0000 {
302 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
303 reg = <0x0 0xff0e0000 0x0 0x100>;
304 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
306 clock-names = "baudclk", "apb_pclk";
309 pinctrl-names = "default";
310 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
315 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
316 reg = <0x0 0xff120000 0x0 0x1000>;
317 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
318 #address-cells = <1>;
320 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
321 clock-names = "spiclk", "apb_pclk";
322 dmas = <&dmac0 0>, <&dmac0 1>;
323 dma-names = "tx", "rx";
324 pinctrl-names = "default", "high_speed";
325 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
326 pinctrl-1 = <&spi0_clk_hs &spi0_csn0 &spi0_miso_hs &spi0_mosi_hs>;
331 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
332 reg = <0x0 0xff130000 0x0 0x1000>;
333 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
334 #address-cells = <1>;
336 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
337 clock-names = "spiclk", "apb_pclk";
338 dmas = <&dmac0 2>, <&dmac0 3>;
339 dma-names = "tx", "rx";
340 pinctrl-names = "default", "high_speed";
341 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
342 pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_miso_hs &spi1_mosi_hs>;
347 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
348 reg = <0x0 0xff140000 0x0 0x1000>;
349 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
350 #address-cells = <1>;
352 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
353 clock-names = "spiclk", "apb_pclk";
354 dmas = <&dmac1 16>, <&dmac1 17>;
355 dma-names = "tx", "rx";
356 pinctrl-names = "default", "high_speed";
357 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
358 pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>;
363 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
364 reg = <0x0 0xff160000 0x0 0x10>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pwm8_pin>;
368 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
369 clock-names = "pwm", "pclk";
374 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
375 reg = <0x0 0xff160010 0x0 0x10>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&pwm9_pin>;
379 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
380 clock-names = "pwm", "pclk";
384 pwm10: pwm@ff160020 {
385 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
386 reg = <0x0 0xff160020 0x0 0x10>;
388 pinctrl-names = "default";
389 pinctrl-0 = <&pwm10_pin>;
390 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
391 clock-names = "pwm", "pclk";
395 pwm11: pwm@ff160030 {
396 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
397 reg = <0x0 0xff160030 0x0 0x10>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pwm11_pin>;
401 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
402 clock-names = "pwm", "pclk";
407 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
408 reg = <0x0 0xff170000 0x0 0x10>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&pwm4_pin>;
412 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
413 clock-names = "pwm", "pclk";
418 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
419 reg = <0x0 0xff170010 0x0 0x10>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&pwm5_pin>;
423 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
424 clock-names = "pwm", "pclk";
429 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
430 reg = <0x0 0xff170020 0x0 0x10>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&pwm6_pin>;
434 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
435 clock-names = "pwm", "pclk";
440 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
441 reg = <0x0 0xff170030 0x0 0x10>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&pwm7_pin>;
445 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
446 clock-names = "pwm", "pclk";
451 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
452 reg = <0x0 0xff180000 0x0 0x10>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&pwm0_pin>;
456 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
457 clock-names = "pwm", "pclk";
462 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
463 reg = <0x0 0xff180010 0x0 0x10>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pwm1_pin>;
467 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
468 clock-names = "pwm", "pclk";
473 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
474 reg = <0x0 0xff180020 0x0 0x10>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&pwm2_pin>;
478 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
479 clock-names = "pwm", "pclk";
484 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
485 reg = <0x0 0xff180030 0x0 0x10>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&pwm3_pin>;
489 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
490 clock-names = "pwm", "pclk";
494 rktimer: rktimer@ff1a0000 {
495 compatible = "rockchip,rk3288-timer";
496 reg = <0x0 0xff1a0000 0x0 0x20>;
497 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
499 clock-names = "pclk", "timer";
502 saradc: saradc@ff1e0000 {
503 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
504 reg = <0x0 0xff1e0000 0x0 0x100>;
505 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
506 #io-channel-cells = <1>;
507 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
508 clock-names = "saradc", "apb_pclk";
509 resets = <&cru SRST_SARADC_P>;
510 reset-names = "saradc-apb";
515 compatible = "arm,amba-bus";
516 #address-cells = <2>;
520 dmac0: dma-controller@ff2c0000 {
521 compatible = "arm,pl330", "arm,primecell";
522 reg = <0x0 0xff2c0000 0x0 0x4000>;
523 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&cru ACLK_DMAC0>;
527 clock-names = "apb_pclk";
528 peripherals-req-type-burst;
531 dmac1: dma-controller@ff2d0000 {
532 compatible = "arm,pl330", "arm,primecell";
533 reg = <0x0 0xff2d0000 0x0 0x4000>;
534 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&cru ACLK_DMAC1>;
538 clock-names = "apb_pclk";
539 peripherals-req-type-burst;
543 i2s_2ch_0: i2s@ff350000 {
544 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
545 reg = <0x0 0xff350000 0x0 0x1000>;
546 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
548 clock-names = "i2s_clk", "i2s_hclk";
549 dmas = <&dmac1 8>, <&dmac1 9>;
550 dma-names = "tx", "rx";
551 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
552 reset-names = "reset-m", "reset-h";
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2s_2ch_0_sclk
561 i2s_2ch_1: i2s@ff360000 {
562 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
563 reg = <0x0 0xff360000 0x0 0x1000>;
564 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
566 clock-names = "i2s_clk", "i2s_hclk";
569 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
570 reset-names = "reset-m", "reset-h";
574 spdif_tx: spdif-tx@ff3a0000 {
575 compatible = "rockchip,rk3308-spdif", "rockchip,rk3328-spdif";
576 reg = <0x0 0xff3a0000 0x0 0x1000>;
577 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
579 clock-names = "mclk", "hclk";
582 pinctrl-names = "default";
583 pinctrl-0 = <&spdif_out>;
587 sdmmc: dwmmc@ff480000 {
588 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
589 reg = <0x0 0xff480000 0x0 0x4000>;
590 max-frequency = <150000000>;
592 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
593 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
594 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
595 fifo-depth = <0x100>;
596 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
602 emmc: dwmmc@ff490000 {
603 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
604 reg = <0x0 0xff490000 0x0 0x4000>;
605 max-frequency = <150000000>;
607 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
608 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
609 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
610 fifo-depth = <0x100>;
611 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
615 sdio: dwmmc@ff4a0000 {
616 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
617 reg = <0x0 0xff4a0000 0x0 0x4000>;
618 max-frequency = <150000000>;
620 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
621 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
622 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
623 fifo-depth = <0x100>;
624 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
625 pinctrl-names = "default";
626 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
630 mac: ethernet@ff4e0000 {
631 compatible = "rockchip,rk3308-mac";
632 reg = <0x0 0xff4e0000 0x0 0x10000>;
633 rockchip,grf = <&grf>;
634 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
635 interrupt-names = "macirq";
636 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
637 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
638 <&cru SCLK_MAC>, <&cru ACLK_MAC>,
639 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
640 clock-names = "stmmaceth", "mac_clk_rx",
641 "mac_clk_tx", "clk_mac_ref",
642 "clk_mac_refout", "aclk_mac",
643 "pclk_mac", "clk_mac_speed";
645 pinctrl-names = "default";
646 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
647 resets = <&cru SRST_MAC_A>;
648 reset-names = "stmmaceth";
652 cru: clock-controller@ff500000 {
653 compatible = "rockchip,rk3308-cru";
654 reg = <0x0 0xff500000 0x0 0x1000>;
655 rockchip,grf = <&grf>;
660 gic: interrupt-controller@ff580000 {
661 compatible = "arm,gic-400";
662 #interrupt-cells = <3>;
663 #address-cells = <0>;
664 interrupt-controller;
666 reg = <0x0 0xff581000 0x0 0x1000>,
667 <0x0 0xff582000 0x0 0x2000>,
668 <0x0 0xff584000 0x0 0x2000>,
669 <0x0 0xff586000 0x0 0x2000>;
670 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
673 sram: sram@fff80000 {
674 compatible = "mmio-sram";
675 reg = <0x0 0xfff80000 0x0 0x40000>;
676 #address-cells = <1>;
678 ranges = <0 0x0 0xfff80000 0x40000>;
679 /* reserved for ddr dvfs and system suspend/resume */
683 /* reserved for vad audio buffer */
684 vad_sram: vad-sram@8000 {
685 reg = <0x8000 0x38000>;
690 compatible = "rockchip,rk3308-pinctrl";
691 rockchip,grf = <&grf>;
692 #address-cells = <2>;
695 gpio0: gpio0@ff220000 {
696 compatible = "rockchip,gpio-bank";
697 reg = <0x0 0xff220000 0x0 0x100>;
698 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&cru PCLK_GPIO0>;
703 interrupt-controller;
704 #interrupt-cells = <2>;
707 gpio1: gpio1@ff230000 {
708 compatible = "rockchip,gpio-bank";
709 reg = <0x0 0xff230000 0x0 0x100>;
710 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&cru PCLK_GPIO1>;
715 interrupt-controller;
716 #interrupt-cells = <2>;
719 gpio2: gpio2@ff240000 {
720 compatible = "rockchip,gpio-bank";
721 reg = <0x0 0xff240000 0x0 0x100>;
722 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&cru PCLK_GPIO2>;
727 interrupt-controller;
728 #interrupt-cells = <2>;
731 gpio3: gpio3@ff250000 {
732 compatible = "rockchip,gpio-bank";
733 reg = <0x0 0xff250000 0x0 0x100>;
734 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&cru PCLK_GPIO3>;
739 interrupt-controller;
740 #interrupt-cells = <2>;
743 gpio4: gpio4@ff260000 {
744 compatible = "rockchip,gpio-bank";
745 reg = <0x0 0xff260000 0x0 0x100>;
746 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&cru PCLK_GPIO4>;
751 interrupt-controller;
752 #interrupt-cells = <2>;
755 pcfg_pull_up: pcfg-pull-up {
759 pcfg_pull_down: pcfg-pull-down {
763 pcfg_pull_none: pcfg-pull-none {
767 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
769 drive-strength = <2>;
772 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
774 drive-strength = <2>;
777 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
779 drive-strength = <4>;
782 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
784 drive-strength = <4>;
787 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
789 drive-strength = <4>;
792 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
794 drive-strength = <8>;
797 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
799 drive-strength = <8>;
802 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
804 drive-strength = <12>;
807 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
809 drive-strength = <12>;
812 pcfg_pull_none_smt: pcfg-pull-none-smt {
814 input-schmitt-enable;
817 pcfg_output_high: pcfg-output-high {
821 pcfg_output_low: pcfg-output-low {
825 pcfg_input_high: pcfg-input-high {
830 pcfg_input: pcfg-input {
835 i2c0_xfer: i2c0-xfer {
837 <1 RK_PD0 2 &pcfg_pull_none_smt>,
838 <1 RK_PD1 2 &pcfg_pull_none_smt>;
843 i2c1_xfer: i2c1-xfer {
845 <0 RK_PB3 1 &pcfg_pull_none_smt>,
846 <0 RK_PB4 1 &pcfg_pull_none_smt>;
851 i2c2_xfer: i2c2-xfer {
853 <2 RK_PA2 3 &pcfg_pull_none_smt>,
854 <2 RK_PA3 3 &pcfg_pull_none_smt>;
859 i2c3m0_xfer: i2c3m0-xfer {
861 <0 RK_PB7 2 &pcfg_pull_none_smt>,
862 <0 RK_PC0 2 &pcfg_pull_none_smt>;
867 i2c3m1_xfer: i2c3m1-xfer {
869 <3 RK_PB4 2 &pcfg_pull_none_smt>,
870 <3 RK_PB5 2 &pcfg_pull_none_smt>;
875 i2c3m2_xfer: i2c3m2-xfer {
877 <2 RK_PA1 3 &pcfg_pull_none_smt>,
878 <2 RK_PA0 3 &pcfg_pull_none_smt>;
883 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
885 <4 RK_PB4 1 &pcfg_pull_none>;
888 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
890 <4 RK_PB5 1 &pcfg_pull_none>;
893 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
895 <4 RK_PB6 1 &pcfg_pull_none>;
898 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
900 <4 RK_PB7 1 &pcfg_pull_none>;
903 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
905 <4 RK_PC0 1 &pcfg_pull_none>;
910 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
912 <2 RK_PA4 1 &pcfg_pull_none>;
915 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
917 <2 RK_PA5 1 &pcfg_pull_none>;
920 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
922 <2 RK_PA6 1 &pcfg_pull_none>;
925 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
927 <2 RK_PA7 1 &pcfg_pull_none>;
930 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
932 <2 RK_PB0 1 &pcfg_pull_none>;
935 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
937 <2 RK_PB1 1 &pcfg_pull_none>;
940 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
942 <2 RK_PB2 1 &pcfg_pull_none>;
945 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
947 <2 RK_PB3 1 &pcfg_pull_none>;
950 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
952 <2 RK_PB4 1 &pcfg_pull_none>;
955 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
957 <2 RK_PB5 1 &pcfg_pull_none>;
960 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
962 <2 RK_PB6 1 &pcfg_pull_none>;
965 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
967 <2 RK_PB7 1 &pcfg_pull_none>;
970 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
972 <2 RK_PC0 1 &pcfg_pull_none>;
977 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
979 <1 RK_PA2 2 &pcfg_pull_none>;
982 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
984 <1 RK_PA3 2 &pcfg_pull_none>;
987 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
989 <1 RK_PA4 2 &pcfg_pull_none>;
992 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
994 <1 RK_PA5 2 &pcfg_pull_none>;
997 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
999 <1 RK_PA6 2 &pcfg_pull_none>;
1002 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
1004 <1 RK_PA7 2 &pcfg_pull_none>;
1007 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
1009 <1 RK_PB0 2 &pcfg_pull_none>;
1012 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
1014 <1 RK_PB1 2 &pcfg_pull_none>;
1017 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
1019 <1 RK_PB2 2 &pcfg_pull_none>;
1022 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1024 <1 RK_PB3 2 &pcfg_pull_none>;
1029 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1031 <1 RK_PB4 2 &pcfg_pull_none>;
1034 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1036 <1 RK_PB5 2 &pcfg_pull_none>;
1039 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1041 <1 RK_PB6 2 &pcfg_pull_none>;
1044 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1046 <1 RK_PB7 2 &pcfg_pull_none>;
1049 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1051 <1 RK_PC0 2 &pcfg_pull_none>;
1054 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1056 <1 RK_PC1 2 &pcfg_pull_none>;
1059 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1061 <1 RK_PC2 2 &pcfg_pull_none>;
1064 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1066 <1 RK_PC3 2 &pcfg_pull_none>;
1069 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1071 <1 RK_PC4 2 &pcfg_pull_none>;
1074 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1076 <1 RK_PC5 2 &pcfg_pull_none>;
1081 pdm_m0_clk: pdm-m0-clk {
1083 <1 RK_PA4 3 &pcfg_pull_none>;
1086 pdm_m0_sdi0: pdm-m0-sdi0 {
1088 <1 RK_PB3 3 &pcfg_pull_none>;
1091 pdm_m0_sdi1: pdm-m0-sdi1 {
1093 <1 RK_PB2 3 &pcfg_pull_none>;
1096 pdm_m0_sdi2: pdm-m0-sdi2 {
1098 <1 RK_PB1 3 &pcfg_pull_none>;
1101 pdm_m0_sdi3: pdm-m0-sdi3 {
1103 <1 RK_PB0 3 &pcfg_pull_none>;
1108 pdm_m1_clk: pdm-m1-clk {
1110 <1 RK_PB6 4 &pcfg_pull_none>;
1113 pdm_m1_sdi0: pdm-m1-sdi0 {
1115 <1 RK_PC5 4 &pcfg_pull_none>;
1118 pdm_m1_sdi1: pdm-m1-sdi1 {
1120 <1 RK_PC4 4 &pcfg_pull_none>;
1123 pdm_m1_sdi2: pdm-m1-sdi2 {
1125 <1 RK_PC3 4 &pcfg_pull_none>;
1128 pdm_m1_sdi3: pdm-m1-sdi3 {
1130 <1 RK_PC2 4 &pcfg_pull_none>;
1135 pdm_m2_clkm: pdm-m2-clkm {
1137 <2 RK_PA4 3 &pcfg_pull_none>;
1140 pdm_m2_clk: pdm-m2-clk {
1142 <2 RK_PA6 2 &pcfg_pull_none>;
1145 pdm_m2_sdi0: pdm-m2-sdi0 {
1147 <2 RK_PB5 2 &pcfg_pull_none>;
1150 pdm_m2_sdi1: pdm-m2-sdi1 {
1152 <2 RK_PB6 2 &pcfg_pull_none>;
1155 pdm_m2_sdi2: pdm-m2-sdi2 {
1157 <2 RK_PB7 2 &pcfg_pull_none>;
1160 pdm_m2_sdi3: pdm-m2-sdi3 {
1162 <2 RK_PC0 2 &pcfg_pull_none>;
1167 spdif_in: spdif-in {
1169 <0 RK_PC2 1 &pcfg_pull_none>;
1174 spdif_out: spdif-out {
1176 <0 RK_PC1 1 &pcfg_pull_none>;
1181 tsadc_otp_gpio: tsadc-otp-gpio {
1183 <0 RK_PB2 0 &pcfg_pull_none>;
1186 tsadc_otp_out: tsadc-otp-out {
1188 <0 RK_PB2 1 &pcfg_pull_none>;
1193 uart0_xfer: uart0-xfer {
1195 <2 RK_PA1 1 &pcfg_pull_up>,
1196 <2 RK_PA0 1 &pcfg_pull_up>;
1199 uart0_cts: uart0-cts {
1201 <2 RK_PA2 1 &pcfg_pull_none>;
1204 uart0_rts: uart0-rts {
1206 <2 RK_PA3 1 &pcfg_pull_none>;
1209 uart0_rts_gpio: uart0-rts-gpio {
1211 <2 RK_PA3 0 &pcfg_pull_none>;
1216 uart1_xfer: uart1-xfer {
1218 <1 RK_PD1 1 &pcfg_pull_up>,
1219 <1 RK_PD0 1 &pcfg_pull_up>;
1222 uart1_cts: uart1-cts {
1224 <1 RK_PC6 1 &pcfg_pull_none>;
1227 uart1_rts: uart1-rts {
1229 <1 RK_PC7 1 &pcfg_pull_none>;
1234 uart2m0_xfer: uart2m0-xfer {
1236 <1 RK_PC7 2 &pcfg_pull_up>,
1237 <1 RK_PC6 2 &pcfg_pull_up>;
1242 uart2m1_xfer: uart2m1-xfer {
1244 <4 RK_PD3 2 &pcfg_pull_up>,
1245 <4 RK_PD2 2 &pcfg_pull_up>;
1250 uart3_xfer: uart3-xfer {
1252 <3 RK_PB5 4 &pcfg_pull_up>,
1253 <3 RK_PB4 4 &pcfg_pull_up>;
1258 uart3m1_xfer: uart3m1-xfer {
1260 <0 RK_PC2 3 &pcfg_pull_up>,
1261 <0 RK_PC1 3 &pcfg_pull_up>;
1267 uart4_xfer: uart4-xfer {
1269 <4 RK_PB1 1 &pcfg_pull_up>,
1270 <4 RK_PB0 1 &pcfg_pull_up>;
1273 uart4_cts: uart4-cts {
1275 <4 RK_PA6 1 &pcfg_pull_none>;
1279 uart4_rts: uart4-rts {
1281 <4 RK_PA7 1 &pcfg_pull_none>;
1284 uart4_rts_gpio: uart4-rts-gpio {
1286 <4 RK_PA7 0 &pcfg_pull_none>;
1291 spi0_clk: spi0-clk {
1293 <2 RK_PA2 2 &pcfg_pull_up_4ma>;
1296 spi0_csn0: spi0-csn0 {
1298 <2 RK_PA3 2 &pcfg_pull_up_4ma>;
1301 spi0_miso: spi0-miso {
1303 <2 RK_PA0 2 &pcfg_pull_up_4ma>;
1306 spi0_mosi: spi0-mosi {
1308 <2 RK_PA1 2 &pcfg_pull_up_4ma>;
1311 spi0_clk_hs: spi0-clk-hs {
1313 <2 RK_PA2 2 &pcfg_pull_up_8ma>;
1316 spi0_miso_hs: spi0-miso-hs {
1318 <2 RK_PA0 2 &pcfg_pull_up_8ma>;
1321 spi0_mosi_hs: spi0-mosi-hs {
1323 <2 RK_PA1 2 &pcfg_pull_up_8ma>;
1329 spi1_clk: spi1-clk {
1331 <3 RK_PB3 3 &pcfg_pull_up_4ma>;
1334 spi1_csn0: spi1-csn0 {
1336 <3 RK_PB5 3 &pcfg_pull_up_4ma>;
1339 spi1_miso: spi1-miso {
1341 <3 RK_PB2 3 &pcfg_pull_up_4ma>;
1344 spi1_mosi: spi1-mosi {
1346 <3 RK_PB4 3 &pcfg_pull_up_4ma>;
1349 spi1_clk_hs: spi1-clk-hs {
1351 <3 RK_PB3 3 &pcfg_pull_up_8ma>;
1354 spi1_miso_hs: spi1-miso-hs {
1356 <3 RK_PB2 3 &pcfg_pull_up_8ma>;
1359 spi1_mosi_hs: spi1-mosi-hs {
1361 <3 RK_PB4 3 &pcfg_pull_up_8ma>;
1366 spi1m1_miso: spi1m1-miso {
1368 <2 RK_PA4 2 &pcfg_pull_up_4ma>;
1371 spi1m1_mosi: spi1m1-mosi {
1373 <2 RK_PA5 2 &pcfg_pull_up_4ma>;
1376 spi1m1_clk: spi1m1-clk {
1378 <2 RK_PA7 2 &pcfg_pull_up_4ma>;
1381 spi1m1_csn0: spi1m1-csn0 {
1383 <2 RK_PB1 2 &pcfg_pull_up_4ma>;
1386 spi1m1_miso_hs: spi1m1-miso-hs {
1388 <2 RK_PA4 2 &pcfg_pull_up_8ma>;
1391 spi1m1_mosi_hs: spi1m1-mosi-hs {
1393 <2 RK_PA5 2 &pcfg_pull_up_8ma>;
1396 spi1m1_clk_hs: spi1m1-clk-hs {
1398 <2 RK_PA7 2 &pcfg_pull_up_8ma>;
1401 spi1m1_csn0_hs: spi1m1-csn0-hs {
1403 <2 RK_PB1 2 &pcfg_pull_up_8ma>;
1408 spi2_clk: spi2-clk {
1410 <1 RK_PD0 3 &pcfg_pull_up_4ma>;
1413 spi2_csn0: spi2-csn0 {
1415 <1 RK_PD1 3 &pcfg_pull_up_4ma>;
1418 spi2_miso: spi2-miso {
1420 <1 RK_PC6 3 &pcfg_pull_up_4ma>;
1423 spi2_mosi: spi2-mosi {
1425 <1 RK_PC7 3 &pcfg_pull_up_4ma>;
1428 spi2_clk_hs: spi2-clk-hs {
1430 <1 RK_PD0 3 &pcfg_pull_up_8ma>;
1433 spi2_miso_hs: spi2-miso-hs {
1435 <1 RK_PC6 3 &pcfg_pull_up_8ma>;
1438 spi2_mosi_hs: spi2-mosi-hs {
1440 <1 RK_PC7 3 &pcfg_pull_up_8ma>;
1445 sdmmc_clk: sdmmc-clk {
1447 <4 RK_PD5 1 &pcfg_pull_none_4ma>;
1450 sdmmc_cmd: sdmmc-cmd {
1452 <4 RK_PD4 1 &pcfg_pull_up_4ma>;
1455 sdmmc_det: sdmmc-det {
1457 <0 RK_PA3 1 &pcfg_pull_up_4ma>;
1460 sdmmc_pwren: sdmmc-pwren {
1462 <4 RK_PD6 1 &pcfg_pull_none_4ma>;
1465 sdmmc_bus1: sdmmc-bus1 {
1467 <4 RK_PD0 1 &pcfg_pull_up_4ma>;
1470 sdmmc_bus4: sdmmc-bus4 {
1472 <4 RK_PD0 1 &pcfg_pull_up_4ma>,
1473 <4 RK_PD1 1 &pcfg_pull_up_4ma>,
1474 <4 RK_PD2 1 &pcfg_pull_up_4ma>,
1475 <4 RK_PD3 1 &pcfg_pull_up_4ma>;
1478 sdmmc_gpio: sdmmc-gpio {
1480 <4 RK_PD0 0 &pcfg_pull_up_4ma>,
1481 <4 RK_PD1 0 &pcfg_pull_up_4ma>,
1482 <4 RK_PD2 0 &pcfg_pull_up_4ma>,
1483 <4 RK_PD3 0 &pcfg_pull_up_4ma>,
1484 <4 RK_PD4 0 &pcfg_pull_up_4ma>,
1485 <4 RK_PD5 0 &pcfg_pull_up_4ma>,
1486 <4 RK_PD6 0 &pcfg_pull_up_4ma>;
1491 sdio_clk: sdio-clk {
1493 <4 RK_PA5 1 &pcfg_pull_none_8ma>;
1496 sdio_cmd: sdio-cmd {
1498 <4 RK_PA4 1 &pcfg_pull_up_8ma>;
1501 sdio_pwren: sdio-pwren {
1503 <0 RK_PA2 1 &pcfg_pull_none_8ma>;
1506 sdio_wrpt: sdio-wrpt {
1508 <0 RK_PA1 1 &pcfg_pull_none_8ma>;
1511 sdio_intn: sdio-intn {
1513 <0 RK_PA0 1 &pcfg_pull_none_8ma>;
1516 sdio_bus1: sdio-bus1 {
1518 <4 RK_PA0 1 &pcfg_pull_up_8ma>;
1521 sdio_bus4: sdio-bus4 {
1523 <4 RK_PA0 1 &pcfg_pull_up_8ma>,
1524 <4 RK_PA1 1 &pcfg_pull_up_8ma>,
1525 <4 RK_PA2 1 &pcfg_pull_up_8ma>,
1526 <4 RK_PA3 1 &pcfg_pull_up_8ma>;
1529 sdio_gpio: sdio-gpio {
1531 <4 RK_PA0 0 &pcfg_pull_up_4ma>,
1532 <4 RK_PA1 0 &pcfg_pull_up_4ma>,
1533 <4 RK_PA2 0 &pcfg_pull_up_4ma>,
1534 <4 RK_PA3 0 &pcfg_pull_up_4ma>,
1535 <4 RK_PA4 0 &pcfg_pull_up_4ma>,
1536 <4 RK_PA5 0 &pcfg_pull_up_4ma>;
1541 emmc_clk: emmc-clk {
1543 <3 RK_PB1 2 &pcfg_pull_none_8ma>;
1546 emmc_cmd: emmc-cmd {
1548 <3 RK_PB0 2 &pcfg_pull_up_8ma>;
1551 emmc_pwren: emmc-pwren {
1553 <3 RK_PB3 2 &pcfg_pull_none>;
1556 emmc_rstn: emmc-rstn {
1558 <3 RK_PB2 2 &pcfg_pull_none>;
1561 emmc_bus1: emmc-bus1 {
1563 <3 RK_PA0 2 &pcfg_pull_up_8ma>;
1566 emmc_bus4: emmc-bus4 {
1568 <3 RK_PA0 2 &pcfg_pull_up_8ma>,
1569 <3 RK_PA1 2 &pcfg_pull_up_8ma>,
1570 <3 RK_PA2 2 &pcfg_pull_up_8ma>,
1571 <3 RK_PA3 2 &pcfg_pull_up_8ma>;
1574 emmc_bus8: emmc-bus8 {
1576 <3 RK_PA0 2 &pcfg_pull_up_8ma>,
1577 <3 RK_PA1 2 &pcfg_pull_up_8ma>,
1578 <3 RK_PA2 2 &pcfg_pull_up_8ma>,
1579 <3 RK_PA3 2 &pcfg_pull_up_8ma>,
1580 <3 RK_PA4 2 &pcfg_pull_up_8ma>,
1581 <3 RK_PA5 2 &pcfg_pull_up_8ma>,
1582 <3 RK_PA6 2 &pcfg_pull_up_8ma>,
1583 <3 RK_PA7 2 &pcfg_pull_up_8ma>;
1588 flash_csn0: flash-csn0 {
1590 <3 RK_PB5 1 &pcfg_pull_none>;
1593 flash_rdy: flash-rdy {
1595 <3 RK_PB4 1 &pcfg_pull_none>;
1598 flash_ale: flash-ale {
1600 <3 RK_PB3 1 &pcfg_pull_none>;
1603 flash_cle: flash-cle {
1605 <3 RK_PB1 1 &pcfg_pull_none>;
1608 flash_wrn: flash-wrn {
1610 <3 RK_PB0 1 &pcfg_pull_none>;
1613 flash_rdn: flash-rdn {
1615 <3 RK_PB2 1 &pcfg_pull_none>;
1618 flash_bus8: flash-bus8 {
1620 <3 RK_PA0 1 &pcfg_pull_up_12ma>,
1621 <3 RK_PA1 1 &pcfg_pull_up_12ma>,
1622 <3 RK_PA2 1 &pcfg_pull_up_12ma>,
1623 <3 RK_PA3 1 &pcfg_pull_up_12ma>,
1624 <3 RK_PA4 1 &pcfg_pull_up_12ma>,
1625 <3 RK_PA5 1 &pcfg_pull_up_12ma>,
1626 <3 RK_PA6 1 &pcfg_pull_up_12ma>,
1627 <3 RK_PA7 1 &pcfg_pull_up_12ma>;
1632 pwm0_pin: pwm0-pin {
1634 <0 RK_PB5 1 &pcfg_pull_none>;
1637 pwm0_pin_pull_down: pwm0-pin-pull-down {
1639 <0 RK_PB5 1 &pcfg_pull_down>;
1644 pwm1_pin: pwm1-pin {
1646 <0 RK_PB6 1 &pcfg_pull_none>;
1649 pwm1_pin_pull_down: pwm1-pin-pull-down {
1651 <0 RK_PB6 1 &pcfg_pull_down>;
1656 pwm2_pin: pwm2-pin {
1658 <0 RK_PB7 1 &pcfg_pull_none>;
1661 pwm2_pin_pull_down: pwm2-pin-pull-down {
1663 <0 RK_PB7 1 &pcfg_pull_down>;
1668 pwm3_pin: pwm3-pin {
1670 <0 RK_PC0 1 &pcfg_pull_none>;
1673 pwm3_pin_pull_down: pwm3-pin-pull-down {
1675 <0 RK_PC0 1 &pcfg_pull_down>;
1680 pwm4_pin: pwm4-pin {
1682 <0 RK_PA1 2 &pcfg_pull_none>;
1685 pwm4_pin_pull_down: pwm4-pin-pull-down {
1687 <0 RK_PA1 2 &pcfg_pull_down>;
1692 pwm5_pin: pwm5-pin {
1694 <0 RK_PC1 2 &pcfg_pull_none>;
1697 pwm5_pin_pull_down: pwm5-pin-pull-down {
1699 <0 RK_PC1 2 &pcfg_pull_down>;
1704 pwm6_pin: pwm6-pin {
1706 <0 RK_PC2 2 &pcfg_pull_none>;
1709 pwm6_pin_pull_down: pwm6-pin-pull-down {
1711 <0 RK_PC2 2 &pcfg_pull_down>;
1716 pwm7_pin: pwm7-pin {
1718 <2 RK_PB0 2 &pcfg_pull_none>;
1721 pwm7_pin_pull_down: pwm7-pin-pull-down {
1723 <2 RK_PB0 2 &pcfg_pull_down>;
1728 pwm8_pin: pwm8-pin {
1730 <2 RK_PB2 2 &pcfg_pull_none>;
1733 pwm8_pin_pull_down: pwm8-pin-pull-down {
1735 <2 RK_PB2 2 &pcfg_pull_down>;
1740 pwm9_pin: pwm9-pin {
1742 <2 RK_PB3 2 &pcfg_pull_none>;
1745 pwm9_pin_pull_down: pwm9-pin-pull-down {
1747 <2 RK_PB3 2 &pcfg_pull_down>;
1752 pwm10_pin: pwm10-pin {
1754 <2 RK_PB4 2 &pcfg_pull_none>;
1757 pwm10_pin_pull_down: pwm10-pin-pull-down {
1759 <2 RK_PB4 2 &pcfg_pull_down>;
1764 pwm11_pin: pwm11-pin {
1766 <2 RK_PC0 4 &pcfg_pull_none>;
1769 pwm11_pin_pull_down: pwm11-pin-pull-down {
1771 <2 RK_PC0 4 &pcfg_pull_down>;
1776 rmii_pins: rmii-pins {
1779 <1 RK_PC1 3 &pcfg_pull_none_12ma>,
1781 <1 RK_PC3 3 &pcfg_pull_none_12ma>,
1783 <1 RK_PC2 3 &pcfg_pull_none_12ma>,
1785 <1 RK_PC4 3 &pcfg_pull_none>,
1787 <1 RK_PC5 3 &pcfg_pull_none>,
1789 <1 RK_PB7 3 &pcfg_pull_none>,
1791 <1 RK_PC0 3 &pcfg_pull_none>,
1793 <1 RK_PB6 3 &pcfg_pull_none>,
1795 <1 RK_PB5 3 &pcfg_pull_none>;
1798 mac_refclk_12ma: mac-refclk-12ma {
1800 <1 RK_PB4 3 &pcfg_pull_none_12ma>;
1803 mac_refclk: mac-refclk {
1805 <1 RK_PB4 3 &pcfg_pull_none>;
1810 rmiim1_pins: rmiim1-pins {
1813 <4 RK_PB7 2 &pcfg_pull_none_12ma>,
1815 <4 RK_PA5 2 &pcfg_pull_none_12ma>,
1817 <4 RK_PA4 2 &pcfg_pull_none_12ma>,
1819 <4 RK_PA2 2 &pcfg_pull_none>,
1821 <4 RK_PA3 2 &pcfg_pull_none>,
1823 <4 RK_PA0 2 &pcfg_pull_none>,
1825 <4 RK_PA1 2 &pcfg_pull_none>,
1827 <4 RK_PB6 2 &pcfg_pull_none>,
1829 <4 RK_PB5 2 &pcfg_pull_none>;
1832 macm1_refclk_12ma: macm1-refclk-12ma {
1834 <4 RK_PB4 2 &pcfg_pull_none_12ma>;
1837 macm1_refclk: macm1-refclk {
1839 <4 RK_PB4 2 &pcfg_pull_none>;
1846 <0 RK_PC3 1 &pcfg_pull_none>;