arch/arm/dts/rk3288.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3288-cru.h>
   8 #include <dt-bindings/power/rk3288-power.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10 #include <dt-bindings/soc/rockchip,boot-mode.h>
  11
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         compatible = "rockchip,rk3288";
  17
  18         interrupt-parent = <&gic>;
  19
  20         aliases {
  21                 ethernet0 = &gmac;
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 i2c4 = &i2c4;
  27                 i2c5 = &i2c5;
  28                 mshc0 = &emmc;
  29                 mshc1 = &sdmmc;
  30                 mshc2 = &sdio0;
  31                 mshc3 = &sdio1;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37                 spi0 = &spi0;
  38                 spi1 = &spi1;
  39                 spi2 = &spi2;
  40         };
  41
  42         arm-pmu {
  43                 compatible = "arm,cortex-a12-pmu";
  44                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  45                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  46                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  47                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  48                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54                 enable-method = "rockchip,rk3066-smp";
  55                 rockchip,pmu = <&pmu>;
  56
  57                 cpu0: cpu@500 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a12";
  60                         reg = <0x500>;
  61                         resets = <&cru SRST_CORE0>;
  62                         operating-points-v2 = <&cpu_opp_table>;
  63                         #cooling-cells = <2>; /* min followed by max */
  64                         clock-latency = <40000>;
  65                         clocks = <&cru ARMCLK>;
  66                         dynamic-power-coefficient = <370>;
  67                 };
  68                 cpu1: cpu@501 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a12";
  71                         reg = <0x501>;
  72                         resets = <&cru SRST_CORE1>;
  73                         operating-points-v2 = <&cpu_opp_table>;
  74                         #cooling-cells = <2>; /* min followed by max */
  75                         clock-latency = <40000>;
  76                         clocks = <&cru ARMCLK>;
  77                         dynamic-power-coefficient = <370>;
  78                 };
  79                 cpu2: cpu@502 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a12";
  82                         reg = <0x502>;
  83                         resets = <&cru SRST_CORE2>;
  84                         operating-points-v2 = <&cpu_opp_table>;
  85                         #cooling-cells = <2>; /* min followed by max */
  86                         clock-latency = <40000>;
  87                         clocks = <&cru ARMCLK>;
  88                         dynamic-power-coefficient = <370>;
  89                 };
  90                 cpu3: cpu@503 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a12";
  93                         reg = <0x503>;
  94                         resets = <&cru SRST_CORE3>;
  95                         operating-points-v2 = <&cpu_opp_table>;
  96                         #cooling-cells = <2>; /* min followed by max */
  97                         clock-latency = <40000>;
  98                         clocks = <&cru ARMCLK>;
  99                         dynamic-power-coefficient = <370>;
 100                 };
 101         };
 102
 103         cpu_opp_table: opp-table-0 {
 104                 compatible = "operating-points-v2";
 105                 opp-shared;
 106
 107                 opp-126000000 {
 108                         opp-hz = /bits/ 64 <126000000>;
 109                         opp-microvolt = <900000>;
 110                 };
 111                 opp-216000000 {
 112                         opp-hz = /bits/ 64 <216000000>;
 113                         opp-microvolt = <900000>;
 114                 };
 115                 opp-312000000 {
 116                         opp-hz = /bits/ 64 <312000000>;
 117                         opp-microvolt = <900000>;
 118                 };
 119                 opp-408000000 {
 120                         opp-hz = /bits/ 64 <408000000>;
 121                         opp-microvolt = <900000>;
 122                 };
 123                 opp-600000000 {
 124                         opp-hz = /bits/ 64 <600000000>;
 125                         opp-microvolt = <900000>;
 126                 };
 127                 opp-696000000 {
 128                         opp-hz = /bits/ 64 <696000000>;
 129                         opp-microvolt = <950000>;
 130                 };
 131                 opp-816000000 {
 132                         opp-hz = /bits/ 64 <816000000>;
 133                         opp-microvolt = <1000000>;
 134                 };
 135                 opp-1008000000 {
 136                         opp-hz = /bits/ 64 <1008000000>;
 137                         opp-microvolt = <1050000>;
 138                 };
 139                 opp-1200000000 {
 140                         opp-hz = /bits/ 64 <1200000000>;
 141                         opp-microvolt = <1100000>;
 142                 };
 143                 opp-1416000000 {
 144                         opp-hz = /bits/ 64 <1416000000>;
 145                         opp-microvolt = <1200000>;
 146                 };
 147                 opp-1512000000 {
 148                         opp-hz = /bits/ 64 <1512000000>;
 149                         opp-microvolt = <1300000>;
 150                 };
 151                 opp-1608000000 {
 152                         opp-hz = /bits/ 64 <1608000000>;
 153                         opp-microvolt = <1350000>;
 154                 };
 155         };
 156
 157         reserved-memory {
 158                 #address-cells = <1>;
 159                 #size-cells = <1>;
 160                 ranges;
 161
 162                 /*
 163                  * The rk3288 cannot use the memory area above 0xfe000000
 164                  * for dma operations for some reason. While there is
 165                  * probably a better solution available somewhere, we
 166                  * haven't found it yet and while devices with 2GB of ram
 167                  * are not affected, this issue prevents 4GB from booting.
 168                  * So to make these devices at least bootable, block
 169                  * this area for the time being until the real solution
 170                  * is found.
 171                  */
 172                 dma-unusable@fe000000 {
 173                         reg = <0xfe000000 0x1000000>;
 174                 };
 175         };
 176
 177         xin24m: oscillator {
 178                 compatible = "fixed-clock";
 179                 clock-frequency = <24000000>;
 180                 clock-output-names = "xin24m";
 181                 #clock-cells = <0>;
 182         };
 183
 184         timer {
 185                 compatible = "arm,armv7-timer";
 186                 arm,cpu-registers-not-fw-configured;
 187                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 188                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 189                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 190                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 191                 clock-frequency = <24000000>;
 192                 arm,no-tick-in-suspend;
 193         };
 194
 195         timer: timer@ff810000 {
 196                 compatible = "rockchip,rk3288-timer";
 197                 reg = <0x0 0xff810000 0x0 0x20>;
 198                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 199                 clocks = <&cru PCLK_TIMER>, <&xin24m>;
 200                 clock-names = "pclk", "timer";
 201         };
 202
 203         display-subsystem {
 204                 compatible = "rockchip,display-subsystem";
 205                 ports = <&vopl_out>, <&vopb_out>;
 206         };
 207
 208         sdmmc: mmc@ff0c0000 {
 209                 compatible = "rockchip,rk3288-dw-mshc";
 210                 max-frequency = <150000000>;
 211                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 212                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 213                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 214                 fifo-depth = <0x100>;
 215                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 216                 reg = <0xff0c0000 0x4000>;
 217                 resets = <&cru SRST_MMC0>;
 218                 reset-names = "reset";
 219                 status = "disabled";
 220         };
 221
 222         sdio0: mmc@ff0d0000 {
 223                 compatible = "rockchip,rk3288-dw-mshc";
 224                 max-frequency = <150000000>;
 225                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 226                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 227                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 228                 fifo-depth = <0x100>;
 229                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 230                 reg = <0xff0d0000 0x4000>;
 231                 resets = <&cru SRST_SDIO0>;
 232                 reset-names = "reset";
 233                 status = "disabled";
 234         };
 235
 236         sdio1: mmc@ff0e0000 {
 237                 compatible = "rockchip,rk3288-dw-mshc";
 238                 max-frequency = <150000000>;
 239                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 240                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 241                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 242                 fifo-depth = <0x100>;
 243                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 244                 reg = <0xff0e0000 0x4000>;
 245                 resets = <&cru SRST_SDIO1>;
 246                 reset-names = "reset";
 247                 status = "disabled";
 248         };
 249
 250         emmc: mmc@ff0f0000 {
 251                 compatible = "rockchip,rk3288-dw-mshc";
 252                 max-frequency = <150000000>;
 253                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 254                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 255                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 256                 fifo-depth = <0x100>;
 257                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 258                 reg = <0xff0f0000 0x4000>;
 259                 resets = <&cru SRST_EMMC>;
 260                 reset-names = "reset";
 261                 status = "disabled";
 262         };
 263
 264         saradc: saradc@ff100000 {
 265                 compatible = "rockchip,saradc";
 266                 reg = <0xff100000 0x100>;
 267                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 268                 #io-channel-cells = <1>;
 269                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 270                 clock-names = "saradc", "apb_pclk";
 271                 resets = <&cru SRST_SARADC>;
 272                 reset-names = "saradc-apb";
 273                 status = "disabled";
 274         };
 275
 276         spi0: spi@ff110000 {
 277                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 278                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 279                 clock-names = "spiclk", "apb_pclk";
 280                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 281                 dma-names = "tx", "rx";
 282                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 283                 pinctrl-names = "default";
 284                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 285                 reg = <0xff110000 0x1000>;
 286                 #address-cells = <1>;
 287                 #size-cells = <0>;
 288                 status = "disabled";
 289         };
 290
 291         spi1: spi@ff120000 {
 292                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 293                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 294                 clock-names = "spiclk", "apb_pclk";
 295                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 296                 dma-names = "tx", "rx";
 297                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 300                 reg = <0xff120000 0x1000>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 status = "disabled";
 304         };
 305
 306         spi2: spi@ff130000 {
 307                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 308                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 309                 clock-names = "spiclk", "apb_pclk";
 310                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 311                 dma-names = "tx", "rx";
 312                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 313                 pinctrl-names = "default";
 314                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 315                 reg = <0xff130000 0x1000>;
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 status = "disabled";
 319         };
 320
 321         i2c1: i2c@ff140000 {
 322                 compatible = "rockchip,rk3288-i2c";
 323                 reg = <0xff140000 0x1000>;
 324                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327                 clock-names = "i2c";
 328                 clocks = <&cru PCLK_I2C1>;
 329                 pinctrl-names = "default";
 330                 pinctrl-0 = <&i2c1_xfer>;
 331                 status = "disabled";
 332         };
 333
 334         i2c3: i2c@ff150000 {
 335                 compatible = "rockchip,rk3288-i2c";
 336                 reg = <0xff150000 0x1000>;
 337                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 clock-names = "i2c";
 341                 clocks = <&cru PCLK_I2C3>;
 342                 pinctrl-names = "default";
 343                 pinctrl-0 = <&i2c3_xfer>;
 344                 status = "disabled";
 345         };
 346
 347         i2c4: i2c@ff160000 {
 348                 compatible = "rockchip,rk3288-i2c";
 349                 reg = <0xff160000 0x1000>;
 350                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 351                 #address-cells = <1>;
 352                 #size-cells = <0>;
 353                 clock-names = "i2c";
 354                 clocks = <&cru PCLK_I2C4>;
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&i2c4_xfer>;
 357                 status = "disabled";
 358         };
 359
 360         i2c5: i2c@ff170000 {
 361                 compatible = "rockchip,rk3288-i2c";
 362                 reg = <0xff170000 0x1000>;
 363                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 clock-names = "i2c";
 367                 clocks = <&cru PCLK_I2C5>;
 368                 pinctrl-names = "default";
 369                 pinctrl-0 = <&i2c5_xfer>;
 370                 status = "disabled";
 371         };
 372
 373         uart0: serial@ff180000 {
 374                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 375                 reg = <0xff180000 0x100>;
 376                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 377                 reg-shift = <2>;
 378                 reg-io-width = <4>;
 379                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 380                 clock-names = "baudclk", "apb_pclk";
 381                 dmas = <&dmac_peri 1>, <&dmac_peri 2>;
 382                 dma-names = "tx", "rx";
 383                 pinctrl-names = "default";
 384                 pinctrl-0 = <&uart0_xfer>;
 385                 status = "disabled";
 386         };
 387
 388         uart1: serial@ff190000 {
 389                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 390                 reg = <0xff190000 0x100>;
 391                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 392                 reg-shift = <2>;
 393                 reg-io-width = <4>;
 394                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 395                 clock-names = "baudclk", "apb_pclk";
 396                 dmas = <&dmac_peri 3>, <&dmac_peri 4>;
 397                 dma-names = "tx", "rx";
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&uart1_xfer>;
 400                 status = "disabled";
 401         };
 402
 403         uart2: serial@ff690000 {
 404                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 405                 reg = <0xff690000 0x100>;
 406                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 407                 reg-shift = <2>;
 408                 reg-io-width = <4>;
 409                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 410                 clock-names = "baudclk", "apb_pclk";
 411                 pinctrl-names = "default";
 412                 pinctrl-0 = <&uart2_xfer>;
 413                 status = "disabled";
 414         };
 415
 416         uart3: serial@ff1b0000 {
 417                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 418                 reg = <0xff1b0000 0x100>;
 419                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 420                 reg-shift = <2>;
 421                 reg-io-width = <4>;
 422                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 423                 clock-names = "baudclk", "apb_pclk";
 424                 dmas = <&dmac_peri 7>, <&dmac_peri 8>;
 425                 dma-names = "tx", "rx";
 426                 pinctrl-names = "default";
 427                 pinctrl-0 = <&uart3_xfer>;
 428                 status = "disabled";
 429         };
 430
 431         uart4: serial@ff1c0000 {
 432                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 433                 reg = <0xff1c0000 0x100>;
 434                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 435                 reg-shift = <2>;
 436                 reg-io-width = <4>;
 437                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 438                 clock-names = "baudclk", "apb_pclk";
 439                 dmas = <&dmac_peri 9>, <&dmac_peri 10>;
 440                 dma-names = "tx", "rx";
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&uart4_xfer>;
 443                 status = "disabled";
 444         };
 445
 446         dmac_peri: dma-controller@ff250000 {
 447                 compatible = "arm,pl330", "arm,primecell";
 448                 reg = <0xff250000 0x4000>;
 449                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 450                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 451                 #dma-cells = <1>;
 452                 arm,pl330-broken-no-flushp;
 453                 arm,pl330-periph-burst;
 454                 clocks = <&cru ACLK_DMAC2>;
 455                 clock-names = "apb_pclk";
 456         };
 457
 458         thermal: thermal-zones {
 459                 reserve_thermal: reserve-thermal {
 460                         polling-delay-passive = <1000>; /* milliseconds */
 461                         polling-delay = <5000>; /* milliseconds */
 462
 463                         thermal-sensors = <&tsadc 0>;
 464                 };
 465
 466                 cpu_thermal: cpu-thermal {
 467                         polling-delay-passive = <100>; /* milliseconds */
 468                         polling-delay = <5000>; /* milliseconds */
 469
 470                         thermal-sensors = <&tsadc 1>;
 471
 472                         trips {
 473                                 cpu_alert0: cpu_alert0 {
 474                                         temperature = <70000>; /* millicelsius */
 475                                         hysteresis = <2000>; /* millicelsius */
 476                                         type = "passive";
 477                                 };
 478                                 cpu_alert1: cpu_alert1 {
 479                                         temperature = <75000>; /* millicelsius */
 480                                         hysteresis = <2000>; /* millicelsius */
 481                                         type = "passive";
 482                                 };
 483                                 cpu_crit: cpu_crit {
 484                                         temperature = <90000>; /* millicelsius */
 485                                         hysteresis = <2000>; /* millicelsius */
 486                                         type = "critical";
 487                                 };
 488                         };
 489
 490                         cooling-maps {
 491                                 map0 {
 492                                         trip = <&cpu_alert0>;
 493                                         cooling-device =
 494                                                 <&cpu0 THERMAL_NO_LIMIT 6>,
 495                                                 <&cpu1 THERMAL_NO_LIMIT 6>,
 496                                                 <&cpu2 THERMAL_NO_LIMIT 6>,
 497                                                 <&cpu3 THERMAL_NO_LIMIT 6>;
 498                                 };
 499                                 map1 {
 500                                         trip = <&cpu_alert1>;
 501                                         cooling-device =
 502                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 503                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 504                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 505                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 506                                 };
 507                         };
 508                 };
 509
 510                 gpu_thermal: gpu-thermal {
 511                         polling-delay-passive = <100>; /* milliseconds */
 512                         polling-delay = <5000>; /* milliseconds */
 513
 514                         thermal-sensors = <&tsadc 2>;
 515
 516                         trips {
 517                                 gpu_alert0: gpu_alert0 {
 518                                         temperature = <70000>; /* millicelsius */
 519                                         hysteresis = <2000>; /* millicelsius */
 520                                         type = "passive";
 521                                 };
 522                                 gpu_crit: gpu_crit {
 523                                         temperature = <90000>; /* millicelsius */
 524                                         hysteresis = <2000>; /* millicelsius */
 525                                         type = "critical";
 526                                 };
 527                         };
 528
 529                         cooling-maps {
 530                                 map0 {
 531                                         trip = <&gpu_alert0>;
 532                                         cooling-device =
 533                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 534                                 };
 535                         };
 536                 };
 537         };
 538
 539         tsadc: tsadc@ff280000 {
 540                 compatible = "rockchip,rk3288-tsadc";
 541                 reg = <0xff280000 0x100>;
 542                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 543                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 544                 clock-names = "tsadc", "apb_pclk";
 545                 resets = <&cru SRST_TSADC>;
 546                 reset-names = "tsadc-apb";
 547                 pinctrl-names = "otp_out";
 548                 pinctrl-0 = <&otp_out>;
 549                 #thermal-sensor-cells = <1>;
 550                 hw-shut-temp = <125000>;
 551                 status = "disabled";
 552         };
 553
 554         gmac: ethernet@ff290000 {
 555                 compatible = "rockchip,rk3288-gmac";
 556                 reg = <0xff290000 0x10000>;
 557                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 558                 interrupt-names = "macirq";
 559                 rockchip,grf = <&grf>;
 560                 clocks = <&cru SCLK_MAC>,
 561                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 562                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 563                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 564                 clock-names = "stmmaceth",
 565                         "mac_clk_rx", "mac_clk_tx",
 566                         "clk_mac_ref", "clk_mac_refout",
 567                         "aclk_mac", "pclk_mac";
 568                 resets = <&cru SRST_MAC>;
 569                 reset-names = "stmmaceth";
 570         };
 571
 572         usb_host0_ehci: usb@ff500000 {
 573                 compatible = "generic-ehci";
 574                 reg = <0xff500000 0x100>;
 575                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 576                 clocks = <&cru HCLK_USBHOST0>;
 577                 clock-names = "usbhost";
 578                 phys = <&usbphy1>;
 579                 phy-names = "usb";
 580                 status = "disabled";
 581         };
 582
 583         /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
 584         usb_host0_ohci: usb@ff520000 {
 585                 compatible = "generic-ohci";
 586                 reg = <0x0 0xff520000 0x0 0x100>;
 587                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 588                 clocks = <&cru HCLK_USBHOST0>;
 589                 phys = <&usbphy1>;
 590                 phy-names = "usb";
 591                 status = "disabled";
 592         };
 593
 594         usb_host1: usb@ff540000 {
 595                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 596                                 "snps,dwc2";
 597                 reg = <0xff540000 0x40000>;
 598                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 599                 clocks = <&cru HCLK_USBHOST1>;
 600                 clock-names = "otg";
 601                 dr_mode = "host";
 602                 phys = <&usbphy2>;
 603                 phy-names = "usb2-phy";
 604                 snps,reset-phy-on-wake;
 605                 status = "disabled";
 606         };
 607
 608         usb_otg: usb@ff580000 {
 609                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 610                                 "snps,dwc2";
 611                 reg = <0xff580000 0x40000>;
 612                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 613                 clocks = <&cru HCLK_OTG0>;
 614                 clock-names = "otg";
 615                 dr_mode = "otg";
 616                 g-np-tx-fifo-size = <16>;
 617                 g-rx-fifo-size = <275>;
 618                 g-tx-fifo-size = <256 128 128 64 64 32>;
 619                 phys = <&usbphy0>;
 620                 phy-names = "usb2-phy";
 621                 status = "disabled";
 622         };
 623
 624         usb_hsic: usb@ff5c0000 {
 625                 compatible = "generic-ehci";
 626                 reg = <0xff5c0000 0x100>;
 627                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 628                 clocks = <&cru HCLK_HSIC>;
 629                 clock-names = "usbhost";
 630                 status = "disabled";
 631         };
 632
 633         dmac_bus_ns: dma-controller@ff600000 {
 634                 compatible = "arm,pl330", "arm,primecell";
 635                 reg = <0xff600000 0x4000>;
 636                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 637                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 638                 #dma-cells = <1>;
 639                 arm,pl330-broken-no-flushp;
 640                 arm,pl330-periph-burst;
 641                 clocks = <&cru ACLK_DMAC1>;
 642                 clock-names = "apb_pclk";
 643                 status = "disabled";
 644         };
 645
 646         i2c0: i2c@ff650000 {
 647                 compatible = "rockchip,rk3288-i2c";
 648                 reg = <0xff650000 0x1000>;
 649                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 650                 #address-cells = <1>;
 651                 #size-cells = <0>;
 652                 clock-names = "i2c";
 653                 clocks = <&cru PCLK_I2C0>;
 654                 pinctrl-names = "default";
 655                 pinctrl-0 = <&i2c0_xfer>;
 656                 status = "disabled";
 657         };
 658
 659         i2c2: i2c@ff660000 {
 660                 compatible = "rockchip,rk3288-i2c";
 661                 reg = <0xff660000 0x1000>;
 662                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 663                 #address-cells = <1>;
 664                 #size-cells = <0>;
 665                 clock-names = "i2c";
 666                 clocks = <&cru PCLK_I2C2>;
 667                 pinctrl-names = "default";
 668                 pinctrl-0 = <&i2c2_xfer>;
 669                 status = "disabled";
 670         };
 671
 672         pwm0: pwm@ff680000 {
 673                 compatible = "rockchip,rk3288-pwm";
 674                 reg = <0xff680000 0x10>;
 675                 #pwm-cells = <3>;
 676                 pinctrl-names = "default";
 677                 pinctrl-0 = <&pwm0_pin>;
 678                 clocks = <&cru PCLK_RKPWM>;
 679                 status = "disabled";
 680         };
 681
 682         pwm1: pwm@ff680010 {
 683                 compatible = "rockchip,rk3288-pwm";
 684                 reg = <0xff680010 0x10>;
 685                 #pwm-cells = <3>;
 686                 pinctrl-names = "default";
 687                 pinctrl-0 = <&pwm1_pin>;
 688                 clocks = <&cru PCLK_RKPWM>;
 689                 status = "disabled";
 690         };
 691
 692         pwm2: pwm@ff680020 {
 693                 compatible = "rockchip,rk3288-pwm";
 694                 reg = <0xff680020 0x10>;
 695                 #pwm-cells = <3>;
 696                 pinctrl-names = "default";
 697                 pinctrl-0 = <&pwm2_pin>;
 698                 clocks = <&cru PCLK_RKPWM>;
 699                 status = "disabled";
 700         };
 701
 702         pwm3: pwm@ff680030 {
 703                 compatible = "rockchip,rk3288-pwm";
 704                 reg = <0xff680030 0x10>;
 705                 #pwm-cells = <3>;
 706                 pinctrl-names = "default";
 707                 pinctrl-0 = <&pwm3_pin>;
 708                 clocks = <&cru PCLK_RKPWM>;
 709                 status = "disabled";
 710         };
 711
 712         bus_intmem: sram@ff700000 {
 713                 compatible = "mmio-sram";
 714                 reg = <0xff700000 0x18000>;
 715                 #address-cells = <1>;
 716                 #size-cells = <1>;
 717                 ranges = <0 0xff700000 0x18000>;
 718                 smp-sram@0 {
 719                         compatible = "rockchip,rk3066-smp-sram";
 720                         reg = <0x00 0x10>;
 721                 };
 722         };
 723
 724         pmu_sram: sram@ff720000 {
 725                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 726                 reg = <0xff720000 0x1000>;
 727         };
 728
 729         pmu: power-management@ff730000 {
 730                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 731                 reg = <0xff730000 0x100>;
 732
 733                 power: power-controller {
 734                         compatible = "rockchip,rk3288-power-controller";
 735                         #power-domain-cells = <1>;
 736                         #address-cells = <1>;
 737                         #size-cells = <0>;
 738
 739                         assigned-clocks = <&cru SCLK_EDP_24M>;
 740                         assigned-clock-parents = <&xin24m>;
 741
 742                         /*
 743                          * Note: Although SCLK_* are the working clocks
 744                          * of device without including on the NOC, needed for
 745                          * synchronous reset.
 746                          *
 747                          * The clocks on the which NOC:
 748                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 749                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 750                          * ACLK_RGA is on ACLK_RGA_NIU.
 751                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 752                          *
 753                          * Which clock are device clocks:
 754                          *      clocks          devices
 755                          *      *_IEP           IEP:Image Enhancement Processor
 756                          *      *_ISP           ISP:Image Signal Processing
 757                          *      *_VIP           VIP:Video Input Processor
 758                          *      *_VOP*          VOP:Visual Output Processor
 759                          *      *_RGA           RGA
 760                          *      *_EDP*          EDP
 761                          *      *_LVDS_*        LVDS
 762                          *      *_HDMI          HDMI
 763                          *      *_MIPI_*        MIPI
 764                          */
 765                         power-domain@RK3288_PD_VIO {
 766                                 reg = <RK3288_PD_VIO>;
 767                                 clocks = <&cru ACLK_IEP>,
 768                                          <&cru ACLK_ISP>,
 769                                          <&cru ACLK_RGA>,
 770                                          <&cru ACLK_VIP>,
 771                                          <&cru ACLK_VOP0>,
 772                                          <&cru ACLK_VOP1>,
 773                                          <&cru DCLK_VOP0>,
 774                                          <&cru DCLK_VOP1>,
 775                                          <&cru HCLK_IEP>,
 776                                          <&cru HCLK_ISP>,
 777                                          <&cru HCLK_RGA>,
 778                                          <&cru HCLK_VIP>,
 779                                          <&cru HCLK_VOP0>,
 780                                          <&cru HCLK_VOP1>,
 781                                          <&cru PCLK_EDP_CTRL>,
 782                                          <&cru PCLK_HDMI_CTRL>,
 783                                          <&cru PCLK_LVDS_PHY>,
 784                                          <&cru PCLK_MIPI_CSI>,
 785                                          <&cru PCLK_MIPI_DSI0>,
 786                                          <&cru PCLK_MIPI_DSI1>,
 787                                          <&cru SCLK_EDP_24M>,
 788                                          <&cru SCLK_EDP>,
 789                                          <&cru SCLK_ISP_JPE>,
 790                                          <&cru SCLK_ISP>,
 791                                          <&cru SCLK_RGA>;
 792                                 pm_qos = <&qos_vio0_iep>,
 793                                          <&qos_vio1_vop>,
 794                                          <&qos_vio1_isp_w0>,
 795                                          <&qos_vio1_isp_w1>,
 796                                          <&qos_vio0_vop>,
 797                                          <&qos_vio0_vip>,
 798                                          <&qos_vio2_rga_r>,
 799                                          <&qos_vio2_rga_w>,
 800                                          <&qos_vio1_isp_r>;
 801                                 #power-domain-cells = <0>;
 802                         };
 803
 804                         /*
 805                          * Note: The following 3 are HEVC(H.265) clocks,
 806                          * and on the ACLK_HEVC_NIU (NOC).
 807                          */
 808                         power-domain@RK3288_PD_HEVC {
 809                                 reg = <RK3288_PD_HEVC>;
 810                                 clocks = <&cru ACLK_HEVC>,
 811                                          <&cru SCLK_HEVC_CABAC>,
 812                                          <&cru SCLK_HEVC_CORE>;
 813                                 pm_qos = <&qos_hevc_r>,
 814                                          <&qos_hevc_w>;
 815                                 #power-domain-cells = <0>;
 816                         };
 817
 818                         /*
 819                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 820                          * (video endecoder & decoder) clocks that on the
 821                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 822                          */
 823                         power-domain@RK3288_PD_VIDEO {
 824                                 reg = <RK3288_PD_VIDEO>;
 825                                 clocks = <&cru ACLK_VCODEC>,
 826                                          <&cru HCLK_VCODEC>;
 827                                 pm_qos = <&qos_video>;
 828                                 #power-domain-cells = <0>;
 829                         };
 830
 831                         /*
 832                          * Note: ACLK_GPU is the GPU clock,
 833                          * and on the ACLK_GPU_NIU (NOC).
 834                          */
 835                         power-domain@RK3288_PD_GPU {
 836                                 reg = <RK3288_PD_GPU>;
 837                                 clocks = <&cru ACLK_GPU>;
 838                                 pm_qos = <&qos_gpu_r>,
 839                                          <&qos_gpu_w>;
 840                                 #power-domain-cells = <0>;
 841                         };
 842                 };
 843
 844                 reboot-mode {
 845                         compatible = "syscon-reboot-mode";
 846                         offset = <0x94>;
 847                         mode-normal = <BOOT_NORMAL>;
 848                         mode-recovery = <BOOT_RECOVERY>;
 849                         mode-bootloader = <BOOT_FASTBOOT>;
 850                         mode-loader = <BOOT_BL_DOWNLOAD>;
 851                 };
 852         };
 853
 854         sgrf: syscon@ff740000 {
 855                 compatible = "rockchip,rk3288-sgrf", "syscon";
 856                 reg = <0xff740000 0x1000>;
 857         };
 858
 859         cru: clock-controller@ff760000 {
 860                 compatible = "rockchip,rk3288-cru";
 861                 reg = <0xff760000 0x1000>;
 862                 rockchip,grf = <&grf>;
 863                 #clock-cells = <1>;
 864                 #reset-cells = <1>;
 865                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 866                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 867                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 868                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 869                                   <&cru PCLK_PERI>;
 870                 assigned-clock-rates = <594000000>, <400000000>,
 871                                        <500000000>, <300000000>,
 872                                        <150000000>, <75000000>,
 873                                        <300000000>, <150000000>,
 874                                        <75000000>;
 875         };
 876
 877         grf: syscon@ff770000 {
 878                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 879                 reg = <0xff770000 0x1000>;
 880
 881                 edp_phy: edp-phy {
 882                         compatible = "rockchip,rk3288-dp-phy";
 883                         clocks = <&cru SCLK_EDP_24M>;
 884                         clock-names = "24m";
 885                         #phy-cells = <0>;
 886                         status = "disabled";
 887                 };
 888
 889                 io_domains: io-domains {
 890                         compatible = "rockchip,rk3288-io-voltage-domain";
 891                         status = "disabled";
 892                 };
 893
 894                 usbphy: usbphy {
 895                         compatible = "rockchip,rk3288-usb-phy";
 896                         #address-cells = <1>;
 897                         #size-cells = <0>;
 898                         status = "disabled";
 899
 900                         usbphy0: usb-phy@320 {
 901                                 #phy-cells = <0>;
 902                                 reg = <0x320>;
 903                                 clocks = <&cru SCLK_OTGPHY0>;
 904                                 clock-names = "phyclk";
 905                                 #clock-cells = <0>;
 906                                 resets = <&cru SRST_USBOTG_PHY>;
 907                                 reset-names = "phy-reset";
 908                         };
 909
 910                         usbphy1: usb-phy@334 {
 911                                 #phy-cells = <0>;
 912                                 reg = <0x334>;
 913                                 clocks = <&cru SCLK_OTGPHY1>;
 914                                 clock-names = "phyclk";
 915                                 #clock-cells = <0>;
 916                                 resets = <&cru SRST_USBHOST0_PHY>;
 917                                 reset-names = "phy-reset";
 918                         };
 919
 920                         usbphy2: usb-phy@348 {
 921                                 #phy-cells = <0>;
 922                                 reg = <0x348>;
 923                                 clocks = <&cru SCLK_OTGPHY2>;
 924                                 clock-names = "phyclk";
 925                                 #clock-cells = <0>;
 926                                 resets = <&cru SRST_USBHOST1_PHY>;
 927                                 reset-names = "phy-reset";
 928                         };
 929                 };
 930         };
 931
 932         wdt: watchdog@ff800000 {
 933                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 934                 reg = <0xff800000 0x100>;
 935                 clocks = <&cru PCLK_WDT>;
 936                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 937                 status = "disabled";
 938         };
 939
 940         spdif: sound@ff88b0000 {
 941                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 942                 reg = <0xff8b0000 0x10000>;
 943                 #sound-dai-cells = <0>;
 944                 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
 945                 clock-names = "mclk", "hclk";
 946                 dmas = <&dmac_bus_s 3>;
 947                 dma-names = "tx";
 948                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 949                 pinctrl-names = "default";
 950                 pinctrl-0 = <&spdif_tx>;
 951                 rockchip,grf = <&grf>;
 952                 status = "disabled";
 953         };
 954
 955         i2s: i2s@ff890000 {
 956                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 957                 reg = <0xff890000 0x10000>;
 958                 #sound-dai-cells = <0>;
 959                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 960                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
 961                 clock-names = "i2s_clk", "i2s_hclk";
 962                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 963                 dma-names = "tx", "rx";
 964                 pinctrl-names = "default";
 965                 pinctrl-0 = <&i2s0_bus>;
 966                 rockchip,playback-channels = <8>;
 967                 rockchip,capture-channels = <2>;
 968                 status = "disabled";
 969         };
 970
 971         crypto: crypto@ff8a0000 {
 972                 compatible = "rockchip,rk3288-crypto";
 973                 reg = <0xff8a0000 0x4000>;
 974                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 975                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
 976                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
 977                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 978                 resets = <&cru SRST_CRYPTO>;
 979                 reset-names = "crypto-rst";
 980         };
 981
 982         iep_mmu: iommu@ff900800 {
 983                 compatible = "rockchip,iommu";
 984                 reg = <0xff900800 0x40>;
 985                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 986                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 987                 clock-names = "aclk", "iface";
 988                 #iommu-cells = <0>;
 989                 status = "disabled";
 990         };
 991
 992         isp_mmu: iommu@ff914000 {
 993                 compatible = "rockchip,iommu";
 994                 reg = <0xff914000 0x100>, <0xff915000 0x100>;
 995                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 996                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
 997                 clock-names = "aclk", "iface";
 998                 #iommu-cells = <0>;
 999                 rockchip,disable-mmu-reset;
1000                 status = "disabled";
1001         };
1002
1003         rga: rga@ff920000 {
1004                 compatible = "rockchip,rk3288-rga";
1005                 reg = <0xff920000 0x180>;
1006                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1007                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1008                 clock-names = "aclk", "hclk", "sclk";
1009                 power-domains = <&power RK3288_PD_VIO>;
1010                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1011                 reset-names = "core", "axi", "ahb";
1012         };
1013
1014         vopb: vop@ff930000 {
1015                 compatible = "rockchip,rk3288-vop";
1016                 reg = <0xff930000 0x19c>, <0xff931000 0x1000>;
1017                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1018                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1019                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1020                 power-domains = <&power RK3288_PD_VIO>;
1021                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1022                 reset-names = "axi", "ahb", "dclk";
1023                 iommus = <&vopb_mmu>;
1024                 status = "disabled";
1025
1026                 vopb_out: port {
1027                         #address-cells = <1>;
1028                         #size-cells = <0>;
1029
1030                         vopb_out_hdmi: endpoint@0 {
1031                                 reg = <0>;
1032                                 remote-endpoint = <&hdmi_in_vopb>;
1033                         };
1034
1035                         vopb_out_edp: endpoint@1 {
1036                                 reg = <1>;
1037                                 remote-endpoint = <&edp_in_vopb>;
1038                         };
1039
1040                         vopb_out_mipi: endpoint@2 {
1041                                 reg = <2>;
1042                                 remote-endpoint = <&mipi_in_vopb>;
1043                         };
1044
1045                         vopb_out_lvds: endpoint@3 {
1046                                 reg = <3>;
1047                                 remote-endpoint = <&lvds_in_vopb>;
1048                         };
1049                 };
1050         };
1051
1052         vopb_mmu: iommu@ff930300 {
1053                 compatible = "rockchip,iommu";
1054                 reg = <0xff930300 0x100>;
1055                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1056                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1057                 clock-names = "aclk", "iface";
1058                 power-domains = <&power RK3288_PD_VIO>;
1059                 #iommu-cells = <0>;
1060                 status = "disabled";
1061         };
1062
1063         vopl: vop@ff940000 {
1064                 compatible = "rockchip,rk3288-vop";
1065                 reg = <0xff940000 0x19c>, <0xff941000 0x1000>;
1066                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1067                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1068                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1069                 power-domains = <&power RK3288_PD_VIO>;
1070                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1071                 reset-names = "axi", "ahb", "dclk";
1072                 iommus = <&vopl_mmu>;
1073                 status = "disabled";
1074
1075                 vopl_out: port {
1076                         #address-cells = <1>;
1077                         #size-cells = <0>;
1078
1079                         vopl_out_hdmi: endpoint@0 {
1080                                 reg = <0>;
1081                                 remote-endpoint = <&hdmi_in_vopl>;
1082                         };
1083
1084                         vopl_out_edp: endpoint@1 {
1085                                 reg = <1>;
1086                                 remote-endpoint = <&edp_in_vopl>;
1087                         };
1088
1089                         vopl_out_mipi: endpoint@2 {
1090                                 reg = <2>;
1091                                 remote-endpoint = <&mipi_in_vopl>;
1092                         };
1093
1094                         vopl_out_lvds: endpoint@3 {
1095                                 reg = <3>;
1096                                 remote-endpoint = <&lvds_in_vopl>;
1097                         };
1098                 };
1099         };
1100
1101         vopl_mmu: iommu@ff940300 {
1102                 compatible = "rockchip,iommu";
1103                 reg = <0xff940300 0x100>;
1104                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1105                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1106                 clock-names = "aclk", "iface";
1107                 power-domains = <&power RK3288_PD_VIO>;
1108                 #iommu-cells = <0>;
1109                 status = "disabled";
1110         };
1111
1112         mipi_dsi: mipi@ff960000 {
1113                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1114                 reg = <0xff960000 0x4000>;
1115                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1116                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1117                 clock-names = "ref", "pclk";
1118                 power-domains = <&power RK3288_PD_VIO>;
1119                 rockchip,grf = <&grf>;
1120                 status = "disabled";
1121
1122                 ports {
1123                         mipi_in: port {
1124                                 #address-cells = <1>;
1125                                 #size-cells = <0>;
1126                                 mipi_in_vopb: endpoint@0 {
1127                                         reg = <0>;
1128                                         remote-endpoint = <&vopb_out_mipi>;
1129                                 };
1130                                 mipi_in_vopl: endpoint@1 {
1131                                         reg = <1>;
1132                                         remote-endpoint = <&vopl_out_mipi>;
1133                                 };
1134                         };
1135                 };
1136         };
1137
1138         lvds: lvds@ff96c000 {
1139                 compatible = "rockchip,rk3288-lvds";
1140                 reg = <0xff96c000 0x4000>;
1141                 clocks = <&cru PCLK_LVDS_PHY>;
1142                 clock-names = "pclk_lvds";
1143                 pinctrl-names = "lcdc";
1144                 pinctrl-0 = <&lcdc_ctl>;
1145                 power-domains = <&power RK3288_PD_VIO>;
1146                 rockchip,grf = <&grf>;
1147                 status = "disabled";
1148
1149                 ports {
1150                         #address-cells = <1>;
1151                         #size-cells = <0>;
1152
1153                         lvds_in: port@0 {
1154                                 reg = <0>;
1155
1156                                 #address-cells = <1>;
1157                                 #size-cells = <0>;
1158
1159                                 lvds_in_vopb: endpoint@0 {
1160                                         reg = <0>;
1161                                         remote-endpoint = <&vopb_out_lvds>;
1162                                 };
1163                                 lvds_in_vopl: endpoint@1 {
1164                                         reg = <1>;
1165                                         remote-endpoint = <&vopl_out_lvds>;
1166                                 };
1167                         };
1168                 };
1169         };
1170
1171         edp: dp@ff970000 {
1172                 compatible = "rockchip,rk3288-dp";
1173                 reg = <0xff970000 0x4000>;
1174                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1175                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1176                 clock-names = "dp", "pclk";
1177                 phys = <&edp_phy>;
1178                 phy-names = "dp";
1179                 power-domains = <&power RK3288_PD_VIO>;
1180                 resets = <&cru SRST_EDP>;
1181                 reset-names = "dp";
1182                 rockchip,grf = <&grf>;
1183                 status = "disabled";
1184
1185                 ports {
1186                         #address-cells = <1>;
1187                         #size-cells = <0>;
1188                         edp_in: port@0 {
1189                                 reg = <0>;
1190                                 #address-cells = <1>;
1191                                 #size-cells = <0>;
1192                                 edp_in_vopb: endpoint@0 {
1193                                         reg = <0>;
1194                                         remote-endpoint = <&vopb_out_edp>;
1195                                 };
1196                                 edp_in_vopl: endpoint@1 {
1197                                         reg = <1>;
1198                                         remote-endpoint = <&vopl_out_edp>;
1199                                 };
1200                         };
1201                 };
1202         };
1203
1204         hdmi: hdmi@ff980000 {
1205                 compatible = "rockchip,rk3288-dw-hdmi";
1206                 reg = <0xff980000 0x20000>;
1207                 reg-io-width = <4>;
1208                 #sound-dai-cells = <0>;
1209                 rockchip,grf = <&grf>;
1210                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1211                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1212                 clock-names = "iahb", "isfr", "cec";
1213                 power-domains = <&power RK3288_PD_VIO>;
1214                 status = "disabled";
1215
1216                 ports {
1217                         hdmi_in: port {
1218                                 #address-cells = <1>;
1219                                 #size-cells = <0>;
1220                                 hdmi_in_vopb: endpoint@0 {
1221                                         reg = <0>;
1222                                         remote-endpoint = <&vopb_out_hdmi>;
1223                                 };
1224                                 hdmi_in_vopl: endpoint@1 {
1225                                         reg = <1>;
1226                                         remote-endpoint = <&vopl_out_hdmi>;
1227                                 };
1228                         };
1229                 };
1230         };
1231
1232         vpu: video-codec@ff9a0000 {
1233                 compatible = "rockchip,rk3288-vpu";
1234                 reg = <0xff9a0000 0x800>;
1235                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1236                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1237                 interrupt-names = "vepu", "vdpu";
1238                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1239                 clock-names = "aclk", "hclk";
1240                 iommus = <&vpu_mmu>;
1241                 power-domains = <&power RK3288_PD_VIDEO>;
1242         };
1243
1244         vpu_mmu: iommu@ff9a0800 {
1245                 compatible = "rockchip,iommu";
1246                 reg = <0xff9a0800 0x100>;
1247                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1248                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1249                 clock-names = "aclk", "iface";
1250                 #iommu-cells = <0>;
1251                 power-domains = <&power RK3288_PD_VIDEO>;
1252         };
1253
1254         hevc_mmu: iommu@ff9c0440 {
1255                 compatible = "rockchip,iommu";
1256                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1257                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1258                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1259                 clock-names = "aclk", "iface";
1260                 #iommu-cells = <0>;
1261                 status = "disabled";
1262         };
1263
1264         gpu: gpu@ffa30000 {
1265                 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1266                 reg = <0xffa30000 0x10000>;
1267                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1268                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1269                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1270                 interrupt-names = "job", "mmu", "gpu";
1271                 clocks = <&cru ACLK_GPU>;
1272                 operating-points-v2 = <&gpu_opp_table>;
1273                 #cooling-cells = <2>; /* min followed by max */
1274                 power-domains = <&power RK3288_PD_GPU>;
1275                 status = "disabled";
1276         };
1277
1278         gpu_opp_table: opp-table-1 {
1279                 compatible = "operating-points-v2";
1280
1281                 opp-100000000 {
1282                         opp-hz = /bits/ 64 <100000000>;
1283                         opp-microvolt = <950000>;
1284                 };
1285                 opp-200000000 {
1286                         opp-hz = /bits/ 64 <200000000>;
1287                         opp-microvolt = <950000>;
1288                 };
1289                 opp-300000000 {
1290                         opp-hz = /bits/ 64 <300000000>;
1291                         opp-microvolt = <1000000>;
1292                 };
1293                 opp-400000000 {
1294                         opp-hz = /bits/ 64 <400000000>;
1295                         opp-microvolt = <1100000>;
1296                 };
1297                 opp-600000000 {
1298                         opp-hz = /bits/ 64 <600000000>;
1299                         opp-microvolt = <1250000>;
1300                 };
1301         };
1302
1303         qos_gpu_r: qos@ffaa0000 {
1304                 compatible = "rockchip,rk3288-qos", "syscon";
1305                 reg = <0xffaa0000 0x20>;
1306         };
1307
1308         qos_gpu_w: qos@ffaa0080 {
1309                 compatible = "rockchip,rk3288-qos", "syscon";
1310                 reg = <0xffaa0080 0x20>;
1311         };
1312
1313         qos_vio1_vop: qos@ffad0000 {
1314                 compatible = "rockchip,rk3288-qos", "syscon";
1315                 reg = <0xffad0000 0x20>;
1316         };
1317
1318         qos_vio1_isp_w0: qos@ffad0100 {
1319                 compatible = "rockchip,rk3288-qos", "syscon";
1320                 reg = <0xffad0100 0x20>;
1321         };
1322
1323         qos_vio1_isp_w1: qos@ffad0180 {
1324                 compatible = "rockchip,rk3288-qos", "syscon";
1325                 reg = <0x0 0xffad0180 0x0 0x20>;
1326         };
1327
1328         qos_vio0_vop: qos@ffad0400 {
1329                 compatible = "rockchip,rk3288-qos", "syscon";
1330                 reg = <0x0 0xffad0400 0x0 0x20>;
1331         };
1332
1333         qos_vio0_vip: qos@ffad0480 {
1334                 compatible = "rockchip,rk3288-qos", "syscon";
1335                 reg = <0xffad0480 0x20>;
1336         };
1337
1338         qos_vio0_iep: qos@ffad0500 {
1339                 compatible = "rockchip,rk3288-qos", "syscon";
1340                 reg = <0xffad0500 0x20>;
1341         };
1342
1343         qos_vio2_rga_r: qos@ffad0800 {
1344                 compatible = "rockchip,rk3288-qos", "syscon";
1345                 reg = <0xffad0800 0x20>;
1346         };
1347
1348         qos_vio2_rga_w: qos@ffad0880 {
1349                 compatible = "rockchip,rk3288-qos", "syscon";
1350                 reg = <0xffad0880 0x20>;
1351         };
1352
1353         qos_vio1_isp_r: qos@ffad0900 {
1354                 compatible = "rockchip,rk3288-qos", "syscon";
1355                 reg = <0xffad0900 0x20>;
1356         };
1357
1358         qos_video: qos@ffae0000 {
1359                 compatible = "rockchip,rk3288-qos", "syscon";
1360                 reg = <0xffae0000 0x20>;
1361         };
1362
1363         qos_hevc_r: qos@ffaf0000 {
1364                 compatible = "rockchip,rk3288-qos", "syscon";
1365                 reg = <0xffaf0000 0x20>;
1366         };
1367
1368         qos_hevc_w: qos@ffaf0080 {
1369                 compatible = "rockchip,rk3288-qos", "syscon";
1370                 reg = <0xffaf0080 0x20>;
1371         };
1372
1373         dmac_bus_s: dma-controller@ffb20000 {
1374                 compatible = "arm,pl330", "arm,primecell";
1375                 reg = <0xffb20000 0x4000>;
1376                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
1377                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1378                 #dma-cells = <1>;
1379                 arm,pl330-broken-no-flushp;
1380                 arm,pl330-periph-burst;
1381                 clocks = <&cru ACLK_DMAC1>;
1382                 clock-names = "apb_pclk";
1383         };
1384
1385         efuse: efuse@ffb40000 {
1386                 compatible = "rockchip,rk3288-efuse";
1387                 reg = <0xffb40000 0x10000>;
1388                 #address-cells = <1>;
1389                 #size-cells = <1>;
1390                 clocks = <&cru PCLK_EFUSE256>;
1391                 clock-names = "pclk_efuse";
1392
1393                 cpu_id: cpu-id@7 {
1394                         reg = <0x07 0x10>;
1395                 };
1396                 cpu_leakage: cpu_leakage@17 {
1397                         reg = <0x17 0x1>;
1398                 };
1399         };
1400
1401         gic: interrupt-controller@ffc01000 {
1402                 compatible = "arm,gic-400";
1403                 interrupt-controller;
1404                 #interrupt-cells = <3>;
1405                 #address-cells = <0>;
1406
1407                 reg = <0xffc01000 0x1000>,
1408                       <0xffc02000 0x1000>,
1409                       <0xffc04000 0x2000>,
1410                       <0xffc06000 0x2000>;
1411                 interrupts = <GIC_PPI 9 0xf04>;
1412         };
1413
1414         pinctrl: pinctrl {
1415                 compatible = "rockchip,rk3288-pinctrl";
1416                 rockchip,grf = <&grf>;
1417                 rockchip,pmu = <&pmu>;
1418                 #address-cells = <1>;
1419                 #size-cells = <1>;
1420                 ranges;
1421
1422                 gpio0: gpio0@ff750000 {
1423                         compatible = "rockchip,gpio-bank";
1424                         reg = <0xff750000 0x100>;
1425                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1426                         clocks = <&cru PCLK_GPIO0>;
1427
1428                         gpio-controller;
1429                         #gpio-cells = <2>;
1430
1431                         interrupt-controller;
1432                         #interrupt-cells = <2>;
1433                 };
1434
1435                 gpio1: gpio1@ff780000 {
1436                         compatible = "rockchip,gpio-bank";
1437                         reg = <0xff780000 0x100>;
1438                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1439                         clocks = <&cru PCLK_GPIO1>;
1440
1441                         gpio-controller;
1442                         #gpio-cells = <2>;
1443
1444                         interrupt-controller;
1445                         #interrupt-cells = <2>;
1446                 };
1447
1448                 gpio2: gpio2@ff790000 {
1449                         compatible = "rockchip,gpio-bank";
1450                         reg = <0xff790000 0x100>;
1451                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1452                         clocks = <&cru PCLK_GPIO2>;
1453
1454                         gpio-controller;
1455                         #gpio-cells = <2>;
1456
1457                         interrupt-controller;
1458                         #interrupt-cells = <2>;
1459                 };
1460
1461                 gpio3: gpio3@ff7a0000 {
1462                         compatible = "rockchip,gpio-bank";
1463                         reg = <0xff7a0000 0x100>;
1464                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1465                         clocks = <&cru PCLK_GPIO3>;
1466
1467                         gpio-controller;
1468                         #gpio-cells = <2>;
1469
1470                         interrupt-controller;
1471                         #interrupt-cells = <2>;
1472                 };
1473
1474                 gpio4: gpio4@ff7b0000 {
1475                         compatible = "rockchip,gpio-bank";
1476                         reg = <0xff7b0000 0x100>;
1477                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1478                         clocks = <&cru PCLK_GPIO4>;
1479
1480                         gpio-controller;
1481                         #gpio-cells = <2>;
1482
1483                         interrupt-controller;
1484                         #interrupt-cells = <2>;
1485                 };
1486
1487                 gpio5: gpio5@ff7c0000 {
1488                         compatible = "rockchip,gpio-bank";
1489                         reg = <0xff7c0000 0x100>;
1490                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1491                         clocks = <&cru PCLK_GPIO5>;
1492
1493                         gpio-controller;
1494                         #gpio-cells = <2>;
1495
1496                         interrupt-controller;
1497                         #interrupt-cells = <2>;
1498                 };
1499
1500                 gpio6: gpio6@ff7d0000 {
1501                         compatible = "rockchip,gpio-bank";
1502                         reg = <0xff7d0000 0x100>;
1503                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1504                         clocks = <&cru PCLK_GPIO6>;
1505
1506                         gpio-controller;
1507                         #gpio-cells = <2>;
1508
1509                         interrupt-controller;
1510                         #interrupt-cells = <2>;
1511                 };
1512
1513                 gpio7: gpio7@ff7e0000 {
1514                         compatible = "rockchip,gpio-bank";
1515                         reg = <0xff7e0000 0x100>;
1516                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1517                         clocks = <&cru PCLK_GPIO7>;
1518
1519                         gpio-controller;
1520                         #gpio-cells = <2>;
1521
1522                         interrupt-controller;
1523                         #interrupt-cells = <2>;
1524                 };
1525
1526                 gpio8: gpio8@ff7f0000 {
1527                         compatible = "rockchip,gpio-bank";
1528                         reg = <0xff7f0000 0x100>;
1529                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1530                         clocks = <&cru PCLK_GPIO8>;
1531
1532                         gpio-controller;
1533                         #gpio-cells = <2>;
1534
1535                         interrupt-controller;
1536                         #interrupt-cells = <2>;
1537                 };
1538
1539                 hdmi {
1540                         hdmi_cec_c0: hdmi-cec-c0 {
1541                                 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
1542                         };
1543
1544                         hdmi_cec_c7: hdmi-cec-c7 {
1545                                 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
1546                         };
1547
1548                         hdmi_ddc: hdmi-ddc {
1549                                 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
1550                                                 <7 RK_PC4 2 &pcfg_pull_none>;
1551                         };
1552
1553                         hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1554                                 rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
1555                                                 <7 RK_PC4 2 &pcfg_pull_none>;
1556                         };
1557                 };
1558
1559                 pcfg_output_low: pcfg-output-low {
1560                         output-low;
1561                 };
1562
1563                 pcfg_pull_up: pcfg-pull-up {
1564                         bias-pull-up;
1565                 };
1566
1567                 pcfg_pull_down: pcfg-pull-down {
1568                         bias-pull-down;
1569                 };
1570
1571                 pcfg_pull_none: pcfg-pull-none {
1572                         bias-disable;
1573                 };
1574
1575                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1576                         bias-disable;
1577                         drive-strength = <12>;
1578                 };
1579
1580                 suspend {
1581                         global_pwroff: global-pwroff {
1582                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
1583                         };
1584
1585                         ddrio_pwroff: ddrio-pwroff {
1586                                 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
1587                         };
1588
1589                         ddr0_retention: ddr0-retention {
1590                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
1591                         };
1592
1593                         ddr1_retention: ddr1-retention {
1594                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
1595                         };
1596                 };
1597
1598                 edp {
1599                         edp_hpd: edp-hpd {
1600                                 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
1601                         };
1602                 };
1603
1604                 i2c0 {
1605                         i2c0_xfer: i2c0-xfer {
1606                                 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
1607                                                 <0 RK_PC0 1 &pcfg_pull_none>;
1608                         };
1609                 };
1610
1611                 i2c1 {
1612                         i2c1_xfer: i2c1-xfer {
1613                                 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
1614                                                 <8 RK_PA5 1 &pcfg_pull_none>;
1615                         };
1616                 };
1617
1618                 i2c2 {
1619                         i2c2_xfer: i2c2-xfer {
1620                                 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
1621                                                 <6 RK_PB2 1 &pcfg_pull_none>;
1622                         };
1623                 };
1624
1625                 i2c3 {
1626                         i2c3_xfer: i2c3-xfer {
1627                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
1628                                                 <2 RK_PC1 1 &pcfg_pull_none>;
1629                         };
1630                 };
1631
1632                 i2c4 {
1633                         i2c4_xfer: i2c4-xfer {
1634                                 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
1635                                                 <7 RK_PC2 1 &pcfg_pull_none>;
1636                         };
1637                 };
1638
1639                 i2c5 {
1640                         i2c5_xfer: i2c5-xfer {
1641                                 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
1642                                                 <7 RK_PC4 1 &pcfg_pull_none>;
1643                         };
1644                 };
1645
1646                 i2s0 {
1647                         i2s0_bus: i2s0-bus {
1648                                 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
1649                                                 <6 RK_PA1 1 &pcfg_pull_none>,
1650                                                 <6 RK_PA2 1 &pcfg_pull_none>,
1651                                                 <6 RK_PA3 1 &pcfg_pull_none>,
1652                                                 <6 RK_PA4 1 &pcfg_pull_none>,
1653                                                 <6 RK_PB0 1 &pcfg_pull_none>;
1654                         };
1655                 };
1656
1657                 lcdc {
1658                         lcdc_ctl: lcdc-ctl {
1659                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1660                                                 <1 RK_PD1 1 &pcfg_pull_none>,
1661                                                 <1 RK_PD2 1 &pcfg_pull_none>,
1662                                                 <1 RK_PD3 1 &pcfg_pull_none>;
1663                         };
1664                 };
1665
1666                 sdmmc {
1667                         sdmmc_clk: sdmmc-clk {
1668                                 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
1669                         };
1670
1671                         sdmmc_cmd: sdmmc-cmd {
1672                                 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
1673                         };
1674
1675                         sdmmc_cd: sdmmc-cd {
1676                                 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
1677                         };
1678
1679                         sdmmc_bus1: sdmmc-bus1 {
1680                                 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
1681                         };
1682
1683                         sdmmc_bus4: sdmmc-bus4 {
1684                                 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
1685                                                 <6 RK_PC1 1 &pcfg_pull_up>,
1686                                                 <6 RK_PC2 1 &pcfg_pull_up>,
1687                                                 <6 RK_PC3 1 &pcfg_pull_up>;
1688                         };
1689                 };
1690
1691                 sdio0 {
1692                         sdio0_bus1: sdio0-bus1 {
1693                                 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
1694                         };
1695
1696                         sdio0_bus4: sdio0-bus4 {
1697                                 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
1698                                                 <4 RK_PC5 1 &pcfg_pull_up>,
1699                                                 <4 RK_PC6 1 &pcfg_pull_up>,
1700                                                 <4 RK_PC7 1 &pcfg_pull_up>;
1701                         };
1702
1703                         sdio0_cmd: sdio0-cmd {
1704                                 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
1705                         };
1706
1707                         sdio0_clk: sdio0-clk {
1708                                 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
1709                         };
1710
1711                         sdio0_cd: sdio0-cd {
1712                                 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
1713                         };
1714
1715                         sdio0_wp: sdio0-wp {
1716                                 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
1717                         };
1718
1719                         sdio0_pwr: sdio0-pwr {
1720                                 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
1721                         };
1722
1723                         sdio0_bkpwr: sdio0-bkpwr {
1724                                 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
1725                         };
1726
1727                         sdio0_int: sdio0-int {
1728                                 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
1729                         };
1730                 };
1731
1732                 sdio1 {
1733                         sdio1_bus1: sdio1-bus1 {
1734                                 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
1735                         };
1736
1737                         sdio1_bus4: sdio1-bus4 {
1738                                 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
1739                                                 <3 RK_PD1 4 &pcfg_pull_up>,
1740                                                 <3 RK_PD2 4 &pcfg_pull_up>,
1741                                                 <3 RK_PD3 4 &pcfg_pull_up>;
1742                         };
1743
1744                         sdio1_cd: sdio1-cd {
1745                                 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
1746                         };
1747
1748                         sdio1_wp: sdio1-wp {
1749                                 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
1750                         };
1751
1752                         sdio1_bkpwr: sdio1-bkpwr {
1753                                 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
1754                         };
1755
1756                         sdio1_int: sdio1-int {
1757                                 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
1758                         };
1759
1760                         sdio1_cmd: sdio1-cmd {
1761                                 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
1762                         };
1763
1764                         sdio1_clk: sdio1-clk {
1765                                 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
1766                         };
1767
1768                         sdio1_pwr: sdio1-pwr {
1769                                 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
1770                         };
1771                 };
1772
1773                 emmc {
1774                         emmc_clk: emmc-clk {
1775                                 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
1776                         };
1777
1778                         emmc_cmd: emmc-cmd {
1779                                 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
1780                         };
1781
1782                         emmc_pwr: emmc-pwr {
1783                                 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
1784                         };
1785
1786                         emmc_bus1: emmc-bus1 {
1787                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
1788                         };
1789
1790                         emmc_bus4: emmc-bus4 {
1791                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1792                                                 <3 RK_PA1 2 &pcfg_pull_up>,
1793                                                 <3 RK_PA2 2 &pcfg_pull_up>,
1794                                                 <3 RK_PA3 2 &pcfg_pull_up>;
1795                         };
1796
1797                         emmc_bus8: emmc-bus8 {
1798                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1799                                                 <3 RK_PA1 2 &pcfg_pull_up>,
1800                                                 <3 RK_PA2 2 &pcfg_pull_up>,
1801                                                 <3 RK_PA3 2 &pcfg_pull_up>,
1802                                                 <3 RK_PA4 2 &pcfg_pull_up>,
1803                                                 <3 RK_PA5 2 &pcfg_pull_up>,
1804                                                 <3 RK_PA6 2 &pcfg_pull_up>,
1805                                                 <3 RK_PA7 2 &pcfg_pull_up>;
1806                         };
1807                 };
1808
1809                 spi0 {
1810                         spi0_clk: spi0-clk {
1811                                 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
1812                         };
1813                         spi0_cs0: spi0-cs0 {
1814                                 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
1815                         };
1816                         spi0_tx: spi0-tx {
1817                                 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
1818                         };
1819                         spi0_rx: spi0-rx {
1820                                 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
1821                         };
1822                         spi0_cs1: spi0-cs1 {
1823                                 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
1824                         };
1825                 };
1826                 spi1 {
1827                         spi1_clk: spi1-clk {
1828                                 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
1829                         };
1830                         spi1_cs0: spi1-cs0 {
1831                                 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
1832                         };
1833                         spi1_rx: spi1-rx {
1834                                 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
1835                         };
1836                         spi1_tx: spi1-tx {
1837                                 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
1838                         };
1839                 };
1840
1841                 spi2 {
1842                         spi2_cs1: spi2-cs1 {
1843                                 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
1844                         };
1845                         spi2_clk: spi2-clk {
1846                                 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
1847                         };
1848                         spi2_cs0: spi2-cs0 {
1849                                 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
1850                         };
1851                         spi2_rx: spi2-rx {
1852                                 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
1853                         };
1854                         spi2_tx: spi2-tx {
1855                                 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
1856                         };
1857                 };
1858
1859                 uart0 {
1860                         uart0_xfer: uart0-xfer {
1861                                 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
1862                                                 <4 RK_PC1 1 &pcfg_pull_none>;
1863                         };
1864
1865                         uart0_cts: uart0-cts {
1866                                 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
1867                         };
1868
1869                         uart0_rts: uart0-rts {
1870                                 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
1871                         };
1872                 };
1873
1874                 uart1 {
1875                         uart1_xfer: uart1-xfer {
1876                                 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
1877                                                 <5 RK_PB1 1 &pcfg_pull_none>;
1878                         };
1879
1880                         uart1_cts: uart1-cts {
1881                                 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
1882                         };
1883
1884                         uart1_rts: uart1-rts {
1885                                 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
1886                         };
1887                 };
1888
1889                 uart2 {
1890                         uart2_xfer: uart2-xfer {
1891                                 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
1892                                                 <7 RK_PC7 1 &pcfg_pull_none>;
1893                         };
1894                         /* no rts / cts for uart2 */
1895                 };
1896
1897                 uart3 {
1898                         uart3_xfer: uart3-xfer {
1899                                 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
1900                                                 <7 RK_PB0 1 &pcfg_pull_none>;
1901                         };
1902
1903                         uart3_cts: uart3-cts {
1904                                 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
1905                         };
1906
1907                         uart3_rts: uart3-rts {
1908                                 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
1909                         };
1910                 };
1911
1912                 uart4 {
1913                         uart4_xfer: uart4-xfer {
1914                                 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
1915                                                 <5 RK_PB6 3 &pcfg_pull_none>;
1916                         };
1917
1918                         uart4_cts: uart4-cts {
1919                                 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
1920                         };
1921
1922                         uart4_rts: uart4-rts {
1923                                 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
1924                         };
1925                 };
1926
1927                 tsadc {
1928                         otp_pin: otp-pin {
1929                                 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1930                         };
1931
1932                         otp_out: otp-out {
1933                                 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
1934                         };
1935                 };
1936
1937                 pwm0 {
1938                         pwm0_pin: pwm0-pin {
1939                                 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
1940                         };
1941                 };
1942
1943                 pwm1 {
1944                         pwm1_pin: pwm1-pin {
1945                                 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
1946                         };
1947                 };
1948
1949                 pwm2 {
1950                         pwm2_pin: pwm2-pin {
1951                                 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
1952                         };
1953                 };
1954
1955                 pwm3 {
1956                         pwm3_pin: pwm3-pin {
1957                                 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
1958                         };
1959                 };
1960
1961                 gmac {
1962                         rgmii_pins: rgmii-pins {
1963                                 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1964                                                 <3 RK_PD7 3 &pcfg_pull_none>,
1965                                                 <3 RK_PD2 3 &pcfg_pull_none>,
1966                                                 <3 RK_PD3 3 &pcfg_pull_none>,
1967                                                 <3 RK_PD4 3 &pcfg_pull_none_12ma>,
1968                                                 <3 RK_PD5 3 &pcfg_pull_none_12ma>,
1969                                                 <3 RK_PD0 3 &pcfg_pull_none_12ma>,
1970                                                 <3 RK_PD1 3 &pcfg_pull_none_12ma>,
1971                                                 <4 RK_PA0 3 &pcfg_pull_none>,
1972                                                 <4 RK_PA5 3 &pcfg_pull_none>,
1973                                                 <4 RK_PA6 3 &pcfg_pull_none>,
1974                                                 <4 RK_PB1 3 &pcfg_pull_none_12ma>,
1975                                                 <4 RK_PA4 3 &pcfg_pull_none_12ma>,
1976                                                 <4 RK_PA1 3 &pcfg_pull_none>,
1977                                                 <4 RK_PA3 3 &pcfg_pull_none>;
1978                         };
1979
1980                         rmii_pins: rmii-pins {
1981                                 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1982                                                 <3 RK_PD7 3 &pcfg_pull_none>,
1983                                                 <3 RK_PD4 3 &pcfg_pull_none>,
1984                                                 <3 RK_PD5 3 &pcfg_pull_none>,
1985                                                 <4 RK_PA0 3 &pcfg_pull_none>,
1986                                                 <4 RK_PA5 3 &pcfg_pull_none>,
1987                                                 <4 RK_PA4 3 &pcfg_pull_none>,
1988                                                 <4 RK_PA1 3 &pcfg_pull_none>,
1989                                                 <4 RK_PA2 3 &pcfg_pull_none>,
1990                                                 <4 RK_PA3 3 &pcfg_pull_none>;
1991                         };
1992                 };
1993
1994                 spdif {
1995                         spdif_tx: spdif-tx {
1996                                 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
1997                         };
1998                 };
1999         };
2000 };