1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power-domain/rk3288.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/video/rk3288.h>
11 #include "skeleton.dtsi"
14 compatible = "rockchip,rk3288";
16 interrupt-parent = <&gic>;
54 enable-method = "rockchip,rk3066-smp";
55 rockchip,pmu = <&pmu>;
59 compatible = "arm,cortex-a12";
77 #cooling-cells = <2>; /* min followed by max */
78 clock-latency = <40000>;
79 clocks = <&cru ARMCLK>;
80 resets = <&cru SRST_CORE0>;
84 compatible = "arm,cortex-a12";
86 resets = <&cru SRST_CORE1>;
90 compatible = "arm,cortex-a12";
92 resets = <&cru SRST_CORE2>;
96 compatible = "arm,cortex-a12";
98 resets = <&cru SRST_CORE3>;
103 compatible = "arm,amba-bus";
104 #address-cells = <1>;
108 dmac_peri: dma-controller@ff250000 {
109 compatible = "arm,pl330", "arm,primecell";
111 reg = <0xff250000 0x4000>;
112 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
113 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&cru ACLK_DMAC2>;
116 clock-names = "apb_pclk";
119 dmac_bus_ns: dma-controller@ff600000 {
120 compatible = "arm,pl330", "arm,primecell";
122 reg = <0xff600000 0x4000>;
123 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&cru ACLK_DMAC1>;
127 clock-names = "apb_pclk";
131 dmac_bus_s: dma-controller@ffb20000 {
132 compatible = "arm,pl330", "arm,primecell";
134 reg = <0xffb20000 0x4000>;
135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&cru ACLK_DMAC1>;
139 clock-names = "apb_pclk";
144 compatible = "fixed-clock";
145 clock-frequency = <24000000>;
146 clock-output-names = "xin24m";
151 arm,use-physical-timer;
152 compatible = "arm,armv7-timer";
153 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
154 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
155 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
156 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
157 clock-frequency = <24000000>;
162 compatible = "rockchip,display-subsystem";
163 ports = <&vopl_out>, <&vopb_out>;
166 sdmmc: dwmmc@ff0c0000 {
167 compatible = "rockchip,rk3288-dw-mshc";
168 max-frequency = <150000000>;
169 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
170 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
171 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
172 fifo-depth = <0x100>;
173 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
174 reg = <0xff0c0000 0x4000>;
178 sdio0: dwmmc@ff0d0000 {
179 compatible = "rockchip,rk3288-dw-mshc";
180 max-frequency = <150000000>;
181 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
182 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
183 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
184 fifo-depth = <0x100>;
185 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
186 reg = <0xff0d0000 0x4000>;
190 sdio1: dwmmc@ff0e0000 {
191 compatible = "rockchip,rk3288-dw-mshc";
192 max-frequency = <150000000>;
193 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
194 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
195 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
196 fifo-depth = <0x100>;
197 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
198 reg = <0xff0e0000 0x4000>;
202 emmc: dwmmc@ff0f0000 {
203 compatible = "rockchip,rk3288-dw-mshc";
204 max-frequency = <150000000>;
205 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
206 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
207 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
208 fifo-depth = <0x100>;
209 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
210 reg = <0xff0f0000 0x4000>;
214 saradc: saradc@ff100000 {
215 compatible = "rockchip,saradc";
216 reg = <0xff100000 0x100>;
217 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
218 #io-channel-cells = <1>;
219 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
220 clock-names = "saradc", "apb_pclk";
225 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
226 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
227 clock-names = "spiclk", "apb_pclk";
228 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
229 dma-names = "tx", "rx";
230 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
233 reg = <0xff110000 0x1000>;
234 #address-cells = <1>;
240 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
241 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
242 clock-names = "spiclk", "apb_pclk";
243 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
244 dma-names = "tx", "rx";
245 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
248 reg = <0xff120000 0x1000>;
249 #address-cells = <1>;
255 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
256 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
257 clock-names = "spiclk", "apb_pclk";
258 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
259 dma-names = "tx", "rx";
260 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
261 pinctrl-names = "default";
262 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
263 reg = <0xff130000 0x1000>;
264 #address-cells = <1>;
270 compatible = "rockchip,rk3288-i2c";
271 reg = <0xff140000 0x1000>;
272 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
273 #address-cells = <1>;
276 clocks = <&cru PCLK_I2C1>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&i2c1_xfer>;
283 compatible = "rockchip,rk3288-i2c";
284 reg = <0xff150000 0x1000>;
285 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
286 #address-cells = <1>;
289 clocks = <&cru PCLK_I2C3>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&i2c3_xfer>;
296 compatible = "rockchip,rk3288-i2c";
297 reg = <0xff160000 0x1000>;
298 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
299 #address-cells = <1>;
302 clocks = <&cru PCLK_I2C4>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&i2c4_xfer>;
309 compatible = "rockchip,rk3288-i2c";
310 reg = <0xff170000 0x1000>;
311 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
312 #address-cells = <1>;
315 clocks = <&cru PCLK_I2C5>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&i2c5_xfer>;
320 uart0: serial@ff180000 {
321 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
322 reg = <0xff180000 0x100>;
323 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
326 clock-frequency = <24000000>;
327 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
328 clock-names = "baudclk", "apb_pclk";
329 pinctrl-names = "default";
330 pinctrl-0 = <&uart0_xfer>;
334 uart1: serial@ff190000 {
335 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
336 reg = <0xff190000 0x100>;
337 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
340 clock-frequency = <24000000>;
341 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
342 clock-names = "baudclk", "apb_pclk";
343 pinctrl-names = "default";
344 pinctrl-0 = <&uart1_xfer>;
348 uart2: serial@ff690000 {
349 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
350 reg = <0xff690000 0x100>;
351 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
354 clock-frequency = <24000000>;
355 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
356 clock-names = "baudclk", "apb_pclk";
357 pinctrl-names = "default";
358 pinctrl-0 = <&uart2_xfer>;
361 uart3: serial@ff1b0000 {
362 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
363 reg = <0xff1b0000 0x100>;
364 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
367 clock-frequency = <24000000>;
368 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
369 clock-names = "baudclk", "apb_pclk";
370 pinctrl-names = "default";
371 pinctrl-0 = <&uart3_xfer>;
375 uart4: serial@ff1c0000 {
376 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
377 reg = <0xff1c0000 0x100>;
378 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
381 clock-frequency = <24000000>;
382 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
383 clock-names = "baudclk", "apb_pclk";
384 pinctrl-names = "default";
385 pinctrl-0 = <&uart4_xfer>;
388 thermal: thermal-zones {
389 #include "rk3288-thermal.dtsi"
392 tsadc: tsadc@ff280000 {
393 compatible = "rockchip,rk3288-tsadc";
394 reg = <0xff280000 0x100>;
395 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
397 clock-names = "tsadc", "apb_pclk";
398 resets = <&cru SRST_TSADC>;
399 reset-names = "tsadc-apb";
400 pinctrl-names = "otp_out";
401 pinctrl-0 = <&otp_out>;
402 #thermal-sensor-cells = <1>;
403 hw-shut-temp = <125000>;
407 gmac: ethernet@ff290000 {
408 compatible = "rockchip,rk3288-gmac";
409 reg = <0xff290000 0x10000>;
410 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
411 interrupt-names = "macirq";
412 rockchip,grf = <&grf>;
413 clocks = <&cru SCLK_MAC>,
414 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
415 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
416 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
417 clock-names = "stmmaceth",
418 "mac_clk_rx", "mac_clk_tx",
419 "clk_mac_ref", "clk_mac_refout",
420 "aclk_mac", "pclk_mac";
423 usb_host0_ehci: usb@ff500000 {
424 compatible = "generic-ehci";
425 reg = <0xff500000 0x100>;
426 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&cru HCLK_USBHOST0>;
428 clock-names = "usbhost";
434 /* NOTE: doesn't work on RK3288, but fixed on RK3288W */
435 usb_host0_ohci: usb@ff520000 {
436 compatible = "generic-ohci";
437 reg = <0x0 0xff520000 0x0 0x100>;
438 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&cru HCLK_USBHOST0>;
445 usb_host1: usb@ff540000 {
446 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
448 reg = <0xff540000 0x40000>;
449 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&cru HCLK_USBHOST1>;
453 phy-names = "usb2-phy";
457 usb_otg: usb@ff580000 {
458 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
460 reg = <0xff580000 0x40000>;
461 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&cru HCLK_OTG0>;
466 phy-names = "usb2-phy";
470 usb_hsic: usb@ff5c0000 {
471 compatible = "generic-ehci";
472 reg = <0xff5c0000 0x100>;
473 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&cru HCLK_HSIC>;
475 clock-names = "usbhost";
480 compatible = "rockchip,rk3288-dmc", "syscon";
481 rockchip,cru = <&cru>;
482 rockchip,grf = <&grf>;
483 rockchip,pmu = <&pmu>;
484 rockchip,sgrf = <&sgrf>;
485 rockchip,noc = <&noc>;
486 reg = <0xff610000 0x3fc
490 rockchip,sram = <&ddr_sram>;
491 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
492 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
494 clock-names = "pclk_ddrupctl0", "pclk_publ0",
495 "pclk_ddrupctl1", "pclk_publ1",
500 compatible = "rockchip,rk3288-i2c";
501 reg = <0xff650000 0x1000>;
502 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
503 #address-cells = <1>;
506 clocks = <&cru PCLK_I2C0>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2c0_xfer>;
513 compatible = "rockchip,rk3288-i2c";
514 reg = <0xff660000 0x1000>;
515 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
516 #address-cells = <1>;
519 clocks = <&cru PCLK_I2C2>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c2_xfer>;
526 compatible = "rockchip,rk3288-pwm";
527 reg = <0xff680000 0x10>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&pwm0_pin>;
531 clocks = <&cru PCLK_PWM>;
533 rockchip,grf = <&grf>;
538 compatible = "rockchip,rk3288-pwm";
539 reg = <0xff680010 0x10>;
541 pinctrl-names = "default";
542 pinctrl-0 = <&pwm1_pin>;
543 clocks = <&cru PCLK_PWM>;
545 rockchip,grf = <&grf>;
550 compatible = "rockchip,rk3288-pwm";
551 reg = <0xff680020 0x10>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&pwm2_pin>;
555 clocks = <&cru PCLK_PWM>;
557 rockchip,grf = <&grf>;
562 compatible = "rockchip,rk3288-pwm";
563 reg = <0xff680030 0x10>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&pwm3_pin>;
567 clocks = <&cru PCLK_PWM>;
569 rockchip,grf = <&grf>;
573 bus_intmem@ff700000 {
574 compatible = "mmio-sram";
575 reg = <0xff700000 0x18000>;
576 #address-cells = <1>;
578 ranges = <0 0xff700000 0x18000>;
580 compatible = "rockchip,rk3066-smp-sram";
583 ddr_sram: ddr-sram@1000 {
584 compatible = "rockchip,rk3288-ddr-sram";
585 reg = <0x1000 0x4000>;
590 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
591 reg = <0xff720000 0x1000>;
594 pmu: power-management@ff730000 {
595 compatible = "rockchip,rk3288-pmu", "syscon";
596 reg = <0xff730000 0x100>;
599 sgrf: syscon@ff740000 {
600 compatible = "rockchip,rk3288-sgrf", "syscon";
601 reg = <0xff740000 0x1000>;
604 cru: clock-controller@ff760000 {
605 compatible = "rockchip,rk3288-cru";
606 reg = <0xff760000 0x1000>;
607 rockchip,grf = <&grf>;
610 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
611 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
612 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
613 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
615 assigned-clock-rates = <594000000>, <400000000>,
616 <500000000>, <300000000>,
617 <150000000>, <75000000>,
618 <300000000>, <150000000>,
622 grf: syscon@ff770000 {
623 compatible = "rockchip,rk3288-grf", "syscon";
624 reg = <0xff770000 0x1000>;
627 wdt: watchdog@ff800000 {
628 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
629 reg = <0xff800000 0x100>;
630 clocks = <&cru PCLK_WDT>;
631 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
635 spdif: sound@ff88b0000 {
636 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
637 reg = <0xff8b0000 0x10000>;
638 #sound-dai-cells = <0>;
639 clock-names = "hclk", "mclk";
640 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
641 dmas = <&dmac_bus_s 3>;
643 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
644 pinctrl-names = "default";
645 pinctrl-0 = <&spdif_tx>;
646 rockchip,grf = <&grf>;
651 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
652 reg = <0xff890000 0x10000>;
653 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
654 #address-cells = <1>;
656 #sound-dai-cells = <1>;
657 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
658 dma-names = "tx", "rx";
659 clock-names = "i2s_hclk", "i2s_clk";
660 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
661 pinctrl-names = "default";
662 pinctrl-0 = <&i2s0_bus>;
667 compatible = "rockchip,rk3288-vop";
668 reg = <0xff930000 0x19c>;
669 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
671 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
672 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
673 reset-names = "axi", "ahb", "dclk";
674 iommus = <&vopb_mmu>;
675 power-domains = <&power RK3288_PD_VIO>;
678 #address-cells = <1>;
680 vopb_out_edp: endpoint@0 {
682 remote-endpoint = <&edp_in_vopb>;
684 vopb_out_hdmi: endpoint@1 {
686 remote-endpoint = <&hdmi_in_vopb>;
688 vopb_out_lvds: endpoint@2 {
690 remote-endpoint = <&lvds_in_vopb>;
692 vopb_out_mipi: endpoint@3 {
694 remote-endpoint = <&mipi_in_vopb>;
700 vopb_mmu: iommu@ff930300 {
701 compatible = "rockchip,iommu";
702 reg = <0xff930300 0x100>;
703 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
704 interrupt-names = "vopb_mmu";
705 power-domains = <&power RK3288_PD_VIO>;
711 compatible = "rockchip,rk3288-vop";
712 reg = <0xff940000 0x19c>;
713 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
715 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
716 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
717 reset-names = "axi", "ahb", "dclk";
718 iommus = <&vopl_mmu>;
719 power-domains = <&power RK3288_PD_VIO>;
722 #address-cells = <1>;
724 vopl_out_edp: endpoint@0 {
726 remote-endpoint = <&edp_in_vopl>;
728 vopl_out_hdmi: endpoint@1 {
730 remote-endpoint = <&hdmi_in_vopl>;
732 vopl_out_lvds: endpoint@2 {
734 remote-endpoint = <&lvds_in_vopl>;
736 vopl_out_mipi: endpoint@3 {
738 remote-endpoint = <&mipi_in_vopl>;
744 vopl_mmu: iommu@ff940300 {
745 compatible = "rockchip,iommu";
746 reg = <0xff940300 0x100>;
747 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
748 interrupt-names = "vopl_mmu";
749 power-domains = <&power RK3288_PD_VIO>;
755 compatible = "rockchip,rk3288-edp";
756 reg = <0xff970000 0x4000>;
757 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
759 rockchip,grf = <&grf>;
760 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
763 power-domains = <&power RK3288_PD_VIO>;
767 #address-cells = <1>;
769 edp_in_vopb: endpoint@0 {
771 remote-endpoint = <&vopb_out_edp>;
773 edp_in_vopl: endpoint@1 {
775 remote-endpoint = <&vopl_out_edp>;
781 hdmi: hdmi@ff980000 {
782 compatible = "rockchip,rk3288-dw-hdmi";
783 reg = <0xff980000 0x20000>;
785 ddc-i2c-bus = <&i2c5>;
786 rockchip,grf = <&grf>;
787 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
789 clock-names = "iahb", "isfr";
793 #address-cells = <1>;
795 hdmi_in_vopb: endpoint@0 {
797 remote-endpoint = <&vopb_out_hdmi>;
799 hdmi_in_vopl: endpoint@1 {
801 remote-endpoint = <&vopl_out_hdmi>;
807 lvds: lvds@ff96c000 {
808 compatible = "rockchip,rk3288-lvds";
809 reg = <0xff96c000 0x4000>;
810 clocks = <&cru PCLK_LVDS_PHY>;
811 clock-names = "pclk_lvds";
812 pinctrl-names = "default";
813 pinctrl-0 = <&lcdc0_ctl>;
814 rockchip,grf = <&grf>;
817 #address-cells = <1>;
821 #address-cells = <1>;
823 lvds_in_vopb: endpoint@0 {
825 remote-endpoint = <&vopb_out_lvds>;
827 lvds_in_vopl: endpoint@1 {
829 remote-endpoint = <&vopl_out_lvds>;
835 mipi_dsi0: mipi@ff960000 {
836 compatible = "rockchip,rk3288_mipi_dsi";
837 reg = <0xff960000 0x4000>;
838 clocks = <&cru PCLK_MIPI_DSI0>;
839 clock-names = "pclk_mipi";
840 /*pinctrl-names = "default";
841 pinctrl-0 = <&lcdc0_ctl>;*/
842 rockchip,grf = <&grf>;
843 #address-cells = <1>;
849 #address-cells = <1>;
851 mipi_in_vopb: endpoint@0 {
853 remote-endpoint = <&vopb_out_mipi>;
855 mipi_in_vopl: endpoint@1 {
857 remote-endpoint = <&vopl_out_mipi>;
863 hdmi_audio: hdmi_audio {
864 compatible = "rockchip,rk3288-hdmi-audio";
865 i2s-controller = <&i2s>;
869 vpu: video-codec@ff9a0000 {
870 compatible = "rockchip,rk3288-vpu";
871 reg = <0xff9a0000 0x800>;
872 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
873 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
874 interrupt-names = "vepu", "vdpu";
875 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
876 clock-names = "aclk_vcodec", "hclk_vcodec";
877 power-domains = <&power RK3288_PD_VIDEO>;
881 vpu_mmu: iommu@ff9a0800 {
882 compatible = "rockchip,iommu";
883 reg = <0xff9a0800 0x100>;
884 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
885 interrupt-names = "vpu_mmu";
886 power-domains = <&power RK3288_PD_VIDEO>;
891 compatible = "arm,malit764",
895 reg = <0xffa30000 0x10000>;
896 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
897 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
899 interrupt-names = "JOB", "MMU", "GPU";
900 clocks = <&cru ACLK_GPU>;
901 clock-names = "aclk_gpu";
908 /* 500000 1200000 - See crosbug.com/p/33857 */
911 power-domains = <&power RK3288_PD_GPU>;
915 noc: syscon@ffac0000 {
916 compatible = "rockchip,rk3288-noc", "syscon";
917 reg = <0xffac0000 0x2000>;
920 efuse: efuse@ffb40000 {
921 compatible = "rockchip,rk3288-efuse";
922 reg = <0xffb40000 0x10000>;
926 gic: interrupt-controller@ffc01000 {
927 compatible = "arm,gic-400";
928 interrupt-controller;
929 #interrupt-cells = <3>;
930 #address-cells = <0>;
932 reg = <0xffc01000 0x1000>,
936 interrupts = <GIC_PPI 9 0xf04>;
940 compatible = "rockchip,rk3288-cpuidle";
944 compatible = "rockchip,rk3288-usb-phy";
945 rockchip,grf = <&grf>;
946 #address-cells = <1>;
953 clocks = <&cru SCLK_OTGPHY0>;
954 clock-names = "phyclk";
960 clocks = <&cru SCLK_OTGPHY1>;
961 clock-names = "phyclk";
967 clocks = <&cru SCLK_OTGPHY2>;
968 clock-names = "phyclk";
973 compatible = "rockchip,rk3288-pinctrl";
974 rockchip,grf = <&grf>;
975 rockchip,pmu = <&pmu>;
976 #address-cells = <1>;
980 gpio0: gpio0@ff750000 {
981 compatible = "rockchip,gpio-bank";
982 reg = <0xff750000 0x100>;
983 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&cru PCLK_GPIO0>;
989 interrupt-controller;
990 #interrupt-cells = <2>;
993 gpio1: gpio1@ff780000 {
994 compatible = "rockchip,gpio-bank";
995 reg = <0xff780000 0x100>;
996 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&cru PCLK_GPIO1>;
1002 interrupt-controller;
1003 #interrupt-cells = <2>;
1006 gpio2: gpio2@ff790000 {
1007 compatible = "rockchip,gpio-bank";
1008 reg = <0xff790000 0x100>;
1009 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&cru PCLK_GPIO2>;
1015 interrupt-controller;
1016 #interrupt-cells = <2>;
1019 gpio3: gpio3@ff7a0000 {
1020 compatible = "rockchip,gpio-bank";
1021 reg = <0xff7a0000 0x100>;
1022 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&cru PCLK_GPIO3>;
1028 interrupt-controller;
1029 #interrupt-cells = <2>;
1032 gpio4: gpio4@ff7b0000 {
1033 compatible = "rockchip,gpio-bank";
1034 reg = <0xff7b0000 0x100>;
1035 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&cru PCLK_GPIO4>;
1041 interrupt-controller;
1042 #interrupt-cells = <2>;
1045 gpio5: gpio5@ff7c0000 {
1046 compatible = "rockchip,gpio-bank";
1047 reg = <0xff7c0000 0x100>;
1048 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&cru PCLK_GPIO5>;
1054 interrupt-controller;
1055 #interrupt-cells = <2>;
1058 gpio6: gpio6@ff7d0000 {
1059 compatible = "rockchip,gpio-bank";
1060 reg = <0xff7d0000 0x100>;
1061 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1062 clocks = <&cru PCLK_GPIO6>;
1067 interrupt-controller;
1068 #interrupt-cells = <2>;
1071 gpio7: gpio7@ff7e0000 {
1072 compatible = "rockchip,gpio-bank";
1073 reg = <0xff7e0000 0x100>;
1074 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1075 clocks = <&cru PCLK_GPIO7>;
1080 interrupt-controller;
1081 #interrupt-cells = <2>;
1084 gpio8: gpio8@ff7f0000 {
1085 compatible = "rockchip,gpio-bank";
1086 reg = <0xff7f0000 0x100>;
1087 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&cru PCLK_GPIO8>;
1093 interrupt-controller;
1094 #interrupt-cells = <2>;
1098 hdmi_cec_c0: hdmi-cec-c0 {
1099 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
1103 pcfg_pull_up: pcfg-pull-up {
1107 pcfg_pull_down: pcfg-pull-down {
1111 pcfg_pull_none: pcfg-pull-none {
1115 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1117 drive-strength = <12>;
1121 global_pwroff: global-pwroff {
1122 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1125 ddrio_pwroff: ddrio-pwroff {
1126 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1129 ddr0_retention: ddr0-retention {
1130 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1133 ddr1_retention: ddr1-retention {
1134 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1139 i2c0_xfer: i2c0-xfer {
1140 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1141 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1146 i2c1_xfer: i2c1-xfer {
1147 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1148 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1153 i2c2_xfer: i2c2-xfer {
1154 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1155 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1160 i2c3_xfer: i2c3-xfer {
1161 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1162 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1167 i2c4_xfer: i2c4-xfer {
1168 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1169 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1174 i2c5_xfer: i2c5-xfer {
1175 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1176 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1181 i2s0_bus: i2s0-bus {
1182 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1183 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1184 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1185 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1186 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1187 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1192 lcdc0_ctl: lcdc0-ctl {
1193 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1194 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1195 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1196 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1201 sdmmc_clk: sdmmc-clk {
1202 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1205 sdmmc_cmd: sdmmc-cmd {
1206 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1209 sdmmc_cd: sdmcc-cd {
1210 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1213 sdmmc_bus1: sdmmc-bus1 {
1214 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1217 sdmmc_bus4: sdmmc-bus4 {
1218 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1219 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1220 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1221 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1226 sdio0_bus1: sdio0-bus1 {
1227 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1230 sdio0_bus4: sdio0-bus4 {
1231 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1232 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1233 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1234 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1237 sdio0_cmd: sdio0-cmd {
1238 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1241 sdio0_clk: sdio0-clk {
1242 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1245 sdio0_cd: sdio0-cd {
1246 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1249 sdio0_wp: sdio0-wp {
1250 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1253 sdio0_pwr: sdio0-pwr {
1254 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1257 sdio0_bkpwr: sdio0-bkpwr {
1258 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1261 sdio0_int: sdio0-int {
1262 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1267 sdio1_bus1: sdio1-bus1 {
1268 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
1271 sdio1_bus4: sdio1-bus4 {
1272 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
1273 <3 25 RK_FUNC_4 &pcfg_pull_up>,
1274 <3 26 RK_FUNC_4 &pcfg_pull_up>,
1275 <3 27 RK_FUNC_4 &pcfg_pull_up>;
1278 sdio1_cd: sdio1-cd {
1279 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
1282 sdio1_wp: sdio1-wp {
1283 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
1286 sdio1_bkpwr: sdio1-bkpwr {
1287 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
1290 sdio1_int: sdio1-int {
1291 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
1294 sdio1_cmd: sdio1-cmd {
1295 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
1298 sdio1_clk: sdio1-clk {
1299 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
1302 sdio1_pwr: sdio1-pwr {
1303 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
1308 emmc_clk: emmc-clk {
1309 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1312 emmc_cmd: emmc-cmd {
1313 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1316 emmc_pwr: emmc-pwr {
1317 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1320 emmc_bus1: emmc-bus1 {
1321 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1324 emmc_bus4: emmc-bus4 {
1325 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1326 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1327 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1328 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1331 emmc_bus8: emmc-bus8 {
1332 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1333 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1334 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1335 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1336 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1337 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1338 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1339 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1344 spi0_clk: spi0-clk {
1345 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1347 spi0_cs0: spi0-cs0 {
1348 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1351 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1354 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1356 spi0_cs1: spi0-cs1 {
1357 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1361 spi1_clk: spi1-clk {
1362 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1364 spi1_cs0: spi1-cs0 {
1365 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1368 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1371 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1376 spi2_cs1: spi2-cs1 {
1377 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1379 spi2_clk: spi2-clk {
1380 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1382 spi2_cs0: spi2-cs0 {
1383 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1386 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1389 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1394 uart0_xfer: uart0-xfer {
1395 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1396 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1399 uart0_cts: uart0-cts {
1400 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1403 uart0_rts: uart0-rts {
1404 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1409 uart1_xfer: uart1-xfer {
1410 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1411 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1414 uart1_cts: uart1-cts {
1415 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1418 uart1_rts: uart1-rts {
1419 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1424 uart2_xfer: uart2-xfer {
1425 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1426 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1428 /* no rts / cts for uart2 */
1432 uart3_xfer: uart3-xfer {
1433 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1434 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1437 uart3_cts: uart3-cts {
1438 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1441 uart3_rts: uart3-rts {
1442 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1447 uart4_xfer: uart4-xfer {
1448 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1449 <5 13 3 &pcfg_pull_none>;
1452 uart4_cts: uart4-cts {
1453 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1456 uart4_rts: uart4-rts {
1457 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1463 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1468 pwm0_pin: pwm0-pin {
1469 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1474 pwm1_pin: pwm1-pin {
1475 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1480 pwm2_pin: pwm2-pin {
1481 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
1486 pwm3_pin: pwm3-pin {
1487 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
1492 rgmii_pins: rgmii-pins {
1493 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1494 <3 31 3 &pcfg_pull_none>,
1495 <3 26 3 &pcfg_pull_none>,
1496 <3 27 3 &pcfg_pull_none>,
1497 <3 28 3 &pcfg_pull_none_12ma>,
1498 <3 29 3 &pcfg_pull_none_12ma>,
1499 <3 24 3 &pcfg_pull_none_12ma>,
1500 <3 25 3 &pcfg_pull_none_12ma>,
1501 <4 0 3 &pcfg_pull_none>,
1502 <4 5 3 &pcfg_pull_none>,
1503 <4 6 3 &pcfg_pull_none>,
1504 <4 9 3 &pcfg_pull_none_12ma>,
1505 <4 4 3 &pcfg_pull_none_12ma>,
1506 <4 1 3 &pcfg_pull_none>,
1507 <4 3 3 &pcfg_pull_none>;
1510 rmii_pins: rmii-pins {
1511 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1512 <3 31 3 &pcfg_pull_none>,
1513 <3 28 3 &pcfg_pull_none>,
1514 <3 29 3 &pcfg_pull_none>,
1515 <4 0 3 &pcfg_pull_none>,
1516 <4 5 3 &pcfg_pull_none>,
1517 <4 4 3 &pcfg_pull_none>,
1518 <4 1 3 &pcfg_pull_none>,
1519 <4 2 3 &pcfg_pull_none>,
1520 <4 3 3 &pcfg_pull_none>;
1525 spdif_tx: spdif-tx {
1526 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1531 power: power-controller {
1532 compatible = "rockchip,rk3288-power-controller";
1533 #power-domain-cells = <1>;
1534 rockchip,pmu = <&pmu>;
1535 #address-cells = <1>;
1539 reg = <RK3288_PD_GPU>;
1540 clocks = <&cru ACLK_GPU>;
1544 reg = <RK3288_PD_HEVC>;
1545 clocks = <&cru ACLK_HEVC>,
1546 <&cru SCLK_HEVC_CABAC>,
1547 <&cru SCLK_HEVC_CORE>,
1552 reg = <RK3288_PD_VIO>;
1553 clocks = <&cru ACLK_IEP>,
1567 <&cru PCLK_EDP_CTRL>,
1568 <&cru PCLK_HDMI_CTRL>,
1569 <&cru PCLK_LVDS_PHY>,
1570 <&cru PCLK_MIPI_CSI>,
1571 <&cru PCLK_MIPI_DSI0>,
1572 <&cru PCLK_MIPI_DSI1>,
1573 <&cru SCLK_EDP_24M>,
1575 <&cru SCLK_HDMI_CEC>,
1576 <&cru SCLK_HDMI_HDCP>,
1577 <&cru SCLK_ISP_JPE>,
1583 reg = <RK3288_PD_VIDEO>;
1584 clocks = <&cru ACLK_VCODEC>,