2 * Device tree file for Phytec phyCORE-RK3288 SoM
3 * Copyright (C) 2017 PHYTEC Messtechnik GmbH
4 * Author: Wadim Egorov <w.egorov@phytec.de>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/net/ti-dp83867.h>
46 #include "rk3288.dtsi"
49 model = "Phytec RK3288 phyCORE";
50 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
53 * Set the minimum memory size here and
54 * let the bootloader set the real size.
57 device_type = "memory";
64 eeprom0 = &i2c_eeprom_id;
67 ext_gmac: external-gmac-clock {
68 compatible = "fixed-clock";
70 clock-frequency = <125000000>;
71 clock-output-names = "ext_gmac";
74 io_domains: io_domains {
75 compatible = "rockchip,rk3288-io-voltage-domain";
78 sdcard-supply = <&vdd_io_sd>;
79 flash0-supply = <&vdd_emmc_io>;
80 flash1-supply = <&vdd_misc_1v8>;
81 gpio1830-supply = <&vdd_3v3_io>;
82 gpio30-supply = <&vdd_3v3_io>;
83 bb-supply = <&vdd_3v3_io>;
84 dvp-supply = <&vdd_3v3_io>;
85 lcdc-supply = <&vdd_3v3_io>;
86 wifi-supply = <&vdd_3v3_io>;
87 audio-supply = <&vdd_3v3_io>;
91 compatible = "gpio-leds";
92 pinctrl-names = "default";
93 pinctrl-0 = <&user_led>;
97 gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
98 linux,default-trigger = "heartbeat";
99 default-state = "keep";
103 vdd_emmc_io: vdd-emmc-io {
104 compatible = "regulator-fixed";
105 regulator-name = "vdd_emmc_io";
106 regulator-min-microvolt = <1800000>;
107 regulator-max-microvolt = <1800000>;
108 vin-supply = <&vdd_3v3_io>;
111 vdd_in_otg_out: vdd-in-otg-out {
112 compatible = "regulator-fixed";
113 regulator-name = "vdd_in_otg_out";
116 regulator-min-microvolt = <5000000>;
117 regulator-max-microvolt = <5000000>;
120 vdd_misc_1v8: vdd-misc-1v8 {
121 compatible = "regulator-fixed";
122 regulator-name = "vdd_misc_1v8";
125 regulator-min-microvolt = <1800000>;
126 regulator-max-microvolt = <1800000>;
131 cpu0-supply = <&vdd_cpu>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
161 vmmc-supply = <&vdd_3v3_io>;
162 vqmmc-supply = <&vdd_emmc_io>;
166 assigned-clocks = <&cru SCLK_MAC>;
167 assigned-clock-parents = <&ext_gmac>;
168 clock_in_out = "input";
169 pinctrl-names = "default";
170 pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>;
171 phy-handle = <&phy0>;
172 phy-supply = <&vdd_eth_2v5>;
173 phy-mode = "rgmii-id";
174 snps,reset-active-low;
175 snps,reset-delays-us = <0 10000 1000000>;
176 snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
181 compatible = "snps,dwmac-mdio";
182 #address-cells = <1>;
185 phy0: ethernet-phy@0 {
186 compatible = "ethernet-phy-ieee802.3-c22";
188 interrupt-parent = <&gpio4>;
189 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
190 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
191 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
192 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
193 enet-phy-lane-no-swap;
199 ddc-i2c-bus = <&i2c5>;
206 clock-frequency = <400000>;
210 compatible = "rockchip,rk818";
212 interrupt-parent = <&gpio0>;
213 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&pmic_int>;
216 rockchip,system-power-controller;
221 vcc1-supply = <&vdd_sys>;
222 vcc2-supply = <&vdd_sys>;
223 vcc3-supply = <&vdd_sys>;
224 vcc4-supply = <&vdd_sys>;
225 boost-supply = <&vdd_in_otg_out>;
226 vcc6-supply = <&vdd_sys>;
227 vcc7-supply = <&vdd_misc_1v8>;
228 vcc8-supply = <&vdd_misc_1v8>;
229 vcc9-supply = <&vdd_3v3_io>;
230 vddio-supply = <&vdd_3v3_io>;
235 regulator-name = "vdd_log";
238 regulator-min-microvolt = <1100000>;
239 regulator-max-microvolt = <1100000>;
240 regulator-state-mem {
241 regulator-off-in-suspend;
246 regulator-name = "vdd_gpu";
249 regulator-min-microvolt = <800000>;
250 regulator-max-microvolt = <1250000>;
251 regulator-state-mem {
252 regulator-on-in-suspend;
253 regulator-suspend-microvolt = <1000000>;
258 regulator-name = "vcc_ddr";
261 regulator-state-mem {
262 regulator-on-in-suspend;
266 vdd_3v3_io: DCDC_REG4 {
267 regulator-name = "vdd_3v3_io";
270 regulator-min-microvolt = <3300000>;
271 regulator-max-microvolt = <3300000>;
272 regulator-state-mem {
273 regulator-on-in-suspend;
274 regulator-suspend-microvolt = <3300000>;
278 vdd_sys: DCDC_BOOST {
279 regulator-name = "vdd_sys";
282 regulator-min-microvolt = <5000000>;
283 regulator-max-microvolt = <5000000>;
284 regulator-state-mem {
285 regulator-on-in-suspend;
286 regulator-suspend-microvolt = <5000000>;
292 regulator-name = "vdd_sd";
295 regulator-state-mem {
296 regulator-off-in-suspend;
301 vdd_eth_2v5: LDO_REG2 {
302 regulator-name = "vdd_eth_2v5";
305 regulator-min-microvolt = <2500000>;
306 regulator-max-microvolt = <2500000>;
307 regulator-state-mem {
308 regulator-on-in-suspend;
309 regulator-suspend-microvolt = <2500000>;
315 regulator-name = "vdd_1v0";
318 regulator-min-microvolt = <1000000>;
319 regulator-max-microvolt = <1000000>;
320 regulator-state-mem {
321 regulator-on-in-suspend;
322 regulator-suspend-microvolt = <1000000>;
327 vdd_1v8_lcd_ldo: LDO_REG4 {
328 regulator-name = "vdd_1v8_lcd_ldo";
331 regulator-min-microvolt = <1800000>;
332 regulator-max-microvolt = <1800000>;
333 regulator-state-mem {
334 regulator-on-in-suspend;
335 regulator-suspend-microvolt = <1800000>;
340 vdd_1v0_lcd: LDO_REG6 {
341 regulator-name = "vdd_1v0_lcd";
344 regulator-min-microvolt = <1000000>;
345 regulator-max-microvolt = <1000000>;
346 regulator-state-mem {
347 regulator-on-in-suspend;
348 regulator-suspend-microvolt = <1000000>;
353 vdd_1v8_ldo: LDO_REG7 {
354 regulator-name = "vdd_1v8_ldo";
357 regulator-min-microvolt = <1800000>;
358 regulator-max-microvolt = <1800000>;
359 regulator-state-mem {
360 regulator-off-in-suspend;
361 regulator-suspend-microvolt = <1800000>;
366 vdd_io_sd: LDO_REG9 {
367 regulator-name = "vdd_io_sd";
370 regulator-min-microvolt = <3300000>;
371 regulator-max-microvolt = <3300000>;
372 regulator-state-mem {
373 regulator-on-in-suspend;
374 regulator-suspend-microvolt = <3300000>;
381 i2c_eeprom: eeprom@50 {
382 compatible = "atmel,24c32";
387 /* M24C32-D Identification page */
388 i2c_eeprom_id: eeprom@58 {
389 compatible = "atmel,24c32";
394 vdd_cpu: regulator@60 {
395 compatible = "fcs,fan53555";
397 fcs,suspend-voltage-selector = <1>;
400 regulator-enable-ramp-delay = <300>;
401 regulator-name = "vdd_cpu";
402 regulator-min-microvolt = <800000>;
403 regulator-max-microvolt = <1430000>;
404 regulator-ramp-delay = <8000>;
405 vin-supply = <&vdd_sys>;
410 pcfg_output_high: pcfg-output-high {
416 * We run eMMC at max speed; bump up drive strength.
417 * We also have external pulls, so disable the internal ones.
420 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>;
424 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>;
427 emmc_bus8: emmc-bus8 {
428 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>,
429 <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
430 <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>,
431 <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>,
432 <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>,
433 <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>,
434 <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>,
435 <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>;
441 rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>;
445 rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
451 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>;
457 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
460 /* Pin for switching state between sleep and non-sleep state */
461 pmic_sleep: pmic-sleep {
462 rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
473 vref-supply = <&vdd_1v8_ldo>;
479 serial_flash: flash@0 {
480 compatible = "micron,n25q128a13", "jedec,spi-nor";
482 spi-max-frequency = <50000000>;
484 #address-cells = <1>;
492 rockchip,hw-tshut-mode = <0>;
493 rockchip,hw-tshut-polarity = <0>;