arch/arm/dts/rk3128.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/pinctrl/rockchip.h>
  10 #include <dt-bindings/clock/rk3128-cru.h>
  11 #include "skeleton.dtsi"
  12
  13 / {
  14         compatible = "rockchip,rk3128";
  15         rockchip,sram = <&sram>;
  16         interrupt-parent = <&gic>;
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 gpio0 = &gpio0;
  22                 gpio1 = &gpio1;
  23                 gpio2 = &gpio2;
  24                 gpio3 = &gpio3;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 i2c2 = &i2c2;
  28                 i2c3 = &i2c3;
  29                 spi0 = &spi0;
  30                 serial0 = &uart0;
  31                 serial1 = &uart1;
  32                 serial2 = &uart2;
  33                 mmc0 = &emmc;
  34                 mmc1 = &sdmmc;
  35         };
  36
  37         memory {
  38                 device_type = "memory";
  39                 reg = <0x60000000 0x40000000>;
  40         };
  41
  42         arm-pmu {
  43                 compatible = "arm,cortex-a7-pmu";
  44                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  45                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  46                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  47                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  48         };
  49
  50         cpus {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53                 enable-method = "rockchip,rk3128-smp";
  54
  55                 cpu0:cpu@0x000 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a7";
  58                         reg = <0x000>;
  59                         operating-points = <
  60                                 /* KHz    uV */
  61                                  816000 1000000
  62                         >;
  63                         #cooling-cells = <2>; /* min followed by max */
  64                         clock-latency = <40000>;
  65                         clocks = <&cru ARMCLK>;
  66                 };
  67
  68                 cpu1:cpu@0x001 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a7";
  71                         reg = <0x001>;
  72                 };
  73
  74                 cpu2:cpu@0x002 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a7";
  77                         reg = <0x002>;
  78                 };
  79
  80                 cpu3:cpu@0x003 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a7";
  83                         reg = <0x003>;
  84                 };
  85         };
  86
  87         cpu_axi_bus: cpu_axi_bus {
  88                 compatible = "rockchip,cpu_axi_bus";
  89                 #address-cells = <1>;
  90                 #size-cells = <1>;
  91                 ranges;
  92
  93                 qos {
  94                         #address-cells = <1>;
  95                         #size-cells = <1>;
  96                         ranges;
  97
  98                         crypto {
  99                                 reg = <0x10128080 0x20>;
 100                         };
 101
 102                         core {
 103                                 reg = <0x1012a000 0x20>;
 104                         };
 105
 106                         peri {
 107                                 reg = <0x1012c000 0x20>;
 108                         };
 109
 110                         gpu {
 111                                 reg = <0x1012d000 0x20>;
 112                         };
 113
 114                         vpu {
 115                                 reg = <0x1012e000 0x20>;
 116                         };
 117
 118                         rga {
 119                                 reg = <0x1012f000 0x20>;
 120                         };
 121                         ebc {
 122                                 reg = <0x1012f080 0x20>;
 123                         };
 124
 125                         iep {
 126                                 reg = <0x1012f100 0x20>;
 127                         };
 128
 129                         lcdc {
 130                                 reg = <0x1012f180 0x20>;
 131                                 rockchip,priority = <3 3>;
 132                         };
 133
 134                         vip {
 135                                 reg = <0x1012f200 0x20>;
 136                                 rockchip,priority = <3 3>;
 137                         };
 138                 };
 139
 140                 msch {
 141                         #address-cells = <1>;
 142                         #size-cells = <1>;
 143                         ranges;
 144
 145                         msch@10128000 {
 146                                 reg = <0x10128000 0x20>;
 147                                 rockchip,read-latency = <0x3f>;
 148                         };
 149                 };
 150         };
 151
 152         psci {
 153                 compatible      = "arm,psci";
 154                 method          = "smc";
 155                 cpu_suspend     = <0x84000001>;
 156                 cpu_off         = <0x84000002>;
 157                 cpu_on          = <0x84000003>;
 158                 migrate         = <0x84000005>;
 159         };
 160
 161         amba {
 162                 compatible = "arm,amba-bus";
 163                 #address-cells = <1>;
 164                 #size-cells = <1>;
 165                 interrupt-parent = <&gic>;
 166                 ranges;
 167
 168                 pdma: pdma@20078000 {
 169                         compatible = "arm,pl330", "arm,primecell";
 170                         reg = <0x20078000 0x4000>;
 171                         arm,pl330-broken-no-flushp;//2
 172                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 173                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 174                         #dma-cells = <1>;
 175                         clocks = <&cru ACLK_DMAC>;
 176                         clock-names = "apb_pclk";
 177                 };
 178         };
 179
 180         xin24m: xin24m {
 181                 compatible = "fixed-clock";
 182                 clock-frequency = <24000000>;
 183                 clock-output-names = "xin24m";
 184                 #clock-cells = <0>;
 185         };
 186
 187         xin12m: xin12m {
 188                 compatible = "fixed-clock";
 189                 clocks = <&xin24m>;
 190                 clock-frequency = <12000000>;
 191                 clock-output-names = "xin12m";
 192                 #clock-cells = <0>;
 193         };
 194
 195         timer {
 196                 compatible = "arm,armv7-timer";
 197                 arm,cpu-registers-not-fw-configured;
 198                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 199                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 200                 clock-frequency = <24000000>;
 201         };
 202
 203         timer@20044000 {
 204                 compatible = "arm,armv7-timer";
 205                 reg = <0x20044000 0xb8>;
 206                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 207                 rockchip,broadcast = <1>;
 208         };
 209
 210         watchdog: wdt@2004c000 {
 211                 compatible = "rockchip,watch dog";
 212                 reg = <0x2004c000 0x100>;
 213                 clock-names = "pclk_wdt";
 214                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 215                 rockchip,irq = <1>;
 216                 rockchip,timeout = <60>;
 217                 rockchip,atboot = <1>;
 218                 rockchip,debug = <0>;
 219         };
 220
 221         reset: reset@20000110 {
 222                 compatible = "rockchip,reset";
 223                 reg = <0x20000110 0x24>;
 224                 #reset-cells = <1>;
 225         };
 226
 227         nandc: nandc@10500000 {
 228                 compatible = "rockchip,rk-nandc";
 229                 reg = <0x10500000 0x4000>;
 230                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 231                 pinctrl-names = "default";
 232                 pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
 233                 nandc_id = <0>;
 234                 clocks = <&cru SCLK_NANDC>,
 235                          <&cru HCLK_NANDC>,
 236                          <&cru SRST_NANDC>;
 237                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 238         };
 239
 240         cru: clock-controller@20000000 {
 241                 compatible = "rockchip,rk3128-cru";
 242                 reg = <0x20000000 0x1000>;
 243                 rockchip,grf = <&grf>;
 244                 #clock-cells = <1>;
 245                 #reset-cells = <1>;
 246                 assigned-clocks = <&cru PLL_GPLL>;
 247                 assigned-clock-rates = <594000000>;
 248         };
 249
 250         uart0: serial0@20060000 {
 251                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 252                 reg = <0x20060000 0x100>;
 253                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 254                 reg-shift = <2>;
 255                 reg-io-width = <4>;
 256                 clock-frequency = <24000000>;
 257                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 258                 clock-names = "baudclk", "apb_pclk";
 259                 pinctrl-names = "default";
 260                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 261                 dmas = <&pdma 2>, <&pdma 3>;
 262                 #dma-cells = <2>;
 263         };
 264
 265         uart1: serial1@20064000 {
 266                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 267                 reg = <0x20064000 0x100>;
 268                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 269                 reg-shift = <2>;
 270                 reg-io-width = <4>;
 271                 clock-frequency = <24000000>;
 272                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 273                 clock-names = "baudclk", "apb_pclk";
 274                 pinctrl-names = "default";
 275                 pinctrl-0 = <&uart1_xfer>;
 276                 dmas = <&pdma 4>, <&pdma 5>;
 277                 #dma-cells = <2>;
 278         };
 279
 280         uart2: serial2@20068000 {
 281                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 282                 reg = <0x20068000 0x100>;
 283                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 284                 reg-shift = <2>;
 285                 reg-io-width = <4>;
 286                 clock-frequency = <24000000>;
 287                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 288                 clock-names = "baudclk", "apb_pclk";
 289                 pinctrl-names = "default";
 290                 pinctrl-0 = <&uart2_xfer>;
 291                 dmas = <&pdma 6>, <&pdma 7>;
 292                 #dma-cells = <2>;
 293         };
 294
 295         saradc: saradc@2006c000 {
 296                 compatible = "rockchip,saradc";
 297                 reg = <0x2006c000 0x100>;
 298                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 299                 #io-channel-cells = <1>;
 300                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 301                 clock-names = "saradc", "apb_pclk";
 302                 resets = <&cru SRST_SARADC>;
 303                 reset-names = "saradc-apb";
 304                 status = "disabled";
 305         };
 306
 307         pwm0: pwm0@20050000 {
 308                 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
 309                 reg = <0x20050000 0x10>;
 310                 #pwm-cells = <3>;
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&pwm0_pin>;
 313                 clocks = <&cru PCLK_PWM>;
 314                 clock-names = "pwm";
 315         };
 316
 317         pwm1: pwm1@20050010 {
 318                 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
 319                 reg = <0x20050010 0x10>;
 320                 #pwm-cells = <3>;
 321                 pinctrl-names = "default";
 322                 pinctrl-0 = <&pwm1_pin>;
 323                 clocks = <&cru PCLK_PWM>;
 324                 clock-names = "pwm";
 325         };
 326
 327         pwm2: pwm2@20050020 {
 328                 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
 329                 reg = <0x20050020 0x10>;
 330                 #pwm-cells = <3>;
 331                 pinctrl-names = "default";
 332                 pinctrl-0 = <&pwm2_pin>;
 333                 clocks = <&cru PCLK_PWM>;
 334                 clock-names = "pwm";
 335         };
 336
 337         pwm3: pwm3@20050030 {
 338                 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
 339                 reg = <0x20050030 0x10>;
 340                 #pwm-cells = <3>;
 341                 pinctrl-names = "default";
 342                 pinctrl-0 = <&pwm3_pin>;
 343                 clocks = <&cru PCLK_PWM>;
 344                 clock-names = "pwm";
 345         };
 346
 347         sram: sram@10080400 {
 348                 compatible = "rockchip,rk3128-smp-sram", "mmio-sram";
 349                 reg = <0x10080400 0x1C00>;
 350                 map-exec;
 351                 map-cacheable;
 352         };
 353
 354         pmu: syscon@100a0000 {
 355                 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
 356                 reg = <0x100a0000 0x1000>;
 357                 #address-cells = <1>;
 358                 #size-cells = <1>;
 359         };
 360
 361         gic: interrupt-controller@10139000 {
 362                 compatible = "arm,gic-400";
 363                 interrupt-controller;
 364                 #interrupt-cells = <3>;
 365                 #address-cells = <0>;
 366                 reg = <0x10139000 0x1000>,
 367                       <0x1013a000 0x1000>,
 368                       <0x1013c000 0x2000>,
 369                       <0x1013e000 0x2000>;
 370                 interrupts = <GIC_PPI 9 0xf04>;
 371         };
 372
 373         u2phy: usb2-phy {
 374                 compatible = "rockchip,rk3128-usb2phy";
 375                 reg = <0x017c 0x0c>;
 376                 rockchip,grf = <&grf>;
 377                 clocks = <&cru SCLK_OTGPHY0>;
 378                 clock-names = "phyclk";
 379                 #clock-cells = <0>;
 380                 clock-output-names = "usb480m_phy";
 381                 #phy-cells = <1>;
 382                 status = "disabled";
 383
 384                 u2phy_otg: otg-port {
 385                         #phy-cells = <0>;
 386                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 387                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 388                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 389                         interrupt-names = "otg-bvalid", "otg-id",
 390                                           "linestate";
 391                         status = "disabled";
 392                 };
 393
 394                 u2phy_host: host-port {
 395                         #phy-cells = <0>;
 396                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 397                         interrupt-names = "linestate";
 398                         status = "disabled";
 399                 };
 400         };
 401
 402         usb_otg: usb@10180000 {
 403                 compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb",
 404                              "snps,dwc2";
 405                 reg = <0x10180000 0x40000>;
 406                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 407                 dr_mode = "otg";
 408                 g-use-dma;
 409                 hnp-srp-disable;
 410                 phys = <&u2phy 0>;
 411                 phy-names = "usb";
 412                 status = "disabled";
 413         };
 414
 415         usb_host_ehci: usb@101c0000 {
 416                 compatible = "generic-ehci";
 417                 reg = <0x101c0000 0x20000>;
 418                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 419                 phys = <&u2phy 1>;
 420                 phy-names = "usb";
 421                 status = "disabled";
 422         };
 423
 424         usb_host_ohci: usb@101e0000 {
 425                 compatible = "generic-ohci";
 426                 reg = <0x101e0000 0x20000>;
 427                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 428                 phys = <&u2phy 1>;
 429                 phy-names = "usb";
 430                 status = "disabled";
 431         };
 432
 433         sdmmc: dwmmc@10214000 {
 434                 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
 435                 reg = <0x10214000 0x4000>;
 436                 max-frequency = <150000000>;
 437                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 438                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 439                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 440                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 441                 fifo-depth = <0x100>;
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
 444                 bus-width = <4>;
 445                 status = "disabled";
 446         };
 447
 448         emmc: dwmmc@1021c000 {
 449                 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
 450                 reg = <0x1021c000 0x4000>;
 451                 max-frequency = <150000000>;
 452                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 453                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 454                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 455                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 456                 bus-width = <8>;
 457                 default-sample-phase = <158>;
 458                 num-slots = <1>;
 459                 fifo-depth = <0x100>;
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 462                 resets = <&cru SRST_EMMC>;
 463                 reset-names = "reset";
 464                 status = "disabled";
 465         };
 466
 467         i2c0: i2c0@20072000 {
 468                 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
 469                 reg = <20072000 0x1000>;
 470                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 471                 #address-cells = <1>;
 472                 #size-cells = <0>;
 473                 clock-names = "i2c";
 474                 clocks = <&cru PCLK_I2C0>;
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&i2c0_xfer>;
 477         };
 478
 479         i2c1: i2c1@20056000 {
 480                 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
 481                 reg = <0x20056000 0x1000>;
 482                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 483                 #address-cells = <1>;
 484                 #size-cells = <0>;
 485                 clock-names = "i2c";
 486                 clocks = <&cru PCLK_I2C1>;
 487                 pinctrl-names = "default";
 488                 pinctrl-0 = <&i2c1_xfer>;
 489         };
 490
 491         i2c2: i2c2@2005a000 {
 492                 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
 493                 reg = <0x2005a000 0x1000>;
 494                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 clock-names = "i2c";
 498                 clocks = <&cru PCLK_I2C2>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&i2c2_xfer>;
 501         };
 502
 503         i2c3: i2c3@2005e000 {
 504                 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
 505                 reg = <0x2005e000 0x1000>;
 506                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 507                 #address-cells = <1>;
 508                 #size-cells = <0>;
 509                 clock-names = "i2c";
 510                 clocks = <&cru PCLK_I2C3>;
 511                 pinctrl-names = "default";
 512                 pinctrl-0 = <&i2c3_xfer>;
 513         };
 514
 515         spi0: spi@20074000 {
 516                 compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi";
 517                 reg = <0x20074000 0x1000>;
 518                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 519                 #address-cells = <1>;
 520                 #size-cells = <0>;
 521                 pinctrl-names = "default";
 522                 pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
 523                 rockchip,spi-src-clk = <0>;
 524                 num-cs = <2>;
 525                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 526                 clock-names = "spiclk", "apb_pclk";
 527                 dmas = <&pdma 8>, <&pdma 9>;
 528                 #dma-cells = <2>;
 529                 dma-names = "tx", "rx";
 530         };
 531
 532         grf: syscon@20008000 {
 533                 compatible = "rockchip,rk3128-grf", "syscon";
 534                 reg = <0x20008000 0x1000>;
 535         };
 536
 537         pinctrl: pinctrl@20008000 {
 538                 compatible = "rockchip,rk3128-pinctrl";
 539                 reg = <0x20008000 0xA8>,
 540                       <0x200080A8 0x4C>,
 541                       <0x20008118 0x20>,
 542                       <0x20008100 0x04>;
 543                 reg-names = "base", "mux", "pull", "drv";
 544                 rockchip,grf = <&grf>;
 545                 #address-cells = <1>;
 546                 #size-cells = <1>;
 547                 ranges;
 548
 549                 gpio0: gpio0@2007c000 {
 550                         compatible = "rockchip,gpio-bank";
 551                         reg = <0x2007c000 0x100>;
 552                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 553                         clocks = <&cru PCLK_GPIO0>;
 554                         gpio-controller;
 555                         #gpio-cells = <2>;
 556                         interrupt-controller;
 557                         #interrupt-cells = <2>;
 558                 };
 559
 560                 gpio1: gpio1@20080000 {
 561                         compatible = "rockchip,gpio-bank";
 562                         reg = <0x20080000 0x100>;
 563                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&cru PCLK_GPIO1>;
 565                         gpio-controller;
 566                         #gpio-cells = <2>;
 567                         interrupt-controller;
 568                         #interrupt-cells = <2>;
 569                 };
 570
 571                 gpio2: gpio2@20084000 {
 572                         compatible = "rockchip,gpio-bank";
 573                         reg = <0x20084000 0x100>;
 574                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 575                         clocks = <&cru PCLK_GPIO2>;
 576                         gpio-controller;
 577                         #gpio-cells = <2>;
 578                         interrupt-controller;
 579                         #interrupt-cells = <2>;
 580                 };
 581
 582                 gpio3: gpio2@20088000 {
 583                         compatible = "rockchip,gpio-bank";
 584                         reg = <0x20088000 0x100>;
 585                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 586                         clocks = <&cru PCLK_GPIO3>;
 587                         gpio-controller;
 588                         #gpio-cells = <2>;
 589                         interrupt-controller;
 590                         #interrupt-cells = <2>;
 591                 };
 592
 593                 pcfg_pull_up: pcfg-pull-up {
 594                         bias-pull-up;
 595                 };
 596
 597                 pcfg_pull_down: pcfg-pull-down {
 598                         bias-pull-down;
 599                 };
 600
 601                 pcfg_pull_none: pcfg-pull-none {
 602                         bias-disable;
 603                 };
 604
 605                 emmc {
 606                         /*
 607                          * We run eMMC at max speed; bump up drive strength.
 608                          * We also have external pulls, so disable the internal ones.
 609                          */
 610
 611                         emmc_clk: emmc-clk {
 612                                 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
 613                         };
 614
 615                         emmc_cmd: emmc-cmd {
 616                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
 617                         };
 618
 619                         emmc_pwren: emmc-pwren {
 620                                 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>;
 621                         };
 622
 623                         emmc_bus8: emmc-bus8 {
 624                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
 625                                                 <1 RK_PD1 2 &pcfg_pull_none>,
 626                                                 <1 RK_PD2 2 &pcfg_pull_none>,
 627                                                 <1 RK_PD3 2 &pcfg_pull_none>,
 628                                                 <1 RK_PD4 2 &pcfg_pull_none>,
 629                                                 <1 RK_PD5 2 &pcfg_pull_none>,
 630                                                 <1 RK_PD6 2 &pcfg_pull_none>,
 631                                                 <1 RK_PD7 2 &pcfg_pull_none>;
 632                         };
 633                 };
 634
 635                 nandc{
 636                         nandc_ale:nandc-ale {
 637                                 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
 638                         };
 639
 640                         nandc_cle:nandc-cle {
 641                                 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
 642                         };
 643
 644                         nandc_wrn:nandc-wrn {
 645                                 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
 646                         };
 647
 648                         nandc_rdn:nandc-rdn {
 649                                 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
 650                         };
 651
 652                         nandc_rdy:nandc-rdy {
 653                                 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
 654                         };
 655
 656                         nandc_cs0:nandc-cs0 {
 657                                 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
 658                         };
 659
 660                         nandc_data: nandc-data {
 661                                 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
 662                         };
 663                 };
 664
 665                 uart0 {
 666                         uart0_xfer: uart0-xfer {
 667                                 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>,
 668                                                 <0 RK_PC1 1 &pcfg_pull_none>;
 669                         };
 670
 671                         uart0_cts: uart0-cts {
 672                                 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
 673                         };
 674
 675                         uart0_rts: uart0-rts {
 676                                 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
 677                         };
 678                 };
 679
 680                 uart1 {
 681                         uart1_xfer: uart1-xfer {
 682                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>,
 683                                                 <2 RK_PC7 1 &pcfg_pull_none>;
 684                         };
 685                 };
 686
 687                 uart2 {
 688                         uart2_xfer: uart2-xfer {
 689                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>,
 690                                                 <1 RK_PC3 2 &pcfg_pull_none>;
 691                         };
 692                 };
 693
 694                 sdmmc {
 695                         sdmmc_clk: sdmmc-clk {
 696                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
 697                         };
 698
 699                         sdmmc_cmd: sdmmc-cmd {
 700                                 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>;
 701                         };
 702
 703                         sdmmc_wp: sdmmc-wp {
 704                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>;
 705                         };
 706
 707                         sdmmc_pwren: sdmmc-pwren {
 708                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>;
 709                         };
 710
 711                         sdmmc_bus4: sdmmc-bus4 {
 712                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>,
 713                                                 <1 RK_PC3 1 &pcfg_pull_up>,
 714                                                 <1 RK_PC4 1 &pcfg_pull_up>,
 715                                                 <1 RK_PC5 1 &pcfg_pull_up>;
 716                         };
 717                 };
 718
 719                 pwm0 {
 720                         pwm0_pin: pwm0-pin {
 721                                 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
 722                         };
 723                 };
 724
 725                 pwm1 {
 726                         pwm1_pin: pwm1-pin {
 727                                 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
 728                         };
 729                 };
 730
 731                 pwm2 {
 732                         pwm2_pin: pwm2-pin {
 733                                 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
 734                         };
 735                 };
 736
 737                 pwm3 {
 738                         pwm3_pin: pwm3-pin {
 739                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
 740                         };
 741                 };
 742
 743                 i2c0 {
 744                         i2c0_xfer: i2c0-xfer {
 745                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
 746                                                 <0 RK_PA1 1 &pcfg_pull_none>;
 747                         };
 748                 };
 749
 750                 i2c1 {
 751                         i2c1_xfer: i2c1-xfer {
 752                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
 753                                                 <0 RK_PA3 1 &pcfg_pull_none>;
 754                         };
 755                 };
 756
 757                 i2c2 {
 758                         i2c2_xfer: i2c2-xfer {
 759                                 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
 760                                                 <2 RK_PC5 3 &pcfg_pull_none>;
 761                         };
 762                 };
 763
 764                 i2c3 {
 765                         i2c3_xfer: i2c3-xfer {
 766                                 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
 767                                                 <0 RK_PA7 1 &pcfg_pull_none>;
 768                         };
 769                 };
 770
 771                 spi0 {
 772                         spi0_txd_mux0:spi0-txd-mux0 {
 773                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
 774                         };
 775
 776                         spi0_rxd_mux0:spi0-rxd-mux0 {
 777                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
 778                         };
 779
 780                         spi0_clk_mux0:spi0-clk-mux0 {
 781                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
 782                         };
 783
 784                         spi0_cs0_mux0:spi0-cs0-mux0 {
 785                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
 786                         };
 787
 788                         spi0_cs1_mux0:spi0-cs1-mux0 {
 789                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
 790                         };
 791                 };
 792
 793         };
 794 };