arch/arm/dts/r8a77990-ebisu.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the ebisu board
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  */
   7
   8 /dts-v1/;
   9 #include "r8a77990.dtsi"
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 / {
  13         model = "Renesas Ebisu board based on r8a77990";
  14         compatible = "renesas,ebisu", "renesas,r8a77990";
  15
  16         aliases {
  17                 serial0 = &scif2;
  18                 ethernet0 = &avb;
  19         };
  20
  21         chosen {
  22                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  23                 stdout-path = "serial0:115200n8";
  24         };
  25
  26         audio_clkout: audio-clkout {
  27                 /*
  28                  * This is same as <&rcar_sound 0>
  29                  * but needed to avoid cs2000/rcar_sound probe dead-lock
  30                  */
  31                 compatible = "fixed-clock";
  32                 #clock-cells = <0>;
  33                 clock-frequency = <11289600>;
  34         };
  35
  36         backlight: backlight {
  37                 compatible = "pwm-backlight";
  38                 pwms = <&pwm3 0 50000>;
  39
  40                 brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
  41                 default-brightness-level = <10>;
  42
  43                 power-supply = <&reg_12p0v>;
  44         };
  45
  46         cvbs-in {
  47                 compatible = "composite-video-connector";
  48                 label = "CVBS IN";
  49
  50                 port {
  51                         cvbs_con: endpoint {
  52                                 remote-endpoint = <&adv7482_ain7>;
  53                         };
  54                 };
  55         };
  56
  57         hdmi-in {
  58                 compatible = "hdmi-connector";
  59                 label = "HDMI IN";
  60                 type = "a";
  61
  62                 port {
  63                         hdmi_in_con: endpoint {
  64                                 remote-endpoint = <&adv7482_hdmi>;
  65                         };
  66                 };
  67         };
  68
  69         hdmi-out {
  70                 compatible = "hdmi-connector";
  71                 type = "a";
  72
  73                 port {
  74                         hdmi_con_out: endpoint {
  75                                 remote-endpoint = <&adv7511_out>;
  76                         };
  77                 };
  78         };
  79
  80         lvds-decoder {
  81                 compatible = "thine,thc63lvd1024";
  82                 vcc-supply = <&reg_3p3v>;
  83
  84                 ports {
  85                         #address-cells = <1>;
  86                         #size-cells = <0>;
  87
  88                         port@0 {
  89                                 reg = <0>;
  90                                 thc63lvd1024_in: endpoint {
  91                                         remote-endpoint = <&lvds0_out>;
  92                                 };
  93                         };
  94
  95                         port@2 {
  96                                 reg = <2>;
  97                                 thc63lvd1024_out: endpoint {
  98                                         remote-endpoint = <&adv7511_in>;
  99                                 };
 100                         };
 101                 };
 102         };
 103
 104         memory@48000000 {
 105                 device_type = "memory";
 106                 /* first 128MB is reserved for secure area. */
 107                 reg = <0x0 0x48000000 0x0 0x38000000>;
 108         };
 109
 110         reg_1p8v: regulator0 {
 111                 compatible = "regulator-fixed";
 112                 regulator-name = "fixed-1.8V";
 113                 regulator-min-microvolt = <1800000>;
 114                 regulator-max-microvolt = <1800000>;
 115                 regulator-boot-on;
 116                 regulator-always-on;
 117         };
 118
 119         reg_3p3v: regulator1 {
 120                 compatible = "regulator-fixed";
 121                 regulator-name = "fixed-3.3V";
 122                 regulator-min-microvolt = <3300000>;
 123                 regulator-max-microvolt = <3300000>;
 124                 regulator-boot-on;
 125                 regulator-always-on;
 126         };
 127
 128         reg_12p0v: regulator2 {
 129                 compatible = "regulator-fixed";
 130                 regulator-name = "D12.0V";
 131                 regulator-min-microvolt = <12000000>;
 132                 regulator-max-microvolt = <12000000>;
 133                 regulator-boot-on;
 134                 regulator-always-on;
 135         };
 136
 137         rsnd_ak4613: sound {
 138                 compatible = "simple-audio-card";
 139
 140                 simple-audio-card,name = "rsnd-ak4613";
 141                 simple-audio-card,format = "left_j";
 142                 simple-audio-card,bitclock-master = <&sndcpu>;
 143                 simple-audio-card,frame-master = <&sndcpu>;
 144
 145                 sndcodec: simple-audio-card,codec {
 146                         sound-dai = <&ak4613>;
 147                 };
 148
 149                 sndcpu: simple-audio-card,cpu {
 150                         sound-dai = <&rcar_sound>;
 151                 };
 152         };
 153
 154         vbus0_usb2: regulator-vbus0-usb2 {
 155                 compatible = "regulator-fixed";
 156
 157                 regulator-name = "USB20_VBUS_CN";
 158                 regulator-min-microvolt = <5000000>;
 159                 regulator-max-microvolt = <5000000>;
 160
 161                 gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
 162                 enable-active-high;
 163         };
 164
 165         vcc_sdhi0: regulator-vcc-sdhi0 {
 166                 compatible = "regulator-fixed";
 167
 168                 regulator-name = "SDHI0 Vcc";
 169                 regulator-min-microvolt = <3300000>;
 170                 regulator-max-microvolt = <3300000>;
 171
 172                 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
 173                 enable-active-high;
 174         };
 175
 176         vccq_sdhi0: regulator-vccq-sdhi0 {
 177                 compatible = "regulator-gpio";
 178
 179                 regulator-name = "SDHI0 VccQ";
 180                 regulator-min-microvolt = <1800000>;
 181                 regulator-max-microvolt = <3300000>;
 182
 183                 gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
 184                 gpios-states = <1>;
 185                 states = <3300000 1>, <1800000 0>;
 186         };
 187
 188         vcc_sdhi1: regulator-vcc-sdhi1 {
 189                 compatible = "regulator-fixed";
 190
 191                 regulator-name = "SDHI1 Vcc";
 192                 regulator-min-microvolt = <3300000>;
 193                 regulator-max-microvolt = <3300000>;
 194
 195                 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
 196                 enable-active-high;
 197         };
 198
 199         vccq_sdhi1: regulator-vccq-sdhi1 {
 200                 compatible = "regulator-gpio";
 201
 202                 regulator-name = "SDHI1 VccQ";
 203                 regulator-min-microvolt = <1800000>;
 204                 regulator-max-microvolt = <3300000>;
 205
 206                 gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
 207                 gpios-states = <1>;
 208                 states = <3300000 1>, <1800000 0>;
 209         };
 210
 211         vga {
 212                 compatible = "vga-connector";
 213
 214                 port {
 215                         vga_in: endpoint {
 216                                 remote-endpoint = <&adv7123_out>;
 217                         };
 218                 };
 219         };
 220
 221         vga-encoder {
 222                 compatible = "adi,adv7123";
 223
 224                 ports {
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227
 228                         port@0 {
 229                                 reg = <0>;
 230                                 adv7123_in: endpoint {
 231                                         remote-endpoint = <&du_out_rgb>;
 232                                 };
 233                         };
 234                         port@1 {
 235                                 reg = <1>;
 236                                 adv7123_out: endpoint {
 237                                         remote-endpoint = <&vga_in>;
 238                                 };
 239                         };
 240                 };
 241         };
 242
 243         x12_clk: x12 {
 244                 compatible = "fixed-clock";
 245                 #clock-cells = <0>;
 246                 clock-frequency = <24576000>;
 247         };
 248
 249         x13_clk: x13 {
 250                 compatible = "fixed-clock";
 251                 #clock-cells = <0>;
 252                 clock-frequency = <74250000>;
 253         };
 254 };
 255
 256 &audio_clk_a {
 257         clock-frequency = <22579200>;
 258 };
 259
 260 &avb {
 261         pinctrl-0 = <&avb_pins>;
 262         pinctrl-names = "default";
 263         phy-handle = <&phy0>;
 264         status = "okay";
 265
 266         phy0: ethernet-phy@0 {
 267                 rxc-skew-ps = <1500>;
 268                 reg = <0>;
 269                 interrupt-parent = <&gpio2>;
 270                 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
 271                 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
 272                 /*
 273                  * TX clock internal delay mode is required for reliable
 274                  * 1Gbps communication using the KSZ9031RNX phy present on
 275                  * the Ebisu board, however, TX clock internal delay mode
 276                  * isn't supported on r8a77990.  Thus, limit speed to
 277                  * 100Mbps for reliable communication.
 278                  */
 279                 max-speed = <100>;
 280         };
 281 };
 282
 283 &canfd {
 284         pinctrl-0 = <&canfd0_pins>;
 285         pinctrl-names = "default";
 286         status = "okay";
 287
 288         channel0 {
 289                 status = "okay";
 290         };
 291 };
 292
 293 &csi40 {
 294         status = "okay";
 295
 296         ports {
 297                 port@0 {
 298                         reg = <0>;
 299
 300                         csi40_in: endpoint {
 301                                 clock-lanes = <0>;
 302                                 data-lanes = <1 2>;
 303                                 remote-endpoint = <&adv7482_txa>;
 304                         };
 305                 };
 306         };
 307 };
 308
 309 &du {
 310         pinctrl-0 = <&du_pins>;
 311         pinctrl-names = "default";
 312         status = "okay";
 313
 314         clocks = <&cpg CPG_MOD 724>,
 315                  <&cpg CPG_MOD 723>,
 316                  <&x13_clk>;
 317         clock-names = "du.0", "du.1", "dclkin.0";
 318
 319         ports {
 320                 port@0 {
 321                         endpoint {
 322                                 remote-endpoint = <&adv7123_in>;
 323                         };
 324                 };
 325         };
 326 };
 327
 328 &ehci0 {
 329         dr_mode = "otg";
 330         status = "okay";
 331 };
 332
 333 &extal_clk {
 334         clock-frequency = <48000000>;
 335 };
 336
 337 &hsusb {
 338         dr_mode = "otg";
 339         status = "okay";
 340 };
 341
 342 &i2c0 {
 343         status = "okay";
 344
 345         io_expander: gpio@20 {
 346                 compatible = "onnn,pca9654";
 347                 reg = <0x20>;
 348                 gpio-controller;
 349                 #gpio-cells = <2>;
 350                 interrupt-parent = <&gpio2>;
 351                 interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
 352         };
 353
 354         hdmi-encoder@39 {
 355                 compatible = "adi,adv7511w";
 356                 reg = <0x39>;
 357                 interrupt-parent = <&gpio1>;
 358                 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
 359
 360                 adi,input-depth = <8>;
 361                 adi,input-colorspace = "rgb";
 362                 adi,input-clock = "1x";
 363                 adi,input-style = <1>;
 364                 adi,input-justification = "evenly";
 365
 366                 ports {
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369
 370                         port@0 {
 371                                 reg = <0>;
 372                                 adv7511_in: endpoint {
 373                                         remote-endpoint = <&thc63lvd1024_out>;
 374                                 };
 375                         };
 376
 377                         port@1 {
 378                                 reg = <1>;
 379                                 adv7511_out: endpoint {
 380                                         remote-endpoint = <&hdmi_con_out>;
 381                                 };
 382                         };
 383                 };
 384         };
 385
 386         video-receiver@70 {
 387                 compatible = "adi,adv7482";
 388                 reg = <0x70>;
 389
 390                 #address-cells = <1>;
 391                 #size-cells = <0>;
 392
 393                 interrupt-parent = <&gpio0>;
 394                 interrupt-names = "intrq1", "intrq2";
 395                 interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
 396                              <17 IRQ_TYPE_LEVEL_LOW>;
 397
 398                 port@7 {
 399                         reg = <7>;
 400
 401                         adv7482_ain7: endpoint {
 402                                 remote-endpoint = <&cvbs_con>;
 403                         };
 404                 };
 405
 406                 port@8 {
 407                         reg = <8>;
 408
 409                         adv7482_hdmi: endpoint {
 410                                 remote-endpoint = <&hdmi_in_con>;
 411                         };
 412                 };
 413
 414                 port@a {
 415                         reg = <10>;
 416
 417                         adv7482_txa: endpoint {
 418                                 clock-lanes = <0>;
 419                                 data-lanes = <1 2>;
 420                                 remote-endpoint = <&csi40_in>;
 421                         };
 422                 };
 423         };
 424 };
 425
 426 &i2c3 {
 427         status = "okay";
 428
 429         ak4613: codec@10 {
 430                 compatible = "asahi-kasei,ak4613";
 431                 #sound-dai-cells = <0>;
 432                 reg = <0x10>;
 433                 clocks = <&rcar_sound 3>;
 434
 435                 asahi-kasei,in1-single-end;
 436                 asahi-kasei,in2-single-end;
 437                 asahi-kasei,out1-single-end;
 438                 asahi-kasei,out2-single-end;
 439                 asahi-kasei,out3-single-end;
 440                 asahi-kasei,out4-single-end;
 441                 asahi-kasei,out5-single-end;
 442                 asahi-kasei,out6-single-end;
 443         };
 444
 445         cs2000: clk-multiplier@4f {
 446                 #clock-cells = <0>;
 447                 compatible = "cirrus,cs2000-cp";
 448                 reg = <0x4f>;
 449                 clocks = <&audio_clkout>, <&x12_clk>;
 450                 clock-names = "clk_in", "ref_clk";
 451
 452                 assigned-clocks = <&cs2000>;
 453                 assigned-clock-rates = <24576000>; /* 1/1 divide */
 454         };
 455 };
 456
 457 &i2c_dvfs {
 458         status = "okay";
 459
 460         clock-frequency = <400000>;
 461
 462         pmic: pmic@30 {
 463                 pinctrl-0 = <&irq0_pins>;
 464                 pinctrl-names = "default";
 465
 466                 compatible = "rohm,bd9571mwv";
 467                 reg = <0x30>;
 468                 interrupt-parent = <&intc_ex>;
 469                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 470                 interrupt-controller;
 471                 #interrupt-cells = <2>;
 472                 gpio-controller;
 473                 #gpio-cells = <2>;
 474                 rohm,ddr-backup-power = <0x1>;
 475                 rohm,rstbmode-level;
 476         };
 477 };
 478
 479 &lvds0 {
 480         status = "okay";
 481
 482         clocks = <&cpg CPG_MOD 727>,
 483                  <&x13_clk>,
 484                  <&extal_clk>;
 485         clock-names = "fck", "dclkin.0", "extal";
 486
 487         ports {
 488                 port@1 {
 489                         lvds0_out: endpoint {
 490                                 remote-endpoint = <&thc63lvd1024_in>;
 491                         };
 492                 };
 493         };
 494 };
 495
 496 &lvds1 {
 497         /*
 498          * Even though the LVDS1 output is not connected, the encoder must be
 499          * enabled to supply a pixel clock to the DU for the DPAD output when
 500          * LVDS0 is in use.
 501          */
 502         status = "okay";
 503
 504         clocks = <&cpg CPG_MOD 727>,
 505                  <&x13_clk>,
 506                  <&extal_clk>;
 507         clock-names = "fck", "dclkin.0", "extal";
 508 };
 509
 510 &ohci0 {
 511         dr_mode = "otg";
 512         status = "okay";
 513 };
 514
 515 &pcie_bus_clk {
 516         clock-frequency = <100000000>;
 517 };
 518
 519 &pciec0 {
 520         status = "okay";
 521 };
 522
 523 &pfc {
 524         avb_pins: avb {
 525                 mux {
 526                         groups = "avb_link", "avb_mii";
 527                         function = "avb";
 528                 };
 529         };
 530
 531         canfd0_pins: canfd0 {
 532                 groups = "canfd0_data";
 533                 function = "canfd0";
 534         };
 535
 536         du_pins: du {
 537                 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
 538                 function = "du";
 539         };
 540
 541         irq0_pins: irq0 {
 542                 groups = "intc_ex_irq0";
 543                 function = "intc_ex";
 544         };
 545
 546         pwm3_pins: pwm3 {
 547                 groups = "pwm3_b";
 548                 function = "pwm3";
 549         };
 550
 551         pwm5_pins: pwm5 {
 552                 groups = "pwm5_a";
 553                 function = "pwm5";
 554         };
 555
 556         scif2_pins: scif2 {
 557                 groups = "scif2_data_a";
 558                 function = "scif2";
 559         };
 560
 561         sdhi0_pins: sd0 {
 562                 groups = "sdhi0_data4", "sdhi0_ctrl";
 563                 function = "sdhi0";
 564                 power-source = <3300>;
 565         };
 566
 567         sdhi0_pins_uhs: sd0_uhs {
 568                 groups = "sdhi0_data4", "sdhi0_ctrl";
 569                 function = "sdhi0";
 570                 power-source = <1800>;
 571         };
 572
 573         sdhi1_pins: sd1 {
 574                 groups = "sdhi1_data4", "sdhi1_ctrl";
 575                 function = "sdhi1";
 576                 power-source = <3300>;
 577         };
 578
 579         sdhi1_pins_uhs: sd1_uhs {
 580                 groups = "sdhi1_data4", "sdhi1_ctrl";
 581                 function = "sdhi1";
 582                 power-source = <1800>;
 583         };
 584
 585         sdhi3_pins: sd3 {
 586                 groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
 587                 function = "sdhi3";
 588                 power-source = <1800>;
 589         };
 590
 591         sound_clk_pins: sound_clk {
 592                 groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
 593                          "audio_clkout_a", "audio_clkout1_a";
 594                 function = "audio_clk";
 595         };
 596
 597         sound_pins: sound {
 598                 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
 599                 function = "ssi";
 600         };
 601
 602         usb0_pins: usb {
 603                 groups = "usb0_b", "usb0_id";
 604                 function = "usb0";
 605         };
 606
 607         usb30_pins: usb30 {
 608                 groups = "usb30";
 609                 function = "usb30";
 610         };
 611 };
 612
 613 &pwm3 {
 614         pinctrl-0 = <&pwm3_pins>;
 615         pinctrl-names = "default";
 616
 617         status = "okay";
 618 };
 619
 620 &pwm5 {
 621         pinctrl-0 = <&pwm5_pins>;
 622         pinctrl-names = "default";
 623
 624         status = "okay";
 625 };
 626
 627 &rcar_sound {
 628         pinctrl-0 = <&sound_pins &sound_clk_pins>;
 629         pinctrl-names = "default";
 630
 631         /* Single DAI */
 632         #sound-dai-cells = <0>;
 633
 634         /* audio_clkout0/1/2/3 */
 635         #clock-cells = <1>;
 636         clock-frequency = <12288000 11289600>;
 637
 638         status = "okay";
 639
 640         /* update <audio_clk_b> to <cs2000> */
 641         clocks = <&cpg CPG_MOD 1005>,
 642                  <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
 643                  <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
 644                  <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
 645                  <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
 646                  <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
 647                  <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
 648                  <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
 649                  <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
 650                  <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
 651                  <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
 652                  <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
 653                  <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
 654                  <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
 655                  <&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
 656                  <&cpg CPG_CORE R8A77990_CLK_ZA2>;
 657
 658         rcar_sound,dai {
 659                 dai0 {
 660                         playback = <&ssi0 &src0 &dvc0>;
 661                         capture  = <&ssi1 &src1 &dvc1>;
 662                 };
 663         };
 664
 665 };
 666
 667 &rwdt {
 668         timeout-sec = <60>;
 669         status = "okay";
 670 };
 671
 672 &scif2 {
 673         pinctrl-0 = <&scif2_pins>;
 674         pinctrl-names = "default";
 675
 676         status = "okay";
 677 };
 678
 679 &sdhi0 {
 680         pinctrl-0 = <&sdhi0_pins>;
 681         pinctrl-1 = <&sdhi0_pins_uhs>;
 682         pinctrl-names = "default", "state_uhs";
 683
 684         vmmc-supply = <&vcc_sdhi0>;
 685         vqmmc-supply = <&vccq_sdhi0>;
 686         cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
 687         wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 688         bus-width = <4>;
 689         sd-uhs-sdr50;
 690         sd-uhs-sdr104;
 691         status = "okay";
 692 };
 693
 694 &sdhi1 {
 695         pinctrl-0 = <&sdhi1_pins>;
 696         pinctrl-1 = <&sdhi1_pins_uhs>;
 697         pinctrl-names = "default", "state_uhs";
 698
 699         vmmc-supply = <&vcc_sdhi1>;
 700         vqmmc-supply = <&vccq_sdhi1>;
 701         cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
 702         bus-width = <4>;
 703         sd-uhs-sdr50;
 704         sd-uhs-sdr104;
 705         status = "okay";
 706 };
 707
 708 &sdhi3 {
 709         /* used for on-board 8bit eMMC */
 710         pinctrl-0 = <&sdhi3_pins>;
 711         pinctrl-1 = <&sdhi3_pins>;
 712         pinctrl-names = "default", "state_uhs";
 713
 714         vmmc-supply = <&reg_3p3v>;
 715         vqmmc-supply = <&reg_1p8v>;
 716         mmc-ddr-1_8v;
 717         mmc-hs200-1_8v;
 718         mmc-hs400-1_8v;
 719         bus-width = <8>;
 720         non-removable;
 721         status = "okay";
 722 };
 723
 724 &ssi1 {
 725         shared-pin;
 726 };
 727
 728 &usb2_phy0 {
 729         pinctrl-0 = <&usb0_pins>;
 730         pinctrl-names = "default";
 731
 732         vbus-supply = <&vbus0_usb2>;
 733         status = "okay";
 734 };
 735
 736 &usb3_peri0 {
 737         companion = <&xhci0>;
 738         status = "okay";
 739 };
 740
 741 &vin4 {
 742         status = "okay";
 743 };
 744
 745 &vin5 {
 746         status = "okay";
 747 };
 748
 749 &xhci0 {
 750         pinctrl-0 = <&usb30_pins>;
 751         pinctrl-names = "default";
 752
 753         status = "okay";
 754 };