arch/arm/dts/r8a774e1.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the r8a774e1 SoC
   4  *
   5  * Copyright (C) 2020 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
  11 #include <dt-bindings/power/r8a774e1-sysc.h>
  12
  13 #define CPG_AUDIO_CLK_I         R8A774E1_CLK_S0D4
  14
  15 / {
  16         compatible = "renesas,r8a774e1";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         /*
  21          * The external audio clocks are configured as 0 Hz fixed frequency
  22          * clocks by default.
  23          * Boards that provide audio clocks should override them.
  24          */
  25         audio_clk_a: audio_clk_a {
  26                 compatible = "fixed-clock";
  27                 #clock-cells = <0>;
  28                 clock-frequency = <0>;
  29         };
  30
  31         audio_clk_c: audio_clk_c {
  32                 compatible = "fixed-clock";
  33                 #clock-cells = <0>;
  34                 clock-frequency = <0>;
  35         };
  36
  37         /* External CAN clock - to be overridden by boards that provide it */
  38         can_clk: can {
  39                 compatible = "fixed-clock";
  40                 #clock-cells = <0>;
  41                 clock-frequency = <0>;
  42         };
  43
  44         cluster0_opp: opp_table0 {
  45                 compatible = "operating-points-v2";
  46                 opp-shared;
  47
  48                 opp-500000000 {
  49                         opp-hz = /bits/ 64 <500000000>;
  50                         opp-microvolt = <820000>;
  51                         clock-latency-ns = <300000>;
  52                 };
  53                 opp-1000000000 {
  54                         opp-hz = /bits/ 64 <1000000000>;
  55                         opp-microvolt = <820000>;
  56                         clock-latency-ns = <300000>;
  57                 };
  58                 opp-1500000000 {
  59                         opp-hz = /bits/ 64 <1500000000>;
  60                         opp-microvolt = <820000>;
  61                         clock-latency-ns = <300000>;
  62                         opp-suspend;
  63                 };
  64         };
  65
  66         cluster1_opp: opp_table1 {
  67                 compatible = "operating-points-v2";
  68                 opp-shared;
  69
  70                 opp-800000000 {
  71                         opp-hz = /bits/ 64 <800000000>;
  72                         opp-microvolt = <820000>;
  73                         clock-latency-ns = <300000>;
  74                 };
  75                 opp-1000000000 {
  76                         opp-hz = /bits/ 64 <1000000000>;
  77                         opp-microvolt = <820000>;
  78                         clock-latency-ns = <300000>;
  79                 };
  80                 opp-1200000000 {
  81                         opp-hz = /bits/ 64 <1200000000>;
  82                         opp-microvolt = <820000>;
  83                         clock-latency-ns = <300000>;
  84                 };
  85         };
  86
  87         cpus {
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90
  91                 cpu-map {
  92                         cluster0 {
  93                                 core0 {
  94                                         cpu = <&a57_0>;
  95                                 };
  96                                 core1 {
  97                                         cpu = <&a57_1>;
  98                                 };
  99                                 core2 {
 100                                         cpu = <&a57_2>;
 101                                 };
 102                                 core3 {
 103                                         cpu = <&a57_3>;
 104                                 };
 105                         };
 106
 107                         cluster1 {
 108                                 core0 {
 109                                         cpu = <&a53_0>;
 110                                 };
 111                                 core1 {
 112                                         cpu = <&a53_1>;
 113                                 };
 114                                 core2 {
 115                                         cpu = <&a53_2>;
 116                                 };
 117                                 core3 {
 118                                         cpu = <&a53_3>;
 119                                 };
 120                         };
 121                 };
 122
 123                 a57_0: cpu@0 {
 124                         compatible = "arm,cortex-a57";
 125                         reg = <0x0>;
 126                         device_type = "cpu";
 127                         power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
 128                         next-level-cache = <&L2_CA57>;
 129                         enable-method = "psci";
 130                         dynamic-power-coefficient = <854>;
 131                         clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
 132                         operating-points-v2 = <&cluster0_opp>;
 133                         capacity-dmips-mhz = <1024>;
 134                         #cooling-cells = <2>;
 135                 };
 136
 137                 a57_1: cpu@1 {
 138                         compatible = "arm,cortex-a57";
 139                         reg = <0x1>;
 140                         device_type = "cpu";
 141                         power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
 142                         next-level-cache = <&L2_CA57>;
 143                         enable-method = "psci";
 144                         clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
 145                         operating-points-v2 = <&cluster0_opp>;
 146                         capacity-dmips-mhz = <1024>;
 147                         #cooling-cells = <2>;
 148                 };
 149
 150                 a57_2: cpu@2 {
 151                         compatible = "arm,cortex-a57";
 152                         reg = <0x2>;
 153                         device_type = "cpu";
 154                         power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
 155                         next-level-cache = <&L2_CA57>;
 156                         enable-method = "psci";
 157                         clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
 158                         operating-points-v2 = <&cluster0_opp>;
 159                         capacity-dmips-mhz = <1024>;
 160                         #cooling-cells = <2>;
 161                 };
 162
 163                 a57_3: cpu@3 {
 164                         compatible = "arm,cortex-a57";
 165                         reg = <0x3>;
 166                         device_type = "cpu";
 167                         power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
 168                         next-level-cache = <&L2_CA57>;
 169                         enable-method = "psci";
 170                         clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
 171                         operating-points-v2 = <&cluster0_opp>;
 172                         capacity-dmips-mhz = <1024>;
 173                         #cooling-cells = <2>;
 174                 };
 175
 176                 a53_0: cpu@100 {
 177                         compatible = "arm,cortex-a53";
 178                         reg = <0x100>;
 179                         device_type = "cpu";
 180                         power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
 181                         next-level-cache = <&L2_CA53>;
 182                         enable-method = "psci";
 183                         #cooling-cells = <2>;
 184                         dynamic-power-coefficient = <277>;
 185                         clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
 186                         operating-points-v2 = <&cluster1_opp>;
 187                         capacity-dmips-mhz = <535>;
 188                 };
 189
 190                 a53_1: cpu@101 {
 191                         compatible = "arm,cortex-a53";
 192                         reg = <0x101>;
 193                         device_type = "cpu";
 194                         power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
 195                         next-level-cache = <&L2_CA53>;
 196                         enable-method = "psci";
 197                         clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
 198                         operating-points-v2 = <&cluster1_opp>;
 199                         capacity-dmips-mhz = <535>;
 200                 };
 201
 202                 a53_2: cpu@102 {
 203                         compatible = "arm,cortex-a53";
 204                         reg = <0x102>;
 205                         device_type = "cpu";
 206                         power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
 207                         next-level-cache = <&L2_CA53>;
 208                         enable-method = "psci";
 209                         clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
 210                         operating-points-v2 = <&cluster1_opp>;
 211                         capacity-dmips-mhz = <535>;
 212                 };
 213
 214                 a53_3: cpu@103 {
 215                         compatible = "arm,cortex-a53";
 216                         reg = <0x103>;
 217                         device_type = "cpu";
 218                         power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
 219                         next-level-cache = <&L2_CA53>;
 220                         enable-method = "psci";
 221                         clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
 222                         operating-points-v2 = <&cluster1_opp>;
 223                         capacity-dmips-mhz = <535>;
 224                 };
 225
 226                 L2_CA57: cache-controller-0 {
 227                         compatible = "cache";
 228                         power-domains = <&sysc R8A774E1_PD_CA57_SCU>;
 229                         cache-unified;
 230                         cache-level = <2>;
 231                 };
 232
 233                 L2_CA53: cache-controller-1 {
 234                         compatible = "cache";
 235                         power-domains = <&sysc R8A774E1_PD_CA53_SCU>;
 236                         cache-unified;
 237                         cache-level = <2>;
 238                 };
 239         };
 240
 241         extal_clk: extal {
 242                 compatible = "fixed-clock";
 243                 #clock-cells = <0>;
 244                 /* This value must be overridden by the board */
 245                 clock-frequency = <0>;
 246         };
 247
 248         extalr_clk: extalr {
 249                 compatible = "fixed-clock";
 250                 #clock-cells = <0>;
 251                 /* This value must be overridden by the board */
 252                 clock-frequency = <0>;
 253         };
 254
 255         /* External PCIe clock - can be overridden by the board */
 256         pcie_bus_clk: pcie_bus {
 257                 compatible = "fixed-clock";
 258                 #clock-cells = <0>;
 259                 clock-frequency = <0>;
 260         };
 261
 262         pmu_a53 {
 263                 compatible = "arm,cortex-a53-pmu";
 264                 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 265                                       <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 266                                       <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 267                                       <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 268                 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
 269         };
 270
 271         pmu_a57 {
 272                 compatible = "arm,cortex-a57-pmu";
 273                 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 274                                       <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 275                                       <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 276                                       <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 277                 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>;
 278         };
 279
 280         psci {
 281                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 282                 method = "smc";
 283         };
 284
 285         /* External SCIF clock - to be overridden by boards that provide it */
 286         scif_clk: scif {
 287                 compatible = "fixed-clock";
 288                 #clock-cells = <0>;
 289                 clock-frequency = <0>;
 290         };
 291
 292         soc {
 293                 compatible = "simple-bus";
 294                 interrupt-parent = <&gic>;
 295                 #address-cells = <2>;
 296                 #size-cells = <2>;
 297                 ranges;
 298
 299                 rwdt: watchdog@e6020000 {
 300                         compatible = "renesas,r8a774e1-wdt",
 301                                      "renesas,rcar-gen3-wdt";
 302                         reg = <0 0xe6020000 0 0x0c>;
 303                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 304                         clocks = <&cpg CPG_MOD 402>;
 305                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 306                         resets = <&cpg 402>;
 307                         status = "disabled";
 308                 };
 309
 310                 gpio0: gpio@e6050000 {
 311                         compatible = "renesas,gpio-r8a774e1",
 312                                      "renesas,rcar-gen3-gpio";
 313                         reg = <0 0xe6050000 0 0x50>;
 314                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 315                         #gpio-cells = <2>;
 316                         gpio-controller;
 317                         gpio-ranges = <&pfc 0 0 16>;
 318                         #interrupt-cells = <2>;
 319                         interrupt-controller;
 320                         clocks = <&cpg CPG_MOD 912>;
 321                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 322                         resets = <&cpg 912>;
 323                 };
 324
 325                 gpio1: gpio@e6051000 {
 326                         compatible = "renesas,gpio-r8a774e1",
 327                                      "renesas,rcar-gen3-gpio";
 328                         reg = <0 0xe6051000 0 0x50>;
 329                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 330                         #gpio-cells = <2>;
 331                         gpio-controller;
 332                         gpio-ranges = <&pfc 0 32 29>;
 333                         #interrupt-cells = <2>;
 334                         interrupt-controller;
 335                         clocks = <&cpg CPG_MOD 911>;
 336                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 337                         resets = <&cpg 911>;
 338                 };
 339
 340                 gpio2: gpio@e6052000 {
 341                         compatible = "renesas,gpio-r8a774e1",
 342                                      "renesas,rcar-gen3-gpio";
 343                         reg = <0 0xe6052000 0 0x50>;
 344                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 345                         #gpio-cells = <2>;
 346                         gpio-controller;
 347                         gpio-ranges = <&pfc 0 64 15>;
 348                         #interrupt-cells = <2>;
 349                         interrupt-controller;
 350                         clocks = <&cpg CPG_MOD 910>;
 351                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 352                         resets = <&cpg 910>;
 353                 };
 354
 355                 gpio3: gpio@e6053000 {
 356                         compatible = "renesas,gpio-r8a774e1",
 357                                      "renesas,rcar-gen3-gpio";
 358                         reg = <0 0xe6053000 0 0x50>;
 359                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 360                         #gpio-cells = <2>;
 361                         gpio-controller;
 362                         gpio-ranges = <&pfc 0 96 16>;
 363                         #interrupt-cells = <2>;
 364                         interrupt-controller;
 365                         clocks = <&cpg CPG_MOD 909>;
 366                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 367                         resets = <&cpg 909>;
 368                 };
 369
 370                 gpio4: gpio@e6054000 {
 371                         compatible = "renesas,gpio-r8a774e1",
 372                                      "renesas,rcar-gen3-gpio";
 373                         reg = <0 0xe6054000 0 0x50>;
 374                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 375                         #gpio-cells = <2>;
 376                         gpio-controller;
 377                         gpio-ranges = <&pfc 0 128 18>;
 378                         #interrupt-cells = <2>;
 379                         interrupt-controller;
 380                         clocks = <&cpg CPG_MOD 908>;
 381                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 382                         resets = <&cpg 908>;
 383                 };
 384
 385                 gpio5: gpio@e6055000 {
 386                         compatible = "renesas,gpio-r8a774e1",
 387                                      "renesas,rcar-gen3-gpio";
 388                         reg = <0 0xe6055000 0 0x50>;
 389                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 390                         #gpio-cells = <2>;
 391                         gpio-controller;
 392                         gpio-ranges = <&pfc 0 160 26>;
 393                         #interrupt-cells = <2>;
 394                         interrupt-controller;
 395                         clocks = <&cpg CPG_MOD 907>;
 396                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 397                         resets = <&cpg 907>;
 398                 };
 399
 400                 gpio6: gpio@e6055400 {
 401                         compatible = "renesas,gpio-r8a774e1",
 402                                      "renesas,rcar-gen3-gpio";
 403                         reg = <0 0xe6055400 0 0x50>;
 404                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 405                         #gpio-cells = <2>;
 406                         gpio-controller;
 407                         gpio-ranges = <&pfc 0 192 32>;
 408                         #interrupt-cells = <2>;
 409                         interrupt-controller;
 410                         clocks = <&cpg CPG_MOD 906>;
 411                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 412                         resets = <&cpg 906>;
 413                 };
 414
 415                 gpio7: gpio@e6055800 {
 416                         compatible = "renesas,gpio-r8a774e1",
 417                                      "renesas,rcar-gen3-gpio";
 418                         reg = <0 0xe6055800 0 0x50>;
 419                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 420                         #gpio-cells = <2>;
 421                         gpio-controller;
 422                         gpio-ranges = <&pfc 0 224 4>;
 423                         #interrupt-cells = <2>;
 424                         interrupt-controller;
 425                         clocks = <&cpg CPG_MOD 905>;
 426                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 427                         resets = <&cpg 905>;
 428                 };
 429
 430                 pfc: pin-controller@e6060000 {
 431                         compatible = "renesas,pfc-r8a774e1";
 432                         reg = <0 0xe6060000 0 0x50c>;
 433                 };
 434
 435                 cmt0: timer@e60f0000 {
 436                         compatible = "renesas,r8a774e1-cmt0",
 437                                      "renesas,rcar-gen3-cmt0";
 438                         reg = <0 0xe60f0000 0 0x1004>;
 439                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 440                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 441                         clocks = <&cpg CPG_MOD 303>;
 442                         clock-names = "fck";
 443                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 444                         resets = <&cpg 303>;
 445                         status = "disabled";
 446                 };
 447
 448                 cmt1: timer@e6130000 {
 449                         compatible = "renesas,r8a774e1-cmt1",
 450                                      "renesas,rcar-gen3-cmt1";
 451                         reg = <0 0xe6130000 0 0x1004>;
 452                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 453                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 454                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 455                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 456                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 457                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 458                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 459                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 460                         clocks = <&cpg CPG_MOD 302>;
 461                         clock-names = "fck";
 462                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 463                         resets = <&cpg 302>;
 464                         status = "disabled";
 465                 };
 466
 467                 cmt2: timer@e6140000 {
 468                         compatible = "renesas,r8a774e1-cmt1",
 469                                      "renesas,rcar-gen3-cmt1";
 470                         reg = <0 0xe6140000 0 0x1004>;
 471                         interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
 472                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
 473                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
 474                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
 475                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
 476                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
 477                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
 478                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 479                         clocks = <&cpg CPG_MOD 301>;
 480                         clock-names = "fck";
 481                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 482                         resets = <&cpg 301>;
 483                         status = "disabled";
 484                 };
 485
 486                 cmt3: timer@e6148000 {
 487                         compatible = "renesas,r8a774e1-cmt1",
 488                                      "renesas,rcar-gen3-cmt1";
 489                         reg = <0 0xe6148000 0 0x1004>;
 490                         interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
 491                                      <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
 492                                      <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
 493                                      <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
 494                                      <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
 495                                      <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
 496                                      <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
 497                                      <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
 498                         clocks = <&cpg CPG_MOD 300>;
 499                         clock-names = "fck";
 500                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 501                         resets = <&cpg 300>;
 502                         status = "disabled";
 503                 };
 504
 505                 cpg: clock-controller@e6150000 {
 506                         compatible = "renesas,r8a774e1-cpg-mssr";
 507                         reg = <0 0xe6150000 0 0x1000>;
 508                         clocks = <&extal_clk>, <&extalr_clk>;
 509                         clock-names = "extal", "extalr";
 510                         #clock-cells = <2>;
 511                         #power-domain-cells = <0>;
 512                         #reset-cells = <1>;
 513                 };
 514
 515                 rst: reset-controller@e6160000 {
 516                         compatible = "renesas,r8a774e1-rst";
 517                         reg = <0 0xe6160000 0 0x0200>;
 518                 };
 519
 520                 sysc: system-controller@e6180000 {
 521                         compatible = "renesas,r8a774e1-sysc";
 522                         reg = <0 0xe6180000 0 0x0400>;
 523                         #power-domain-cells = <1>;
 524                 };
 525
 526                 tsc: thermal@e6198000 {
 527                         compatible = "renesas,r8a774e1-thermal";
 528                         reg = <0 0xe6198000 0 0x100>,
 529                               <0 0xe61a0000 0 0x100>,
 530                               <0 0xe61a8000 0 0x100>;
 531                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 532                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 533                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 534                         clocks = <&cpg CPG_MOD 522>;
 535                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 536                         resets = <&cpg 522>;
 537                         #thermal-sensor-cells = <1>;
 538                 };
 539
 540                 intc_ex: interrupt-controller@e61c0000 {
 541                         compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc";
 542                         #interrupt-cells = <2>;
 543                         interrupt-controller;
 544                         reg = <0 0xe61c0000 0 0x200>;
 545                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 546                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 547                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 548                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 549                                      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 550                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 551                         clocks = <&cpg CPG_MOD 407>;
 552                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 553                         resets = <&cpg 407>;
 554                 };
 555
 556                 tmu0: timer@e61e0000 {
 557                         compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
 558                         reg = <0 0xe61e0000 0 0x30>;
 559                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 560                                      <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 561                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 562                         clocks = <&cpg CPG_MOD 125>;
 563                         clock-names = "fck";
 564                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 565                         resets = <&cpg 125>;
 566                         status = "disabled";
 567                 };
 568
 569                 tmu1: timer@e6fc0000 {
 570                         compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
 571                         reg = <0 0xe6fc0000 0 0x30>;
 572                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 573                                      <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 574                                      <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
 575                         clocks = <&cpg CPG_MOD 124>;
 576                         clock-names = "fck";
 577                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 578                         resets = <&cpg 124>;
 579                         status = "disabled";
 580                 };
 581
 582                 tmu2: timer@e6fd0000 {
 583                         compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
 584                         reg = <0 0xe6fd0000 0 0x30>;
 585                         interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
 586                                      <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
 587                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
 588                         clocks = <&cpg CPG_MOD 123>;
 589                         clock-names = "fck";
 590                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 591                         resets = <&cpg 123>;
 592                         status = "disabled";
 593                 };
 594
 595                 tmu3: timer@e6fe0000 {
 596                         compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
 597                         reg = <0 0xe6fe0000 0 0x30>;
 598                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 599                                      <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 600                                      <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 601                         clocks = <&cpg CPG_MOD 122>;
 602                         clock-names = "fck";
 603                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 604                         resets = <&cpg 122>;
 605                         status = "disabled";
 606                 };
 607
 608                 tmu4: timer@ffc00000 {
 609                         compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
 610                         reg = <0 0xffc00000 0 0x30>;
 611                         interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
 612                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
 613                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
 614                         clocks = <&cpg CPG_MOD 121>;
 615                         clock-names = "fck";
 616                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 617                         resets = <&cpg 121>;
 618                         status = "disabled";
 619                 };
 620
 621                 i2c0: i2c@e6500000 {
 622                         #address-cells = <1>;
 623                         #size-cells = <0>;
 624                         compatible = "renesas,i2c-r8a774e1",
 625                                      "renesas,rcar-gen3-i2c";
 626                         reg = <0 0xe6500000 0 0x40>;
 627                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 628                         clocks = <&cpg CPG_MOD 931>;
 629                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 630                         resets = <&cpg 931>;
 631                         dmas = <&dmac1 0x91>, <&dmac1 0x90>,
 632                                <&dmac2 0x91>, <&dmac2 0x90>;
 633                         dma-names = "tx", "rx", "tx", "rx";
 634                         i2c-scl-internal-delay-ns = <110>;
 635                         status = "disabled";
 636                 };
 637
 638                 i2c1: i2c@e6508000 {
 639                         #address-cells = <1>;
 640                         #size-cells = <0>;
 641                         compatible = "renesas,i2c-r8a774e1",
 642                                      "renesas,rcar-gen3-i2c";
 643                         reg = <0 0xe6508000 0 0x40>;
 644                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 645                         clocks = <&cpg CPG_MOD 930>;
 646                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 647                         resets = <&cpg 930>;
 648                         dmas = <&dmac1 0x93>, <&dmac1 0x92>,
 649                                <&dmac2 0x93>, <&dmac2 0x92>;
 650                         dma-names = "tx", "rx", "tx", "rx";
 651                         i2c-scl-internal-delay-ns = <6>;
 652                         status = "disabled";
 653                 };
 654
 655                 i2c2: i2c@e6510000 {
 656                         #address-cells = <1>;
 657                         #size-cells = <0>;
 658                         compatible = "renesas,i2c-r8a774e1",
 659                                      "renesas,rcar-gen3-i2c";
 660                         reg = <0 0xe6510000 0 0x40>;
 661                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 662                         clocks = <&cpg CPG_MOD 929>;
 663                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 664                         resets = <&cpg 929>;
 665                         dmas = <&dmac1 0x95>, <&dmac1 0x94>,
 666                                <&dmac2 0x95>, <&dmac2 0x94>;
 667                         dma-names = "tx", "rx", "tx", "rx";
 668                         i2c-scl-internal-delay-ns = <6>;
 669                         status = "disabled";
 670                 };
 671
 672                 i2c3: i2c@e66d0000 {
 673                         #address-cells = <1>;
 674                         #size-cells = <0>;
 675                         compatible = "renesas,i2c-r8a774e1",
 676                                      "renesas,rcar-gen3-i2c";
 677                         reg = <0 0xe66d0000 0 0x40>;
 678                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 679                         clocks = <&cpg CPG_MOD 928>;
 680                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 681                         resets = <&cpg 928>;
 682                         dmas = <&dmac0 0x97>, <&dmac0 0x96>;
 683                         dma-names = "tx", "rx";
 684                         i2c-scl-internal-delay-ns = <110>;
 685                         status = "disabled";
 686                 };
 687
 688                 i2c4: i2c@e66d8000 {
 689                         #address-cells = <1>;
 690                         #size-cells = <0>;
 691                         compatible = "renesas,i2c-r8a774e1",
 692                                      "renesas,rcar-gen3-i2c";
 693                         reg = <0 0xe66d8000 0 0x40>;
 694                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 695                         clocks = <&cpg CPG_MOD 927>;
 696                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 697                         resets = <&cpg 927>;
 698                         dmas = <&dmac0 0x99>, <&dmac0 0x98>;
 699                         dma-names = "tx", "rx";
 700                         i2c-scl-internal-delay-ns = <110>;
 701                         status = "disabled";
 702                 };
 703
 704                 i2c5: i2c@e66e0000 {
 705                         #address-cells = <1>;
 706                         #size-cells = <0>;
 707                         compatible = "renesas,i2c-r8a774e1",
 708                                      "renesas,rcar-gen3-i2c";
 709                         reg = <0 0xe66e0000 0 0x40>;
 710                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 711                         clocks = <&cpg CPG_MOD 919>;
 712                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 713                         resets = <&cpg 919>;
 714                         dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
 715                         dma-names = "tx", "rx";
 716                         i2c-scl-internal-delay-ns = <110>;
 717                         status = "disabled";
 718                 };
 719
 720                 i2c6: i2c@e66e8000 {
 721                         #address-cells = <1>;
 722                         #size-cells = <0>;
 723                         compatible = "renesas,i2c-r8a774e1",
 724                                      "renesas,rcar-gen3-i2c";
 725                         reg = <0 0xe66e8000 0 0x40>;
 726                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 727                         clocks = <&cpg CPG_MOD 918>;
 728                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 729                         resets = <&cpg 918>;
 730                         dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
 731                         dma-names = "tx", "rx";
 732                         i2c-scl-internal-delay-ns = <6>;
 733                         status = "disabled";
 734                 };
 735
 736                 i2c_dvfs: i2c@e60b0000 {
 737                         #address-cells = <1>;
 738                         #size-cells = <0>;
 739                         compatible = "renesas,iic-r8a774e1",
 740                                      "renesas,rcar-gen3-iic",
 741                                      "renesas,rmobile-iic";
 742                         reg = <0 0xe60b0000 0 0x425>;
 743                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 744                         clocks = <&cpg CPG_MOD 926>;
 745                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 746                         resets = <&cpg 926>;
 747                         dmas = <&dmac0 0x11>, <&dmac0 0x10>;
 748                         dma-names = "tx", "rx";
 749                         status = "disabled";
 750                 };
 751
 752                 hscif0: serial@e6540000 {
 753                         compatible = "renesas,hscif-r8a774e1",
 754                                      "renesas,rcar-gen3-hscif",
 755                                      "renesas,hscif";
 756                         reg = <0 0xe6540000 0 0x60>;
 757                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 758                         clocks = <&cpg CPG_MOD 520>,
 759                                  <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
 760                                  <&scif_clk>;
 761                         clock-names = "fck", "brg_int", "scif_clk";
 762                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 763                                <&dmac2 0x31>, <&dmac2 0x30>;
 764                         dma-names = "tx", "rx", "tx", "rx";
 765                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 766                         resets = <&cpg 520>;
 767                         status = "disabled";
 768                 };
 769
 770                 hscif1: serial@e6550000 {
 771                         compatible = "renesas,hscif-r8a774e1",
 772                                      "renesas,rcar-gen3-hscif",
 773                                      "renesas,hscif";
 774                         reg = <0 0xe6550000 0 0x60>;
 775                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 776                         clocks = <&cpg CPG_MOD 519>,
 777                                  <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
 778                                  <&scif_clk>;
 779                         clock-names = "fck", "brg_int", "scif_clk";
 780                         dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 781                                <&dmac2 0x33>, <&dmac2 0x32>;
 782                         dma-names = "tx", "rx", "tx", "rx";
 783                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 784                         resets = <&cpg 519>;
 785                         status = "disabled";
 786                 };
 787
 788                 hscif2: serial@e6560000 {
 789                         compatible = "renesas,hscif-r8a774e1",
 790                                      "renesas,rcar-gen3-hscif",
 791                                      "renesas,hscif";
 792                         reg = <0 0xe6560000 0 0x60>;
 793                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 794                         clocks = <&cpg CPG_MOD 518>,
 795                                  <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
 796                                  <&scif_clk>;
 797                         clock-names = "fck", "brg_int", "scif_clk";
 798                         dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 799                                <&dmac2 0x35>, <&dmac2 0x34>;
 800                         dma-names = "tx", "rx", "tx", "rx";
 801                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 802                         resets = <&cpg 518>;
 803                         status = "disabled";
 804                 };
 805
 806                 hscif3: serial@e66a0000 {
 807                         compatible = "renesas,hscif-r8a774e1",
 808                                      "renesas,rcar-gen3-hscif",
 809                                      "renesas,hscif";
 810                         reg = <0 0xe66a0000 0 0x60>;
 811                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 812                         clocks = <&cpg CPG_MOD 517>,
 813                                  <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
 814                                  <&scif_clk>;
 815                         clock-names = "fck", "brg_int", "scif_clk";
 816                         dmas = <&dmac0 0x37>, <&dmac0 0x36>;
 817                         dma-names = "tx", "rx";
 818                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 819                         resets = <&cpg 517>;
 820                         status = "disabled";
 821                 };
 822
 823                 hscif4: serial@e66b0000 {
 824                         compatible = "renesas,hscif-r8a774e1",
 825                                      "renesas,rcar-gen3-hscif",
 826                                      "renesas,hscif";
 827                         reg = <0 0xe66b0000 0 0x60>;
 828                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 829                         clocks = <&cpg CPG_MOD 516>,
 830                                  <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
 831                                  <&scif_clk>;
 832                         clock-names = "fck", "brg_int", "scif_clk";
 833                         dmas = <&dmac0 0x39>, <&dmac0 0x38>;
 834                         dma-names = "tx", "rx";
 835                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 836                         resets = <&cpg 516>;
 837                         status = "disabled";
 838                 };
 839
 840                 hsusb: usb@e6590000 {
 841                         reg = <0 0xe6590000 0 0x200>;
 842                         status = "disabled";
 843
 844                         /* placeholder */
 845                 };
 846
 847                 usb3_phy0: usb-phy@e65ee000 {
 848                         reg = <0 0xe65ee000 0 0x90>;
 849                         #phy-cells = <0>;
 850                         status = "disabled";
 851
 852                         /* placeholder */
 853                 };
 854
 855                 dmac0: dma-controller@e6700000 {
 856                         compatible = "renesas,dmac-r8a774e1",
 857                                      "renesas,rcar-dmac";
 858                         reg = <0 0xe6700000 0 0x10000>;
 859                         interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 860                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 861                                      <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 862                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 863                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 864                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
 865                                      <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
 866                                      <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
 867                                      <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 868                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 869                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
 870                                      <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 871                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 872                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 873                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 874                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 875                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 876                         interrupt-names = "error",
 877                                           "ch0", "ch1", "ch2", "ch3",
 878                                           "ch4", "ch5", "ch6", "ch7",
 879                                           "ch8", "ch9", "ch10", "ch11",
 880                                           "ch12", "ch13", "ch14", "ch15";
 881                         clocks = <&cpg CPG_MOD 219>;
 882                         clock-names = "fck";
 883                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 884                         resets = <&cpg 219>;
 885                         #dma-cells = <1>;
 886                         dma-channels = <16>;
 887                         iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
 888                                  <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
 889                                  <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
 890                                  <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
 891                                  <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
 892                                  <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
 893                                  <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
 894                                  <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
 895                 };
 896
 897                 dmac1: dma-controller@e7300000 {
 898                         compatible = "renesas,dmac-r8a774e1",
 899                                      "renesas,rcar-dmac";
 900                         reg = <0 0xe7300000 0 0x10000>;
 901                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
 902                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
 903                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
 904                                      <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 905                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 906                                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
 907                                      <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
 908                                      <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
 909                                      <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
 910                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
 911                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
 912                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
 913                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
 914                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
 915                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
 916                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
 917                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 918                         interrupt-names = "error",
 919                                           "ch0", "ch1", "ch2", "ch3",
 920                                           "ch4", "ch5", "ch6", "ch7",
 921                                           "ch8", "ch9", "ch10", "ch11",
 922                                           "ch12", "ch13", "ch14", "ch15";
 923                         clocks = <&cpg CPG_MOD 218>;
 924                         clock-names = "fck";
 925                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 926                         resets = <&cpg 218>;
 927                         #dma-cells = <1>;
 928                         dma-channels = <16>;
 929                         iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
 930                                  <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
 931                                  <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
 932                                  <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
 933                                  <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
 934                                  <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
 935                                  <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
 936                                  <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
 937                 };
 938
 939                 dmac2: dma-controller@e7310000 {
 940                         compatible = "renesas,dmac-r8a774e1",
 941                                      "renesas,rcar-dmac";
 942                         reg = <0 0xe7310000 0 0x10000>;
 943                         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 944                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
 945                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
 946                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
 947                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
 948                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
 949                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
 950                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 951                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
 952                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
 953                                      <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
 954                                      <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
 955                                      <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
 956                                      <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
 957                                      <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
 958                                      <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
 959                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 960                         interrupt-names = "error",
 961                                           "ch0", "ch1", "ch2", "ch3",
 962                                           "ch4", "ch5", "ch6", "ch7",
 963                                           "ch8", "ch9", "ch10", "ch11",
 964                                           "ch12", "ch13", "ch14", "ch15";
 965                         clocks = <&cpg CPG_MOD 217>;
 966                         clock-names = "fck";
 967                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 968                         resets = <&cpg 217>;
 969                         #dma-cells = <1>;
 970                         dma-channels = <16>;
 971                         iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
 972                                  <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
 973                                  <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
 974                                  <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
 975                                  <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
 976                                  <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
 977                                  <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
 978                                  <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
 979                 };
 980
 981                 ipmmu_ds0: iommu@e6740000 {
 982                         compatible = "renesas,ipmmu-r8a774e1";
 983                         reg = <0 0xe6740000 0 0x1000>;
 984                         renesas,ipmmu-main = <&ipmmu_mm 0>;
 985                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 986                         #iommu-cells = <1>;
 987                 };
 988
 989                 ipmmu_ds1: iommu@e7740000 {
 990                         compatible = "renesas,ipmmu-r8a774e1";
 991                         reg = <0 0xe7740000 0 0x1000>;
 992                         renesas,ipmmu-main = <&ipmmu_mm 1>;
 993                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
 994                         #iommu-cells = <1>;
 995                 };
 996
 997                 ipmmu_hc: iommu@e6570000 {
 998                         compatible = "renesas,ipmmu-r8a774e1";
 999                         reg = <0 0xe6570000 0 0x1000>;
1000                         renesas,ipmmu-main = <&ipmmu_mm 2>;
1001                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1002                         #iommu-cells = <1>;
1003                 };
1004
1005                 ipmmu_mm: iommu@e67b0000 {
1006                         compatible = "renesas,ipmmu-r8a774e1";
1007                         reg = <0 0xe67b0000 0 0x1000>;
1008                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1009                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1010                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1011                         #iommu-cells = <1>;
1012                 };
1013
1014                 ipmmu_mp0: iommu@ec670000 {
1015                         compatible = "renesas,ipmmu-r8a774e1";
1016                         reg = <0 0xec670000 0 0x1000>;
1017                         renesas,ipmmu-main = <&ipmmu_mm 4>;
1018                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1019                         #iommu-cells = <1>;
1020                 };
1021
1022                 ipmmu_pv0: iommu@fd800000 {
1023                         compatible = "renesas,ipmmu-r8a774e1";
1024                         reg = <0 0xfd800000 0 0x1000>;
1025                         renesas,ipmmu-main = <&ipmmu_mm 6>;
1026                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1027                         #iommu-cells = <1>;
1028                 };
1029
1030                 ipmmu_pv1: iommu@fd950000 {
1031                         compatible = "renesas,ipmmu-r8a774e1";
1032                         reg = <0 0xfd950000 0 0x1000>;
1033                         renesas,ipmmu-main = <&ipmmu_mm 7>;
1034                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1035                         #iommu-cells = <1>;
1036                 };
1037
1038                 ipmmu_pv2: iommu@fd960000 {
1039                         compatible = "renesas,ipmmu-r8a774e1";
1040                         reg = <0 0xfd960000 0 0x1000>;
1041                         renesas,ipmmu-main = <&ipmmu_mm 8>;
1042                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1043                         #iommu-cells = <1>;
1044                 };
1045
1046                 ipmmu_pv3: iommu@fd970000 {
1047                         compatible = "renesas,ipmmu-r8a774e1";
1048                         reg = <0 0xfd970000 0 0x1000>;
1049                         renesas,ipmmu-main = <&ipmmu_mm 9>;
1050                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1051                         #iommu-cells = <1>;
1052                 };
1053
1054                 ipmmu_vc0: iommu@fe6b0000 {
1055                         compatible = "renesas,ipmmu-r8a774e1";
1056                         reg = <0 0xfe6b0000 0 0x1000>;
1057                         renesas,ipmmu-main = <&ipmmu_mm 12>;
1058                         power-domains = <&sysc R8A774E1_PD_A3VC>;
1059                         #iommu-cells = <1>;
1060                 };
1061
1062                 ipmmu_vc1: iommu@fe6f0000 {
1063                         compatible = "renesas,ipmmu-r8a774e1";
1064                         reg = <0 0xfe6f0000 0 0x1000>;
1065                         renesas,ipmmu-main = <&ipmmu_mm 13>;
1066                         power-domains = <&sysc R8A774E1_PD_A3VC>;
1067                         #iommu-cells = <1>;
1068                 };
1069
1070                 ipmmu_vi0: iommu@febd0000 {
1071                         compatible = "renesas,ipmmu-r8a774e1";
1072                         reg = <0 0xfebd0000 0 0x1000>;
1073                         renesas,ipmmu-main = <&ipmmu_mm 14>;
1074                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1075                         #iommu-cells = <1>;
1076                 };
1077
1078                 ipmmu_vi1: iommu@febe0000 {
1079                         compatible = "renesas,ipmmu-r8a774e1";
1080                         reg = <0 0xfebe0000 0 0x1000>;
1081                         renesas,ipmmu-main = <&ipmmu_mm 15>;
1082                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1083                         #iommu-cells = <1>;
1084                 };
1085
1086                 ipmmu_vp0: iommu@fe990000 {
1087                         compatible = "renesas,ipmmu-r8a774e1";
1088                         reg = <0 0xfe990000 0 0x1000>;
1089                         renesas,ipmmu-main = <&ipmmu_mm 16>;
1090                         power-domains = <&sysc R8A774E1_PD_A3VP>;
1091                         #iommu-cells = <1>;
1092                 };
1093
1094                 ipmmu_vp1: iommu@fe980000 {
1095                         compatible = "renesas,ipmmu-r8a774e1";
1096                         reg = <0 0xfe980000 0 0x1000>;
1097                         renesas,ipmmu-main = <&ipmmu_mm 17>;
1098                         power-domains = <&sysc R8A774E1_PD_A3VP>;
1099                         #iommu-cells = <1>;
1100                 };
1101
1102                 avb: ethernet@e6800000 {
1103                         compatible = "renesas,etheravb-r8a774e1",
1104                                      "renesas,etheravb-rcar-gen3";
1105                         reg = <0 0xe6800000 0 0x800>;
1106                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1107                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1108                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1109                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1110                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1111                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1112                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1113                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1114                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1115                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1116                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1117                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1118                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1119                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1120                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1121                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1122                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1123                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1124                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1125                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1126                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1127                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1128                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1129                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1130                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1131                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
1132                                           "ch4", "ch5", "ch6", "ch7",
1133                                           "ch8", "ch9", "ch10", "ch11",
1134                                           "ch12", "ch13", "ch14", "ch15",
1135                                           "ch16", "ch17", "ch18", "ch19",
1136                                           "ch20", "ch21", "ch22", "ch23",
1137                                           "ch24";
1138                         clocks = <&cpg CPG_MOD 812>;
1139                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1140                         resets = <&cpg 812>;
1141                         phy-mode = "rgmii";
1142                         iommus = <&ipmmu_ds0 16>;
1143                         #address-cells = <1>;
1144                         #size-cells = <0>;
1145                         status = "disabled";
1146                 };
1147
1148                 can0: can@e6c30000 {
1149                         compatible = "renesas,can-r8a774e1",
1150                                      "renesas,rcar-gen3-can";
1151                         reg = <0 0xe6c30000 0 0x1000>;
1152                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1153                         clocks = <&cpg CPG_MOD 916>,
1154                                  <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1155                                  <&can_clk>;
1156                         clock-names = "clkp1", "clkp2", "can_clk";
1157                         assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1158                         assigned-clock-rates = <40000000>;
1159                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1160                         resets = <&cpg 916>;
1161                         status = "disabled";
1162                 };
1163
1164                 can1: can@e6c38000 {
1165                         compatible = "renesas,can-r8a774e1",
1166                                      "renesas,rcar-gen3-can";
1167                         reg = <0 0xe6c38000 0 0x1000>;
1168                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1169                         clocks = <&cpg CPG_MOD 915>,
1170                                  <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1171                                  <&can_clk>;
1172                         clock-names = "clkp1", "clkp2", "can_clk";
1173                         assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1174                         assigned-clock-rates = <40000000>;
1175                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1176                         resets = <&cpg 915>;
1177                         status = "disabled";
1178                 };
1179
1180                 canfd: can@e66c0000 {
1181                         compatible = "renesas,r8a774e1-canfd",
1182                                      "renesas,rcar-gen3-canfd";
1183                         reg = <0 0xe66c0000 0 0x8000>;
1184                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1185                                      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1186                         clocks = <&cpg CPG_MOD 914>,
1187                                  <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1188                                  <&can_clk>;
1189                         clock-names = "fck", "canfd", "can_clk";
1190                         assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1191                         assigned-clock-rates = <40000000>;
1192                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1193                         resets = <&cpg 914>;
1194                         status = "disabled";
1195
1196                         channel0 {
1197                                 status = "disabled";
1198                         };
1199
1200                         channel1 {
1201                                 status = "disabled";
1202                         };
1203                 };
1204
1205                 pwm0: pwm@e6e30000 {
1206                         reg = <0 0xe6e30000 0 0x8>;
1207                         #pwm-cells = <2>;
1208                         status = "disabled";
1209
1210                         /* placeholder */
1211                 };
1212
1213                 scif0: serial@e6e60000 {
1214                         compatible = "renesas,scif-r8a774e1",
1215                                      "renesas,rcar-gen3-scif", "renesas,scif";
1216                         reg = <0 0xe6e60000 0 0x40>;
1217                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1218                         clocks = <&cpg CPG_MOD 207>,
1219                                  <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1220                                  <&scif_clk>;
1221                         clock-names = "fck", "brg_int", "scif_clk";
1222                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1223                                <&dmac2 0x51>, <&dmac2 0x50>;
1224                         dma-names = "tx", "rx", "tx", "rx";
1225                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1226                         resets = <&cpg 207>;
1227                         status = "disabled";
1228                 };
1229
1230                 scif1: serial@e6e68000 {
1231                         compatible = "renesas,scif-r8a774e1",
1232                                      "renesas,rcar-gen3-scif", "renesas,scif";
1233                         reg = <0 0xe6e68000 0 0x40>;
1234                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1235                         clocks = <&cpg CPG_MOD 206>,
1236                                  <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1237                                  <&scif_clk>;
1238                         clock-names = "fck", "brg_int", "scif_clk";
1239                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1240                                <&dmac2 0x53>, <&dmac2 0x52>;
1241                         dma-names = "tx", "rx", "tx", "rx";
1242                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1243                         resets = <&cpg 206>;
1244                         status = "disabled";
1245                 };
1246
1247                 scif2: serial@e6e88000 {
1248                         compatible = "renesas,scif-r8a774e1",
1249                                      "renesas,rcar-gen3-scif", "renesas,scif";
1250                         reg = <0 0xe6e88000 0 0x40>;
1251                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1252                         clocks = <&cpg CPG_MOD 310>,
1253                                  <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1254                                  <&scif_clk>;
1255                         clock-names = "fck", "brg_int", "scif_clk";
1256                         dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1257                                <&dmac2 0x13>, <&dmac2 0x12>;
1258                         dma-names = "tx", "rx", "tx", "rx";
1259                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1260                         resets = <&cpg 310>;
1261                         status = "disabled";
1262                 };
1263
1264                 scif3: serial@e6c50000 {
1265                         compatible = "renesas,scif-r8a774e1",
1266                                      "renesas,rcar-gen3-scif", "renesas,scif";
1267                         reg = <0 0xe6c50000 0 0x40>;
1268                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1269                         clocks = <&cpg CPG_MOD 204>,
1270                                  <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1271                                  <&scif_clk>;
1272                         clock-names = "fck", "brg_int", "scif_clk";
1273                         dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1274                         dma-names = "tx", "rx";
1275                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1276                         resets = <&cpg 204>;
1277                         status = "disabled";
1278                 };
1279
1280                 scif4: serial@e6c40000 {
1281                         compatible = "renesas,scif-r8a774e1",
1282                                      "renesas,rcar-gen3-scif", "renesas,scif";
1283                         reg = <0 0xe6c40000 0 0x40>;
1284                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1285                         clocks = <&cpg CPG_MOD 203>,
1286                                  <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1287                                  <&scif_clk>;
1288                         clock-names = "fck", "brg_int", "scif_clk";
1289                         dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1290                         dma-names = "tx", "rx";
1291                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1292                         resets = <&cpg 203>;
1293                         status = "disabled";
1294                 };
1295
1296                 scif5: serial@e6f30000 {
1297                         compatible = "renesas,scif-r8a774e1",
1298                                      "renesas,rcar-gen3-scif", "renesas,scif";
1299                         reg = <0 0xe6f30000 0 0x40>;
1300                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1301                         clocks = <&cpg CPG_MOD 202>,
1302                                  <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1303                                  <&scif_clk>;
1304                         clock-names = "fck", "brg_int", "scif_clk";
1305                         dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1306                                <&dmac2 0x5b>, <&dmac2 0x5a>;
1307                         dma-names = "tx", "rx", "tx", "rx";
1308                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1309                         resets = <&cpg 202>;
1310                         status = "disabled";
1311                 };
1312
1313                 msiof0: spi@e6e90000 {
1314                         compatible = "renesas,msiof-r8a774e1",
1315                                      "renesas,rcar-gen3-msiof";
1316                         reg = <0 0xe6e90000 0 0x0064>;
1317                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1318                         clocks = <&cpg CPG_MOD 211>;
1319                         dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1320                                <&dmac2 0x41>, <&dmac2 0x40>;
1321                         dma-names = "tx", "rx", "tx", "rx";
1322                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1323                         resets = <&cpg 211>;
1324                         #address-cells = <1>;
1325                         #size-cells = <0>;
1326                         status = "disabled";
1327                 };
1328
1329                 msiof1: spi@e6ea0000 {
1330                         compatible = "renesas,msiof-r8a774e1",
1331                                      "renesas,rcar-gen3-msiof";
1332                         reg = <0 0xe6ea0000 0 0x0064>;
1333                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1334                         clocks = <&cpg CPG_MOD 210>;
1335                         dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1336                                <&dmac2 0x43>, <&dmac2 0x42>;
1337                         dma-names = "tx", "rx", "tx", "rx";
1338                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1339                         resets = <&cpg 210>;
1340                         #address-cells = <1>;
1341                         #size-cells = <0>;
1342                         status = "disabled";
1343                 };
1344
1345                 msiof2: spi@e6c00000 {
1346                         compatible = "renesas,msiof-r8a774e1",
1347                                      "renesas,rcar-gen3-msiof";
1348                         reg = <0 0xe6c00000 0 0x0064>;
1349                         interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1350                         clocks = <&cpg CPG_MOD 209>;
1351                         dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1352                         dma-names = "tx", "rx";
1353                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1354                         resets = <&cpg 209>;
1355                         #address-cells = <1>;
1356                         #size-cells = <0>;
1357                         status = "disabled";
1358                 };
1359
1360                 msiof3: spi@e6c10000 {
1361                         compatible = "renesas,msiof-r8a774e1",
1362                                      "renesas,rcar-gen3-msiof";
1363                         reg = <0 0xe6c10000 0 0x0064>;
1364                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1365                         clocks = <&cpg CPG_MOD 208>;
1366                         dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1367                         dma-names = "tx", "rx";
1368                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1369                         resets = <&cpg 208>;
1370                         #address-cells = <1>;
1371                         #size-cells = <0>;
1372                         status = "disabled";
1373                 };
1374
1375                 rcar_sound: sound@ec500000 {
1376                         reg = <0 0xec500000 0 0x1000>, /* SCU */
1377                               <0 0xec5a0000 0 0x100>,  /* ADG */
1378                               <0 0xec540000 0 0x1000>, /* SSIU */
1379                               <0 0xec541000 0 0x280>,  /* SSI */
1380                               <0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
1381                         reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1382
1383                         status = "disabled";
1384
1385                         /* placeholder */
1386
1387                         rcar_sound,ssi {
1388                                 ssi2: ssi-2 {
1389                                         /* placeholder */
1390                                 };
1391                         };
1392                 };
1393
1394                 xhci0: usb@ee000000 {
1395                         reg = <0 0xee000000 0 0xc00>;
1396                         status = "disabled";
1397
1398                         /* placeholder */
1399                 };
1400
1401                 usb3_peri0: usb@ee020000 {
1402                         reg = <0 0xee020000 0 0x400>;
1403                         status = "disabled";
1404
1405                         /* placeholder */
1406                 };
1407
1408                 ohci0: usb@ee080000 {
1409                         reg = <0 0xee080000 0 0x100>;
1410                         status = "disabled";
1411
1412                         /* placeholder */
1413                 };
1414
1415                 ohci1: usb@ee0a0000 {
1416                         reg = <0 0xee0a0000 0 0x100>;
1417                         status = "disabled";
1418
1419                         /* placeholder */
1420                 };
1421
1422                 ehci0: usb@ee080100 {
1423                         reg = <0 0xee080100 0 0x100>;
1424                         status = "disabled";
1425
1426                         /* placeholder */
1427                 };
1428
1429                 ehci1: usb@ee0a0100 {
1430                         reg = <0 0xee0a0100 0 0x100>;
1431                         status = "disabled";
1432
1433                         /* placeholder */
1434                 };
1435
1436                 usb2_phy0: usb-phy@ee080200 {
1437                         reg = <0 0xee080200 0 0x700>;
1438                         status = "disabled";
1439
1440                         /* placeholder */
1441                 };
1442
1443                 usb2_phy1: usb-phy@ee0a0200 {
1444                         reg = <0 0xee0a0200 0 0x700>;
1445                         status = "disabled";
1446
1447                         /* placeholder */
1448                 };
1449
1450                 sdhi0: mmc@ee100000 {
1451                         compatible = "renesas,sdhi-r8a774e1",
1452                                      "renesas,rcar-gen3-sdhi";
1453                         reg = <0 0xee100000 0 0x2000>;
1454                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1455                         clocks = <&cpg CPG_MOD 314>;
1456                         max-frequency = <200000000>;
1457                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1458                         resets = <&cpg 314>;
1459                         iommus = <&ipmmu_ds1 32>;
1460                         status = "disabled";
1461                 };
1462
1463                 sdhi1: mmc@ee120000 {
1464                         compatible = "renesas,sdhi-r8a774e1",
1465                                      "renesas,rcar-gen3-sdhi";
1466                         reg = <0 0xee120000 0 0x2000>;
1467                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1468                         clocks = <&cpg CPG_MOD 313>;
1469                         max-frequency = <200000000>;
1470                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1471                         resets = <&cpg 313>;
1472                         iommus = <&ipmmu_ds1 33>;
1473                         status = "disabled";
1474                 };
1475
1476                 sdhi2: mmc@ee140000 {
1477                         compatible = "renesas,sdhi-r8a774e1",
1478                                      "renesas,rcar-gen3-sdhi";
1479                         reg = <0 0xee140000 0 0x2000>;
1480                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1481                         clocks = <&cpg CPG_MOD 312>;
1482                         max-frequency = <200000000>;
1483                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1484                         resets = <&cpg 312>;
1485                         iommus = <&ipmmu_ds1 34>;
1486                         status = "disabled";
1487                 };
1488
1489                 sdhi3: mmc@ee160000 {
1490                         compatible = "renesas,sdhi-r8a774e1",
1491                                      "renesas,rcar-gen3-sdhi";
1492                         reg = <0 0xee160000 0 0x2000>;
1493                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1494                         clocks = <&cpg CPG_MOD 311>;
1495                         max-frequency = <200000000>;
1496                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1497                         resets = <&cpg 311>;
1498                         iommus = <&ipmmu_ds1 35>;
1499                         status = "disabled";
1500                 };
1501
1502                 gic: interrupt-controller@f1010000 {
1503                         compatible = "arm,gic-400";
1504                         #interrupt-cells = <3>;
1505                         #address-cells = <0>;
1506                         interrupt-controller;
1507                         reg = <0x0 0xf1010000 0 0x1000>,
1508                               <0x0 0xf1020000 0 0x20000>,
1509                               <0x0 0xf1040000 0 0x20000>,
1510                               <0x0 0xf1060000 0 0x20000>;
1511                         interrupts = <GIC_PPI 9
1512                                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1513                         clocks = <&cpg CPG_MOD 408>;
1514                         clock-names = "clk";
1515                         power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1516                         resets = <&cpg 408>;
1517                 };
1518
1519                 pciec0: pcie@fe000000 {
1520                         reg = <0 0xfe000000 0 0x80000>;
1521                         #address-cells = <3>;
1522                         #size-cells = <2>;
1523                         status = "disabled";
1524
1525                         /* placeholder */
1526                 };
1527
1528                 hdmi0: hdmi@fead0000 {
1529                         reg = <0 0xfead0000 0 0x10000>;
1530                         status = "disabled";
1531
1532                         /* placeholder */
1533
1534                         ports {
1535                                 #address-cells = <1>;
1536                                 #size-cells = <0>;
1537
1538                                 port@0 {
1539                                         reg = <0>;
1540                                 };
1541                                 port@1 {
1542                                         reg = <1>;
1543                                 };
1544                                 port@2 {
1545                                         reg = <2>;
1546                                 };
1547                         };
1548                 };
1549
1550                 du: display@feb00000 {
1551                         reg = <0 0xfeb00000 0 0x80000>;
1552                         status = "disabled";
1553
1554                         /* placeholder */
1555                         ports {
1556                                 #address-cells = <1>;
1557                                 #size-cells = <0>;
1558
1559                                 port@0 {
1560                                         reg = <0>;
1561                                 };
1562                                 port@1 {
1563                                         reg = <1>;
1564                                 };
1565                                 port@2 {
1566                                         reg = <2>;
1567                                 };
1568                         };
1569                 };
1570
1571                 prr: chipid@fff00044 {
1572                         compatible = "renesas,prr";
1573                         reg = <0 0xfff00044 0 4>;
1574                 };
1575         };
1576
1577         thermal-zones {
1578                 sensor_thermal1: sensor-thermal1 {
1579                         polling-delay-passive = <250>;
1580                         polling-delay = <1000>;
1581                         thermal-sensors = <&tsc 0>;
1582                         sustainable-power = <6313>;
1583
1584                         trips {
1585                                 sensor1_crit: sensor1-crit {
1586                                         temperature = <120000>;
1587                                         hysteresis = <1000>;
1588                                         type = "critical";
1589                                 };
1590                         };
1591                 };
1592
1593                 sensor_thermal2: sensor-thermal2 {
1594                         polling-delay-passive = <250>;
1595                         polling-delay = <1000>;
1596                         thermal-sensors = <&tsc 1>;
1597                         sustainable-power = <6313>;
1598
1599                         trips {
1600                                 sensor2_crit: sensor2-crit {
1601                                         temperature = <120000>;
1602                                         hysteresis = <1000>;
1603                                         type = "critical";
1604                                 };
1605                         };
1606                 };
1607
1608                 sensor_thermal3: sensor-thermal3 {
1609                         polling-delay-passive = <250>;
1610                         polling-delay = <1000>;
1611                         thermal-sensors = <&tsc 2>;
1612                         sustainable-power = <6313>;
1613
1614                         trips {
1615                                 target: trip-point1 {
1616                                         temperature = <100000>;
1617                                         hysteresis = <1000>;
1618                                         type = "passive";
1619                                 };
1620
1621                                 sensor3_crit: sensor3-crit {
1622                                         temperature = <120000>;
1623                                         hysteresis = <1000>;
1624                                         type = "critical";
1625                                 };
1626                         };
1627
1628                         cooling-maps {
1629                                 map0 {
1630                                         trip = <&target>;
1631                                         cooling-device = <&a57_0 0 2>;
1632                                         contribution = <1024>;
1633                                 };
1634
1635                                 map1 {
1636                                         trip = <&target>;
1637                                         cooling-device = <&a53_0 0 2>;
1638                                         contribution = <1024>;
1639                                 };
1640                         };
1641                 };
1642         };
1643
1644         timer {
1645                 compatible = "arm,armv8-timer";
1646                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1647                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1648                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1649                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1650         };
1651
1652         /* External USB clocks - can be overridden by the board */
1653         usb3s0_clk: usb3s0 {
1654                 compatible = "fixed-clock";
1655                 #clock-cells = <0>;
1656                 clock-frequency = <0>;
1657         };
1658
1659         usb_extal_clk: usb_extal {
1660                 compatible = "fixed-clock";
1661                 #clock-cells = <0>;
1662                 clock-frequency = <0>;
1663         };
1664 };