arch/arm/dts/qcom-ipq4019.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2019 Sartura Ltd.
   4  *
   5  * Author: Robert Marko <robert.marko@sartura.hr>
   6  */
   7
   8  /dts-v1/;
   9
  10 #include "skeleton.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
  13 #include <dt-bindings/clock/qcom,ipq4019-gcc.h>
  14 #include <dt-bindings/reset/qcom,ipq4019-reset.h>
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         model = "Qualcomm Technologies, Inc. IPQ4019";
  21         compatible = "qcom,ipq4019";
  22
  23         aliases {
  24                 serial0 = &blsp1_uart1;
  25         };
  26
  27         reserved-memory {
  28                 #address-cells = <0x1>;
  29                 #size-cells = <0x1>;
  30                 ranges;
  31
  32                 smem_mem: smem_region: smem@87e00000 {
  33                         reg = <0x87e00000 0x080000>;
  34                         no-map;
  35                 };
  36
  37                 tz@87e80000 {
  38                         reg = <0x87e80000 0x180000>;
  39                         no-map;
  40                 };
  41         };
  42
  43         smem {
  44                 compatible = "qcom,smem";
  45                 memory-region = <&smem_mem>;
  46         };
  47
  48         soc: soc {
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 ranges;
  52                 compatible = "simple-bus";
  53
  54                 gcc: clock-controller@1800000 {
  55                         compatible = "qcom,gcc-ipq4019";
  56                         reg = <0x1800000 0x60000>;
  57                         #clock-cells = <1>;
  58                         #reset-cells = <1>;
  59                         u-boot,dm-pre-reloc;
  60                 };
  61
  62                 reset: gcc-reset@1800000 {
  63                         compatible = "qcom,gcc-reset-ipq4019";
  64                         reg = <0x1800000 0x60000>;
  65                         #clock-cells = <1>;
  66                         #reset-cells = <1>;
  67                         u-boot,dm-pre-reloc;
  68                 };
  69
  70                 pinctrl: qcom,tlmm@1000000 {
  71                         compatible = "qcom,tlmm-ipq4019";
  72                         reg = <0x1000000 0x300000>;
  73                         u-boot,dm-pre-reloc;
  74                 };
  75
  76                 blsp1_uart1: serial@78af000 {
  77                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  78                         reg = <0x78af000 0x200>;
  79                         clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
  80                         bit-rate = <0xFF>;
  81                         status = "disabled";
  82                         u-boot,dm-pre-reloc;
  83                 };
  84
  85                 soc_gpios: pinctrl@1000000 {
  86                         compatible = "qcom,ipq4019-pinctrl";
  87                         reg = <0x1000000 0x300000>;
  88                         gpio-controller;
  89                         gpio-count = <100>;
  90                         gpio-bank-name="soc";
  91                         #gpio-cells = <2>;
  92                 };
  93
  94                 usb3_ss_phy: ssphy@9a000 {
  95                         compatible = "qcom,usb-ss-ipq4019-phy";
  96                         #phy-cells = <0>;
  97                         reg = <0x9a000 0x800>;
  98                         reg-names = "phy_base";
  99                         resets = <&reset USB3_UNIPHY_PHY_ARES>;
 100                         reset-names = "por_rst";
 101                         status = "disabled";
 102                 };
 103
 104                 usb3_hs_phy: hsphy@a6000 {
 105                         compatible = "qcom,usb-hs-ipq4019-phy";
 106                         #phy-cells = <0>;
 107                         reg = <0xa6000 0x40>;
 108                         reg-names = "phy_base";
 109                         resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>;
 110                         reset-names = "por_rst", "srif_rst";
 111                         status = "disabled";
 112                 };
 113
 114                 usb3: usb3@8af8800 {
 115                         compatible = "qcom,dwc3";
 116                         reg = <0x8af8800 0x100>;
 117                         #address-cells = <1>;
 118                         #size-cells = <1>;
 119                         clocks = <&gcc GCC_USB3_MASTER_CLK>,
 120                                  <&gcc GCC_USB3_SLEEP_CLK>,
 121                                  <&gcc GCC_USB3_MOCK_UTMI_CLK>;
 122                         clock-names = "master", "sleep", "mock_utmi";
 123                         ranges;
 124                         status = "disabled";
 125
 126                         dwc3@8a00000 {
 127                                 compatible = "snps,dwc3";
 128                                 reg = <0x8a00000 0xf8000>;
 129                                 phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
 130                                 phy-names = "usb2-phy", "usb3-phy";
 131                                 dr_mode = "host";
 132                                 maximum-speed = "super-speed";
 133                                 snps,dis_u2_susphy_quirk;
 134                         };
 135                 };
 136
 137                 usb2_hs_phy: hsphy@a8000 {
 138                         compatible = "qcom,usb-hs-ipq4019-phy";
 139                         #phy-cells = <0>;
 140                         reg = <0xa8000 0x40>;
 141                         reg-names = "phy_base";
 142                         resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>;
 143                         reset-names = "por_rst", "srif_rst";
 144                         status = "disabled";
 145                 };
 146
 147                 usb2: usb2@60f8800 {
 148                         compatible = "qcom,dwc3";
 149                         reg = <0x60f8800 0x100>;
 150                         #address-cells = <1>;
 151                         #size-cells = <1>;
 152                         clocks = <&gcc GCC_USB2_MASTER_CLK>,
 153                                  <&gcc GCC_USB2_SLEEP_CLK>,
 154                                  <&gcc GCC_USB2_MOCK_UTMI_CLK>;
 155                         clock-names = "master", "sleep", "mock_utmi";
 156                         ranges;
 157                         status = "disabled";
 158
 159                         dwc3@6000000 {
 160                                 compatible = "snps,dwc3";
 161                                 reg = <0x6000000 0xf8000>;
 162                                 phys = <&usb2_hs_phy>;
 163                                 phy-names = "usb2-phy";
 164                                 dr_mode = "host";
 165                                 maximum-speed = "high-speed";
 166                                 snps,dis_u2_susphy_quirk;
 167                         };
 168                 };
 169         };
 170 };