1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2019 Sartura Ltd.
5 * Author: Robert Marko <robert.marko@sartura.hr>
10 #include "skeleton.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
13 #include <dt-bindings/clock/qcom,ipq4019-gcc.h>
14 #include <dt-bindings/reset/qcom,ipq4019-reset.h>
20 model = "Qualcomm Technologies, Inc. IPQ4019";
21 compatible = "qcom,ipq4019";
24 serial0 = &blsp1_uart1;
29 #address-cells = <0x1>;
33 smem_mem: smem_region: smem@87e00000 {
34 reg = <0x87e00000 0x080000>;
39 reg = <0x87e80000 0x180000>;
45 compatible = "qcom,smem";
46 memory-region = <&smem_mem>;
53 compatible = "simple-bus";
55 gcc: clock-controller@1800000 {
56 compatible = "qcom,gcc-ipq4019";
57 reg = <0x1800000 0x60000>;
64 compatible = "qcom,prng";
65 reg = <0x22000 0x140>;
66 clocks = <&gcc GCC_PRNG_AHB_CLK>;
70 reset: gcc-reset@1800000 {
71 compatible = "qcom,gcc-reset-ipq4019";
72 reg = <0x1800000 0x60000>;
78 pinctrl: qcom,tlmm@1000000 {
79 compatible = "qcom,tlmm-ipq4019";
80 reg = <0x1000000 0x300000>;
84 blsp1_uart1: serial@78af000 {
85 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
86 reg = <0x78af000 0x200>;
87 clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
93 soc_gpios: pinctrl@1000000 {
94 compatible = "qcom,ipq4019-pinctrl";
95 reg = <0x1000000 0x300000>;
103 blsp1_spi1: spi@78b5000 {
104 compatible = "qcom,spi-qup-v2.2.1";
105 reg = <0x78b5000 0x600>;
106 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
107 #address-cells = <1>;
114 #address-cells = <1>;
116 compatible = "qcom,ipq4019-mdio";
117 reg = <0x90000 0x64>;
120 ethphy0: ethernet-phy@0 {
124 ethphy1: ethernet-phy@1 {
128 ethphy2: ethernet-phy@2 {
132 ethphy3: ethernet-phy@3 {
136 ethphy4: ethernet-phy@4 {
141 usb3_ss_phy: ssphy@9a000 {
142 compatible = "qcom,usb-ss-ipq4019-phy";
144 reg = <0x9a000 0x800>;
145 reg-names = "phy_base";
146 resets = <&reset USB3_UNIPHY_PHY_ARES>;
147 reset-names = "por_rst";
151 usb3_hs_phy: hsphy@a6000 {
152 compatible = "qcom,usb-hs-ipq4019-phy";
154 reg = <0xa6000 0x40>;
155 reg-names = "phy_base";
156 resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>;
157 reset-names = "por_rst", "srif_rst";
162 compatible = "qcom,dwc3";
163 reg = <0x8af8800 0x100>;
164 #address-cells = <1>;
166 clocks = <&gcc GCC_USB3_MASTER_CLK>,
167 <&gcc GCC_USB3_SLEEP_CLK>,
168 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
169 clock-names = "master", "sleep", "mock_utmi";
174 compatible = "snps,dwc3";
175 reg = <0x8a00000 0xf8000>;
176 phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
177 phy-names = "usb2-phy", "usb3-phy";
179 maximum-speed = "super-speed";
180 snps,dis_u2_susphy_quirk;
184 usb2_hs_phy: hsphy@a8000 {
185 compatible = "qcom,usb-hs-ipq4019-phy";
187 reg = <0xa8000 0x40>;
188 reg-names = "phy_base";
189 resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>;
190 reset-names = "por_rst", "srif_rst";
195 compatible = "qcom,dwc3";
196 reg = <0x60f8800 0x100>;
197 #address-cells = <1>;
199 clocks = <&gcc GCC_USB2_MASTER_CLK>,
200 <&gcc GCC_USB2_SLEEP_CLK>,
201 <&gcc GCC_USB2_MOCK_UTMI_CLK>;
202 clock-names = "master", "sleep", "mock_utmi";
207 compatible = "snps,dwc3";
208 reg = <0x6000000 0xf8000>;
209 phys = <&usb2_hs_phy>;
210 phy-names = "usb2-phy";
212 maximum-speed = "high-speed";
213 snps,dis_u2_susphy_quirk;