1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 compatible = "rockchip,px30";
18 interrupt-parent = <&gic>;
44 compatible = "arm,cortex-a35";
46 enable-method = "psci";
47 clocks = <&cru ARMCLK>;
49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
50 dynamic-power-coefficient = <90>;
51 operating-points-v2 = <&cpu0_opp_table>;
56 compatible = "arm,cortex-a35";
58 enable-method = "psci";
59 clocks = <&cru ARMCLK>;
61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
62 dynamic-power-coefficient = <90>;
63 operating-points-v2 = <&cpu0_opp_table>;
68 compatible = "arm,cortex-a35";
70 enable-method = "psci";
71 clocks = <&cru ARMCLK>;
73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
74 dynamic-power-coefficient = <90>;
75 operating-points-v2 = <&cpu0_opp_table>;
80 compatible = "arm,cortex-a35";
82 enable-method = "psci";
83 clocks = <&cru ARMCLK>;
85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86 dynamic-power-coefficient = <90>;
87 operating-points-v2 = <&cpu0_opp_table>;
91 entry-method = "psci";
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
102 CLUSTER_SLEEP: cluster-sleep {
103 compatible = "arm,idle-state";
105 arm,psci-suspend-param = <0x1010000>;
106 entry-latency-us = <400>;
107 exit-latency-us = <500>;
108 min-residency-us = <2000>;
113 cpu0_opp_table: opp-table-0 {
114 compatible = "operating-points-v2";
118 opp-hz = /bits/ 64 <600000000>;
119 opp-microvolt = <950000 950000 1350000>;
120 clock-latency-ns = <40000>;
124 opp-hz = /bits/ 64 <816000000>;
125 opp-microvolt = <1050000 1050000 1350000>;
126 clock-latency-ns = <40000>;
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1175000 1175000 1350000>;
131 clock-latency-ns = <40000>;
134 opp-hz = /bits/ 64 <1200000000>;
135 opp-microvolt = <1300000 1300000 1350000>;
136 clock-latency-ns = <40000>;
139 opp-hz = /bits/ 64 <1296000000>;
140 opp-microvolt = <1350000 1350000 1350000>;
141 clock-latency-ns = <40000>;
146 compatible = "arm,cortex-a35-pmu";
147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
154 display_subsystem: display-subsystem {
155 compatible = "rockchip,display-subsystem";
156 ports = <&vopb_out>, <&vopl_out>;
160 gmac_clkin: external-gmac-clock {
161 compatible = "fixed-clock";
162 clock-frequency = <50000000>;
163 clock-output-names = "gmac_clkin";
168 compatible = "arm,psci-1.0";
173 compatible = "arm,armv8-timer";
174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
180 thermal_zones: thermal-zones {
181 soc_thermal: soc-thermal {
182 polling-delay-passive = <20>;
183 polling-delay = <1000>;
184 sustainable-power = <750>;
185 thermal-sensors = <&tsadc 0>;
188 threshold: trip-point-0 {
189 temperature = <70000>;
194 target: trip-point-1 {
195 temperature = <85000>;
201 temperature = <115000>;
210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
211 contribution = <4096>;
216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
217 contribution = <4096>;
222 gpu_thermal: gpu-thermal {
223 polling-delay-passive = <100>; /* milliseconds */
224 polling-delay = <1000>; /* milliseconds */
225 thermal-sensors = <&tsadc 1>;
230 compatible = "fixed-clock";
232 clock-frequency = <24000000>;
233 clock-output-names = "xin24m";
236 pmu: power-management@ff000000 {
237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
238 reg = <0x0 0xff000000 0x0 0x1000>;
240 power: power-controller {
241 compatible = "rockchip,px30-power-controller";
242 #power-domain-cells = <1>;
243 #address-cells = <1>;
246 /* These power domains are grouped by VD_LOGIC */
247 power-domain@PX30_PD_USB {
249 clocks = <&cru HCLK_HOST>,
252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
253 #power-domain-cells = <0>;
255 power-domain@PX30_PD_SDCARD {
256 reg = <PX30_PD_SDCARD>;
257 clocks = <&cru HCLK_SDMMC>,
259 pm_qos = <&qos_sdmmc>;
260 #power-domain-cells = <0>;
262 power-domain@PX30_PD_GMAC {
263 reg = <PX30_PD_GMAC>;
264 clocks = <&cru ACLK_GMAC>,
267 <&cru SCLK_GMAC_RX_TX>;
268 pm_qos = <&qos_gmac>;
269 #power-domain-cells = <0>;
271 power-domain@PX30_PD_MMC_NAND {
272 reg = <PX30_PD_MMC_NAND>;
273 clocks = <&cru HCLK_NANDC>,
281 pm_qos = <&qos_emmc>, <&qos_nand>,
282 <&qos_sdio>, <&qos_sfc>;
283 #power-domain-cells = <0>;
285 power-domain@PX30_PD_VPU {
287 clocks = <&cru ACLK_VPU>,
289 <&cru SCLK_CORE_VPU>;
290 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
291 #power-domain-cells = <0>;
293 power-domain@PX30_PD_VO {
295 clocks = <&cru ACLK_RGA>,
303 <&cru PCLK_MIPI_DSI>,
304 <&cru SCLK_RGA_CORE>,
305 <&cru SCLK_VOPB_PWM>;
306 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
307 <&qos_vop_m0>, <&qos_vop_m1>;
308 #power-domain-cells = <0>;
310 power-domain@PX30_PD_VI {
312 clocks = <&cru ACLK_CIF>,
317 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
318 <&qos_isp_wr>, <&qos_isp_m1>,
320 #power-domain-cells = <0>;
322 power-domain@PX30_PD_GPU {
324 clocks = <&cru SCLK_GPU>;
326 #power-domain-cells = <0>;
331 pmugrf: syscon@ff010000 {
332 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
333 reg = <0x0 0xff010000 0x0 0x1000>;
334 #address-cells = <1>;
337 pmu_io_domains: io-domains {
338 compatible = "rockchip,px30-pmu-io-voltage-domain";
343 compatible = "syscon-reboot-mode";
345 mode-bootloader = <BOOT_BL_DOWNLOAD>;
346 mode-fastboot = <BOOT_FASTBOOT>;
347 mode-loader = <BOOT_BL_DOWNLOAD>;
348 mode-normal = <BOOT_NORMAL>;
349 mode-recovery = <BOOT_RECOVERY>;
353 uart0: serial@ff030000 {
354 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
355 reg = <0x0 0xff030000 0x0 0x100>;
356 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
358 clock-names = "baudclk", "apb_pclk";
359 dmas = <&dmac 0>, <&dmac 1>;
360 dma-names = "tx", "rx";
363 pinctrl-names = "default";
364 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
368 i2s1_2ch: i2s@ff070000 {
369 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
370 reg = <0x0 0xff070000 0x0 0x1000>;
371 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
373 clock-names = "i2s_clk", "i2s_hclk";
374 dmas = <&dmac 18>, <&dmac 19>;
375 dma-names = "tx", "rx";
376 pinctrl-names = "default";
377 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
378 &i2s1_2ch_sdi &i2s1_2ch_sdo>;
379 #sound-dai-cells = <0>;
383 i2s2_2ch: i2s@ff080000 {
384 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
385 reg = <0x0 0xff080000 0x0 0x1000>;
386 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
388 clock-names = "i2s_clk", "i2s_hclk";
389 dmas = <&dmac 20>, <&dmac 21>;
390 dma-names = "tx", "rx";
391 pinctrl-names = "default";
392 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
393 &i2s2_2ch_sdi &i2s2_2ch_sdo>;
394 #sound-dai-cells = <0>;
398 gic: interrupt-controller@ff131000 {
399 compatible = "arm,gic-400";
400 #interrupt-cells = <3>;
401 #address-cells = <0>;
402 interrupt-controller;
403 reg = <0x0 0xff131000 0 0x1000>,
404 <0x0 0xff132000 0 0x2000>,
405 <0x0 0xff134000 0 0x2000>,
406 <0x0 0xff136000 0 0x2000>;
407 interrupts = <GIC_PPI 9
408 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
411 grf: syscon@ff140000 {
412 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
413 reg = <0x0 0xff140000 0x0 0x1000>;
414 #address-cells = <1>;
417 io_domains: io-domains {
418 compatible = "rockchip,px30-io-voltage-domain";
423 compatible = "rockchip,px30-lvds";
426 rockchip,grf = <&grf>;
427 rockchip,output = "lvds";
431 #address-cells = <1>;
436 #address-cells = <1>;
439 lvds_vopb_in: endpoint@0 {
441 remote-endpoint = <&vopb_out_lvds>;
444 lvds_vopl_in: endpoint@1 {
446 remote-endpoint = <&vopl_out_lvds>;
453 uart1: serial@ff158000 {
454 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
455 reg = <0x0 0xff158000 0x0 0x100>;
456 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
458 clock-names = "baudclk", "apb_pclk";
459 dmas = <&dmac 2>, <&dmac 3>;
460 dma-names = "tx", "rx";
463 pinctrl-names = "default";
464 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
468 uart2: serial@ff160000 {
469 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
470 reg = <0x0 0xff160000 0x0 0x100>;
471 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
473 clock-names = "baudclk", "apb_pclk";
474 dmas = <&dmac 4>, <&dmac 5>;
475 dma-names = "tx", "rx";
478 pinctrl-names = "default";
479 pinctrl-0 = <&uart2m0_xfer>;
483 uart3: serial@ff168000 {
484 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
485 reg = <0x0 0xff168000 0x0 0x100>;
486 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
488 clock-names = "baudclk", "apb_pclk";
489 dmas = <&dmac 6>, <&dmac 7>;
490 dma-names = "tx", "rx";
493 pinctrl-names = "default";
494 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
498 uart4: serial@ff170000 {
499 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
500 reg = <0x0 0xff170000 0x0 0x100>;
501 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
503 clock-names = "baudclk", "apb_pclk";
504 dmas = <&dmac 8>, <&dmac 9>;
505 dma-names = "tx", "rx";
508 pinctrl-names = "default";
509 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
513 uart5: serial@ff178000 {
514 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
515 reg = <0x0 0xff178000 0x0 0x100>;
516 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
518 clock-names = "baudclk", "apb_pclk";
519 dmas = <&dmac 10>, <&dmac 11>;
520 dma-names = "tx", "rx";
523 pinctrl-names = "default";
524 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
529 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
530 reg = <0x0 0xff180000 0x0 0x1000>;
531 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
532 clock-names = "i2c", "pclk";
533 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
534 pinctrl-names = "default";
535 pinctrl-0 = <&i2c0_xfer>;
536 #address-cells = <1>;
542 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
543 reg = <0x0 0xff190000 0x0 0x1000>;
544 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
545 clock-names = "i2c", "pclk";
546 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&i2c1_xfer>;
549 #address-cells = <1>;
555 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
556 reg = <0x0 0xff1a0000 0x0 0x1000>;
557 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
558 clock-names = "i2c", "pclk";
559 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&i2c2_xfer>;
562 #address-cells = <1>;
568 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
569 reg = <0x0 0xff1b0000 0x0 0x1000>;
570 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
571 clock-names = "i2c", "pclk";
572 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
573 pinctrl-names = "default";
574 pinctrl-0 = <&i2c3_xfer>;
575 #address-cells = <1>;
581 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
582 reg = <0x0 0xff1d0000 0x0 0x1000>;
583 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
585 clock-names = "spiclk", "apb_pclk";
586 dmas = <&dmac 12>, <&dmac 13>;
587 dma-names = "tx", "rx";
588 pinctrl-names = "default";
589 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
590 #address-cells = <1>;
596 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
597 reg = <0x0 0xff1d8000 0x0 0x1000>;
598 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
600 clock-names = "spiclk", "apb_pclk";
601 dmas = <&dmac 14>, <&dmac 15>;
602 dma-names = "tx", "rx";
603 pinctrl-names = "default";
604 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
605 #address-cells = <1>;
610 wdt: watchdog@ff1e0000 {
611 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
612 reg = <0x0 0xff1e0000 0x0 0x100>;
613 clocks = <&cru PCLK_WDT_NS>;
614 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
619 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
620 reg = <0x0 0xff200000 0x0 0x10>;
621 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
622 clock-names = "pwm", "pclk";
623 pinctrl-names = "default";
624 pinctrl-0 = <&pwm0_pin>;
630 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
631 reg = <0x0 0xff200010 0x0 0x10>;
632 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
633 clock-names = "pwm", "pclk";
634 pinctrl-names = "default";
635 pinctrl-0 = <&pwm1_pin>;
641 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
642 reg = <0x0 0xff200020 0x0 0x10>;
643 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
644 clock-names = "pwm", "pclk";
645 pinctrl-names = "default";
646 pinctrl-0 = <&pwm2_pin>;
652 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
653 reg = <0x0 0xff200030 0x0 0x10>;
654 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
655 clock-names = "pwm", "pclk";
656 pinctrl-names = "default";
657 pinctrl-0 = <&pwm3_pin>;
663 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
664 reg = <0x0 0xff208000 0x0 0x10>;
665 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
666 clock-names = "pwm", "pclk";
667 pinctrl-names = "default";
668 pinctrl-0 = <&pwm4_pin>;
674 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
675 reg = <0x0 0xff208010 0x0 0x10>;
676 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
677 clock-names = "pwm", "pclk";
678 pinctrl-names = "default";
679 pinctrl-0 = <&pwm5_pin>;
685 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
686 reg = <0x0 0xff208020 0x0 0x10>;
687 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
688 clock-names = "pwm", "pclk";
689 pinctrl-names = "default";
690 pinctrl-0 = <&pwm6_pin>;
696 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
697 reg = <0x0 0xff208030 0x0 0x10>;
698 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
699 clock-names = "pwm", "pclk";
700 pinctrl-names = "default";
701 pinctrl-0 = <&pwm7_pin>;
706 rktimer: timer@ff210000 {
707 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
708 reg = <0x0 0xff210000 0x0 0x1000>;
709 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
711 clock-names = "pclk", "timer";
714 dmac: dmac@ff240000 {
715 compatible = "arm,pl330", "arm,primecell";
716 reg = <0x0 0xff240000 0x0 0x4000>;
717 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
719 arm,pl330-periph-burst;
720 clocks = <&cru ACLK_DMAC>;
721 clock-names = "apb_pclk";
725 tsadc: tsadc@ff280000 {
726 compatible = "rockchip,px30-tsadc";
727 reg = <0x0 0xff280000 0x0 0x100>;
728 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
729 assigned-clocks = <&cru SCLK_TSADC>;
730 assigned-clock-rates = <50000>;
731 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
732 clock-names = "tsadc", "apb_pclk";
733 resets = <&cru SRST_TSADC>;
734 reset-names = "tsadc-apb";
735 rockchip,grf = <&grf>;
736 rockchip,hw-tshut-temp = <120000>;
737 pinctrl-names = "init", "default", "sleep";
738 pinctrl-0 = <&tsadc_otp_pin>;
739 pinctrl-1 = <&tsadc_otp_out>;
740 pinctrl-2 = <&tsadc_otp_pin>;
741 #thermal-sensor-cells = <1>;
745 saradc: saradc@ff288000 {
746 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
747 reg = <0x0 0xff288000 0x0 0x100>;
748 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
749 #io-channel-cells = <1>;
750 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
751 clock-names = "saradc", "apb_pclk";
752 resets = <&cru SRST_SARADC_P>;
753 reset-names = "saradc-apb";
757 otp: nvmem@ff290000 {
758 compatible = "rockchip,px30-otp";
759 reg = <0x0 0xff290000 0x0 0x4000>;
760 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
762 clock-names = "otp", "apb_pclk", "phy";
763 resets = <&cru SRST_OTP_PHY>;
765 #address-cells = <1>;
772 cpu_leakage: cpu-leakage@17 {
775 performance: performance@1e {
781 cru: clock-controller@ff2b0000 {
782 compatible = "rockchip,px30-cru";
783 reg = <0x0 0xff2b0000 0x0 0x1000>;
784 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
785 clock-names = "xin24m", "gpll";
786 rockchip,grf = <&grf>;
790 assigned-clocks = <&cru PLL_NPLL>,
791 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
792 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
793 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
795 assigned-clock-rates = <1188000000>,
796 <200000000>, <200000000>,
797 <150000000>, <150000000>,
798 <100000000>, <200000000>;
801 pmucru: clock-controller@ff2bc000 {
802 compatible = "rockchip,px30-pmucru";
803 reg = <0x0 0xff2bc000 0x0 0x1000>;
805 clock-names = "xin24m";
806 rockchip,grf = <&grf>;
811 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
812 <&pmucru SCLK_WIFI_PMU>;
813 assigned-clock-rates =
814 <1200000000>, <100000000>,
818 usb2phy_grf: syscon@ff2c0000 {
819 compatible = "rockchip,px30-usb2phy-grf", "syscon",
821 reg = <0x0 0xff2c0000 0x0 0x10000>;
822 #address-cells = <1>;
826 compatible = "rockchip,px30-usb2phy";
828 clocks = <&pmucru SCLK_USBPHY_REF>;
829 clock-names = "phyclk";
831 assigned-clocks = <&cru USB480M>;
832 assigned-clock-parents = <&u2phy>;
833 clock-output-names = "usb480m_phy";
836 u2phy_host: host-port {
838 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
839 interrupt-names = "linestate";
843 u2phy_otg: otg-port {
845 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
846 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
848 interrupt-names = "otg-bvalid", "otg-id",
855 dsi_dphy: phy@ff2e0000 {
856 compatible = "rockchip,px30-dsi-dphy";
857 reg = <0x0 0xff2e0000 0x0 0x10000>;
858 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
859 clock-names = "ref", "pclk";
860 resets = <&cru SRST_MIPIDSIPHY_P>;
863 power-domains = <&power PX30_PD_VO>;
867 csi_dphy: phy@ff2f0000 {
868 compatible = "rockchip,px30-csi-dphy";
869 reg = <0x0 0xff2f0000 0x0 0x4000>;
870 clocks = <&cru PCLK_MIPICSIPHY>;
871 clock-names = "pclk";
873 power-domains = <&power PX30_PD_VI>;
874 resets = <&cru SRST_MIPICSIPHY_P>;
876 rockchip,grf = <&grf>;
880 usb20_otg: usb@ff300000 {
881 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
883 reg = <0x0 0xff300000 0x0 0x40000>;
884 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&cru HCLK_OTG>;
888 g-np-tx-fifo-size = <16>;
889 g-rx-fifo-size = <280>;
890 g-tx-fifo-size = <256 128 128 64 32 16>;
892 phy-names = "usb2-phy";
893 power-domains = <&power PX30_PD_USB>;
897 usb_host0_ehci: usb@ff340000 {
898 compatible = "generic-ehci";
899 reg = <0x0 0xff340000 0x0 0x10000>;
900 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
901 clocks = <&cru HCLK_HOST>;
902 phys = <&u2phy_host>;
904 power-domains = <&power PX30_PD_USB>;
908 usb_host0_ohci: usb@ff350000 {
909 compatible = "generic-ohci";
910 reg = <0x0 0xff350000 0x0 0x10000>;
911 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&cru HCLK_HOST>;
913 phys = <&u2phy_host>;
915 power-domains = <&power PX30_PD_USB>;
919 gmac: ethernet@ff360000 {
920 compatible = "rockchip,px30-gmac";
921 reg = <0x0 0xff360000 0x0 0x10000>;
922 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
923 interrupt-names = "macirq";
924 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
925 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
926 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
927 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
928 clock-names = "stmmaceth", "mac_clk_rx",
929 "mac_clk_tx", "clk_mac_ref",
930 "clk_mac_refout", "aclk_mac",
931 "pclk_mac", "clk_mac_speed";
932 rockchip,grf = <&grf>;
934 pinctrl-names = "default";
935 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
936 power-domains = <&power PX30_PD_GMAC>;
937 resets = <&cru SRST_GMAC_A>;
938 reset-names = "stmmaceth";
942 sdmmc: mmc@ff370000 {
943 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
944 reg = <0x0 0xff370000 0x0 0x4000>;
945 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
947 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
948 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
950 fifo-depth = <0x100>;
951 max-frequency = <150000000>;
952 pinctrl-names = "default";
953 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
954 power-domains = <&power PX30_PD_SDCARD>;
959 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
960 reg = <0x0 0xff380000 0x0 0x4000>;
961 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
963 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
964 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
966 fifo-depth = <0x100>;
967 max-frequency = <150000000>;
968 pinctrl-names = "default";
969 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
970 power-domains = <&power PX30_PD_MMC_NAND>;
975 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
976 reg = <0x0 0xff390000 0x0 0x4000>;
977 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
979 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
980 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
982 fifo-depth = <0x100>;
983 max-frequency = <150000000>;
984 pinctrl-names = "default";
985 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
986 power-domains = <&power PX30_PD_MMC_NAND>;
991 compatible = "rockchip,sfc";
992 reg = <0x0 0xff3a0000 0x0 0x4000>;
993 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
995 clock-names = "clk_sfc", "hclk_sfc";
996 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
997 pinctrl-names = "default";
998 power-domains = <&power PX30_PD_MMC_NAND>;
1002 nfc: nand-controller@ff3b0000 {
1003 compatible = "rockchip,px30-nfc";
1004 reg = <0x0 0xff3b0000 0x0 0x4000>;
1005 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
1007 clock-names = "ahb", "nfc";
1008 assigned-clocks = <&cru SCLK_NANDC>;
1009 assigned-clock-rates = <150000000>;
1010 pinctrl-names = "default";
1011 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1012 &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
1013 power-domains = <&power PX30_PD_MMC_NAND>;
1014 status = "disabled";
1017 gpu_opp_table: opp-table-1 {
1018 compatible = "operating-points-v2";
1021 opp-hz = /bits/ 64 <200000000>;
1022 opp-microvolt = <950000>;
1025 opp-hz = /bits/ 64 <300000000>;
1026 opp-microvolt = <975000>;
1029 opp-hz = /bits/ 64 <400000000>;
1030 opp-microvolt = <1050000>;
1033 opp-hz = /bits/ 64 <480000000>;
1034 opp-microvolt = <1125000>;
1039 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1040 reg = <0x0 0xff400000 0x0 0x4000>;
1041 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1042 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1043 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1044 interrupt-names = "job", "mmu", "gpu";
1045 clocks = <&cru SCLK_GPU>;
1046 #cooling-cells = <2>;
1047 power-domains = <&power PX30_PD_GPU>;
1048 operating-points-v2 = <&gpu_opp_table>;
1049 status = "disabled";
1052 vpu: video-codec@ff442000 {
1053 compatible = "rockchip,px30-vpu";
1054 reg = <0x0 0xff442000 0x0 0x800>;
1055 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1057 interrupt-names = "vepu", "vdpu";
1058 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1059 clock-names = "aclk", "hclk";
1060 iommus = <&vpu_mmu>;
1061 power-domains = <&power PX30_PD_VPU>;
1064 vpu_mmu: iommu@ff442800 {
1065 compatible = "rockchip,iommu";
1066 reg = <0x0 0xff442800 0x0 0x100>;
1067 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1069 clock-names = "aclk", "iface";
1071 power-domains = <&power PX30_PD_VPU>;
1075 compatible = "rockchip,px30-mipi-dsi";
1076 reg = <0x0 0xff450000 0x0 0x10000>;
1077 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&cru PCLK_MIPI_DSI>;
1079 clock-names = "pclk";
1082 power-domains = <&power PX30_PD_VO>;
1083 resets = <&cru SRST_MIPIDSI_HOST_P>;
1084 reset-names = "apb";
1085 rockchip,grf = <&grf>;
1086 #address-cells = <1>;
1088 status = "disabled";
1091 #address-cells = <1>;
1096 #address-cells = <1>;
1099 dsi_in_vopb: endpoint@0 {
1101 remote-endpoint = <&vopb_out_dsi>;
1104 dsi_in_vopl: endpoint@1 {
1106 remote-endpoint = <&vopl_out_dsi>;
1112 vopb: vop@ff460000 {
1113 compatible = "rockchip,px30-vop-big";
1114 reg = <0x0 0xff460000 0x0 0xefc>;
1115 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1116 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1118 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1119 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1120 reset-names = "axi", "ahb", "dclk";
1121 iommus = <&vopb_mmu>;
1122 power-domains = <&power PX30_PD_VO>;
1123 status = "disabled";
1126 #address-cells = <1>;
1129 vopb_out_dsi: endpoint@0 {
1131 remote-endpoint = <&dsi_in_vopb>;
1134 vopb_out_lvds: endpoint@1 {
1136 remote-endpoint = <&lvds_vopb_in>;
1141 vopb_mmu: iommu@ff460f00 {
1142 compatible = "rockchip,iommu";
1143 reg = <0x0 0xff460f00 0x0 0x100>;
1144 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1146 clock-names = "aclk", "iface";
1147 power-domains = <&power PX30_PD_VO>;
1149 status = "disabled";
1152 vopl: vop@ff470000 {
1153 compatible = "rockchip,px30-vop-lit";
1154 reg = <0x0 0xff470000 0x0 0xefc>;
1155 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1156 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1158 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1159 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1160 reset-names = "axi", "ahb", "dclk";
1161 iommus = <&vopl_mmu>;
1162 power-domains = <&power PX30_PD_VO>;
1163 status = "disabled";
1166 #address-cells = <1>;
1169 vopl_out_dsi: endpoint@0 {
1171 remote-endpoint = <&dsi_in_vopl>;
1174 vopl_out_lvds: endpoint@1 {
1176 remote-endpoint = <&lvds_vopl_in>;
1181 vopl_mmu: iommu@ff470f00 {
1182 compatible = "rockchip,iommu";
1183 reg = <0x0 0xff470f00 0x0 0x100>;
1184 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1185 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1186 clock-names = "aclk", "iface";
1187 power-domains = <&power PX30_PD_VO>;
1189 status = "disabled";
1193 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
1194 reg = <0x0 0xff4a0000 0x0 0x8000>;
1195 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1196 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1197 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1198 interrupt-names = "isp", "mi", "mipi";
1199 clocks = <&cru SCLK_ISP>,
1203 clock-names = "isp", "aclk", "hclk", "pclk";
1204 iommus = <&isp_mmu>;
1207 power-domains = <&power PX30_PD_VI>;
1208 status = "disabled";
1211 #address-cells = <1>;
1216 #address-cells = <1>;
1222 isp_mmu: iommu@ff4a8000 {
1223 compatible = "rockchip,iommu";
1224 reg = <0x0 0xff4a8000 0x0 0x100>;
1225 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1227 clock-names = "aclk", "iface";
1228 power-domains = <&power PX30_PD_VI>;
1229 rockchip,disable-mmu-reset;
1233 qos_gmac: qos@ff518000 {
1234 compatible = "rockchip,px30-qos", "syscon";
1235 reg = <0x0 0xff518000 0x0 0x20>;
1238 qos_gpu: qos@ff520000 {
1239 compatible = "rockchip,px30-qos", "syscon";
1240 reg = <0x0 0xff520000 0x0 0x20>;
1243 qos_sdmmc: qos@ff52c000 {
1244 compatible = "rockchip,px30-qos", "syscon";
1245 reg = <0x0 0xff52c000 0x0 0x20>;
1248 qos_emmc: qos@ff538000 {
1249 compatible = "rockchip,px30-qos", "syscon";
1250 reg = <0x0 0xff538000 0x0 0x20>;
1253 qos_nand: qos@ff538080 {
1254 compatible = "rockchip,px30-qos", "syscon";
1255 reg = <0x0 0xff538080 0x0 0x20>;
1258 qos_sdio: qos@ff538100 {
1259 compatible = "rockchip,px30-qos", "syscon";
1260 reg = <0x0 0xff538100 0x0 0x20>;
1263 qos_sfc: qos@ff538180 {
1264 compatible = "rockchip,px30-qos", "syscon";
1265 reg = <0x0 0xff538180 0x0 0x20>;
1268 qos_usb_host: qos@ff540000 {
1269 compatible = "rockchip,px30-qos", "syscon";
1270 reg = <0x0 0xff540000 0x0 0x20>;
1273 qos_usb_otg: qos@ff540080 {
1274 compatible = "rockchip,px30-qos", "syscon";
1275 reg = <0x0 0xff540080 0x0 0x20>;
1278 qos_isp_128: qos@ff548000 {
1279 compatible = "rockchip,px30-qos", "syscon";
1280 reg = <0x0 0xff548000 0x0 0x20>;
1283 qos_isp_rd: qos@ff548080 {
1284 compatible = "rockchip,px30-qos", "syscon";
1285 reg = <0x0 0xff548080 0x0 0x20>;
1288 qos_isp_wr: qos@ff548100 {
1289 compatible = "rockchip,px30-qos", "syscon";
1290 reg = <0x0 0xff548100 0x0 0x20>;
1293 qos_isp_m1: qos@ff548180 {
1294 compatible = "rockchip,px30-qos", "syscon";
1295 reg = <0x0 0xff548180 0x0 0x20>;
1298 qos_vip: qos@ff548200 {
1299 compatible = "rockchip,px30-qos", "syscon";
1300 reg = <0x0 0xff548200 0x0 0x20>;
1303 qos_rga_rd: qos@ff550000 {
1304 compatible = "rockchip,px30-qos", "syscon";
1305 reg = <0x0 0xff550000 0x0 0x20>;
1308 qos_rga_wr: qos@ff550080 {
1309 compatible = "rockchip,px30-qos", "syscon";
1310 reg = <0x0 0xff550080 0x0 0x20>;
1313 qos_vop_m0: qos@ff550100 {
1314 compatible = "rockchip,px30-qos", "syscon";
1315 reg = <0x0 0xff550100 0x0 0x20>;
1318 qos_vop_m1: qos@ff550180 {
1319 compatible = "rockchip,px30-qos", "syscon";
1320 reg = <0x0 0xff550180 0x0 0x20>;
1323 qos_vpu: qos@ff558000 {
1324 compatible = "rockchip,px30-qos", "syscon";
1325 reg = <0x0 0xff558000 0x0 0x20>;
1328 qos_vpu_r128: qos@ff558080 {
1329 compatible = "rockchip,px30-qos", "syscon";
1330 reg = <0x0 0xff558080 0x0 0x20>;
1334 compatible = "rockchip,px30-pinctrl";
1335 rockchip,grf = <&grf>;
1336 rockchip,pmu = <&pmugrf>;
1337 #address-cells = <2>;
1341 gpio0: gpio@ff040000 {
1342 compatible = "rockchip,gpio-bank";
1343 reg = <0x0 0xff040000 0x0 0x100>;
1344 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&pmucru PCLK_GPIO0_PMU>;
1349 interrupt-controller;
1350 #interrupt-cells = <2>;
1353 gpio1: gpio@ff250000 {
1354 compatible = "rockchip,gpio-bank";
1355 reg = <0x0 0xff250000 0x0 0x100>;
1356 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1357 clocks = <&cru PCLK_GPIO1>;
1361 interrupt-controller;
1362 #interrupt-cells = <2>;
1365 gpio2: gpio@ff260000 {
1366 compatible = "rockchip,gpio-bank";
1367 reg = <0x0 0xff260000 0x0 0x100>;
1368 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1369 clocks = <&cru PCLK_GPIO2>;
1373 interrupt-controller;
1374 #interrupt-cells = <2>;
1377 gpio3: gpio@ff270000 {
1378 compatible = "rockchip,gpio-bank";
1379 reg = <0x0 0xff270000 0x0 0x100>;
1380 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1381 clocks = <&cru PCLK_GPIO3>;
1385 interrupt-controller;
1386 #interrupt-cells = <2>;
1389 pcfg_pull_up: pcfg-pull-up {
1393 pcfg_pull_down: pcfg-pull-down {
1397 pcfg_pull_none: pcfg-pull-none {
1401 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1403 drive-strength = <2>;
1406 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1408 drive-strength = <2>;
1411 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1413 drive-strength = <4>;
1416 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1418 drive-strength = <4>;
1421 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1423 drive-strength = <4>;
1426 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1428 drive-strength = <8>;
1431 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1433 drive-strength = <8>;
1436 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1438 drive-strength = <12>;
1441 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1443 drive-strength = <12>;
1446 pcfg_pull_none_smt: pcfg-pull-none-smt {
1448 input-schmitt-enable;
1451 pcfg_output_high: pcfg-output-high {
1455 pcfg_output_low: pcfg-output-low {
1459 pcfg_input_high: pcfg-input-high {
1464 pcfg_input: pcfg-input {
1469 i2c0_xfer: i2c0-xfer {
1471 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1472 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1477 i2c1_xfer: i2c1-xfer {
1479 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1480 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1485 i2c2_xfer: i2c2-xfer {
1487 <2 RK_PB7 2 &pcfg_pull_none_smt>,
1488 <2 RK_PC0 2 &pcfg_pull_none_smt>;
1493 i2c3_xfer: i2c3-xfer {
1495 <1 RK_PB4 4 &pcfg_pull_none_smt>,
1496 <1 RK_PB5 4 &pcfg_pull_none_smt>;
1501 tsadc_otp_pin: tsadc-otp-pin {
1503 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1506 tsadc_otp_out: tsadc-otp-out {
1508 <0 RK_PA6 1 &pcfg_pull_none>;
1513 uart0_xfer: uart0-xfer {
1515 <0 RK_PB2 1 &pcfg_pull_up>,
1516 <0 RK_PB3 1 &pcfg_pull_up>;
1519 uart0_cts: uart0-cts {
1521 <0 RK_PB4 1 &pcfg_pull_none>;
1524 uart0_rts: uart0-rts {
1526 <0 RK_PB5 1 &pcfg_pull_none>;
1531 uart1_xfer: uart1-xfer {
1533 <1 RK_PC1 1 &pcfg_pull_up>,
1534 <1 RK_PC0 1 &pcfg_pull_up>;
1537 uart1_cts: uart1-cts {
1539 <1 RK_PC2 1 &pcfg_pull_none>;
1542 uart1_rts: uart1-rts {
1544 <1 RK_PC3 1 &pcfg_pull_none>;
1549 uart2m0_xfer: uart2m0-xfer {
1551 <1 RK_PD2 2 &pcfg_pull_up>,
1552 <1 RK_PD3 2 &pcfg_pull_up>;
1557 uart2m1_xfer: uart2m1-xfer {
1559 <2 RK_PB4 2 &pcfg_pull_up>,
1560 <2 RK_PB6 2 &pcfg_pull_up>;
1565 uart3m0_xfer: uart3m0-xfer {
1567 <0 RK_PC0 2 &pcfg_pull_up>,
1568 <0 RK_PC1 2 &pcfg_pull_up>;
1571 uart3m0_cts: uart3m0-cts {
1573 <0 RK_PC2 2 &pcfg_pull_none>;
1576 uart3m0_rts: uart3m0-rts {
1578 <0 RK_PC3 2 &pcfg_pull_none>;
1583 uart3m1_xfer: uart3m1-xfer {
1585 <1 RK_PB6 2 &pcfg_pull_up>,
1586 <1 RK_PB7 2 &pcfg_pull_up>;
1589 uart3m1_cts: uart3m1-cts {
1591 <1 RK_PB4 2 &pcfg_pull_none>;
1594 uart3m1_rts: uart3m1-rts {
1596 <1 RK_PB5 2 &pcfg_pull_none>;
1601 uart4_xfer: uart4-xfer {
1603 <1 RK_PD4 2 &pcfg_pull_up>,
1604 <1 RK_PD5 2 &pcfg_pull_up>;
1607 uart4_cts: uart4-cts {
1609 <1 RK_PD6 2 &pcfg_pull_none>;
1612 uart4_rts: uart4-rts {
1614 <1 RK_PD7 2 &pcfg_pull_none>;
1619 uart5_xfer: uart5-xfer {
1621 <3 RK_PA2 4 &pcfg_pull_up>,
1622 <3 RK_PA1 4 &pcfg_pull_up>;
1625 uart5_cts: uart5-cts {
1627 <3 RK_PA3 4 &pcfg_pull_none>;
1630 uart5_rts: uart5-rts {
1632 <3 RK_PA5 4 &pcfg_pull_none>;
1637 spi0_clk: spi0-clk {
1639 <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1642 spi0_csn: spi0-csn {
1644 <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1647 spi0_miso: spi0-miso {
1649 <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1652 spi0_mosi: spi0-mosi {
1654 <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1657 spi0_clk_hs: spi0-clk-hs {
1659 <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1662 spi0_miso_hs: spi0-miso-hs {
1664 <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1667 spi0_mosi_hs: spi0-mosi-hs {
1669 <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1674 spi1_clk: spi1-clk {
1676 <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1679 spi1_csn0: spi1-csn0 {
1681 <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1684 spi1_csn1: spi1-csn1 {
1686 <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1689 spi1_miso: spi1-miso {
1691 <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1694 spi1_mosi: spi1-mosi {
1696 <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1699 spi1_clk_hs: spi1-clk-hs {
1701 <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1704 spi1_miso_hs: spi1-miso-hs {
1706 <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1709 spi1_mosi_hs: spi1-mosi-hs {
1711 <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1716 pdm_clk0m0: pdm-clk0m0 {
1718 <3 RK_PC6 2 &pcfg_pull_none>;
1721 pdm_clk0m1: pdm-clk0m1 {
1723 <2 RK_PC6 1 &pcfg_pull_none>;
1726 pdm_clk1: pdm-clk1 {
1728 <3 RK_PC7 2 &pcfg_pull_none>;
1731 pdm_sdi0m0: pdm-sdi0m0 {
1733 <3 RK_PD3 2 &pcfg_pull_none>;
1736 pdm_sdi0m1: pdm-sdi0m1 {
1738 <2 RK_PC5 2 &pcfg_pull_none>;
1741 pdm_sdi1: pdm-sdi1 {
1743 <3 RK_PD0 2 &pcfg_pull_none>;
1746 pdm_sdi2: pdm-sdi2 {
1748 <3 RK_PD1 2 &pcfg_pull_none>;
1751 pdm_sdi3: pdm-sdi3 {
1753 <3 RK_PD2 2 &pcfg_pull_none>;
1756 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1758 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1761 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1763 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1766 pdm_clk1_sleep: pdm-clk1-sleep {
1768 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1771 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1773 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1776 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1778 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1781 pdm_sdi1_sleep: pdm-sdi1-sleep {
1783 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1786 pdm_sdi2_sleep: pdm-sdi2-sleep {
1788 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1791 pdm_sdi3_sleep: pdm-sdi3-sleep {
1793 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1798 i2s0_8ch_mclk: i2s0-8ch-mclk {
1800 <3 RK_PC1 2 &pcfg_pull_none>;
1803 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1805 <3 RK_PC3 2 &pcfg_pull_none>;
1808 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1810 <3 RK_PB4 2 &pcfg_pull_none>;
1813 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1815 <3 RK_PC2 2 &pcfg_pull_none>;
1818 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1820 <3 RK_PB5 2 &pcfg_pull_none>;
1823 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1825 <3 RK_PC4 2 &pcfg_pull_none>;
1828 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1830 <3 RK_PC0 2 &pcfg_pull_none>;
1833 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1835 <3 RK_PB7 2 &pcfg_pull_none>;
1838 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1840 <3 RK_PB6 2 &pcfg_pull_none>;
1843 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1845 <3 RK_PC5 2 &pcfg_pull_none>;
1848 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1850 <3 RK_PB3 2 &pcfg_pull_none>;
1853 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1855 <3 RK_PB1 2 &pcfg_pull_none>;
1858 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1860 <3 RK_PB0 2 &pcfg_pull_none>;
1865 i2s1_2ch_mclk: i2s1-2ch-mclk {
1867 <2 RK_PC3 1 &pcfg_pull_none>;
1870 i2s1_2ch_sclk: i2s1-2ch-sclk {
1872 <2 RK_PC2 1 &pcfg_pull_none>;
1875 i2s1_2ch_lrck: i2s1-2ch-lrck {
1877 <2 RK_PC1 1 &pcfg_pull_none>;
1880 i2s1_2ch_sdi: i2s1-2ch-sdi {
1882 <2 RK_PC5 1 &pcfg_pull_none>;
1885 i2s1_2ch_sdo: i2s1-2ch-sdo {
1887 <2 RK_PC4 1 &pcfg_pull_none>;
1892 i2s2_2ch_mclk: i2s2-2ch-mclk {
1894 <3 RK_PA1 2 &pcfg_pull_none>;
1897 i2s2_2ch_sclk: i2s2-2ch-sclk {
1899 <3 RK_PA2 2 &pcfg_pull_none>;
1902 i2s2_2ch_lrck: i2s2-2ch-lrck {
1904 <3 RK_PA3 2 &pcfg_pull_none>;
1907 i2s2_2ch_sdi: i2s2-2ch-sdi {
1909 <3 RK_PA5 2 &pcfg_pull_none>;
1912 i2s2_2ch_sdo: i2s2-2ch-sdo {
1914 <3 RK_PA7 2 &pcfg_pull_none>;
1919 sdmmc_clk: sdmmc-clk {
1921 <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1924 sdmmc_cmd: sdmmc-cmd {
1926 <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1929 sdmmc_det: sdmmc-det {
1931 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1934 sdmmc_bus1: sdmmc-bus1 {
1936 <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1939 sdmmc_bus4: sdmmc-bus4 {
1941 <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1942 <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1943 <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1944 <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1949 sdio_clk: sdio-clk {
1951 <1 RK_PC5 1 &pcfg_pull_none>;
1954 sdio_cmd: sdio-cmd {
1956 <1 RK_PC4 1 &pcfg_pull_up>;
1959 sdio_bus4: sdio-bus4 {
1961 <1 RK_PC6 1 &pcfg_pull_up>,
1962 <1 RK_PC7 1 &pcfg_pull_up>,
1963 <1 RK_PD0 1 &pcfg_pull_up>,
1964 <1 RK_PD1 1 &pcfg_pull_up>;
1969 emmc_clk: emmc-clk {
1971 <1 RK_PB1 2 &pcfg_pull_none_8ma>;
1974 emmc_cmd: emmc-cmd {
1976 <1 RK_PB2 2 &pcfg_pull_up_8ma>;
1979 emmc_rstnout: emmc-rstnout {
1981 <1 RK_PB3 2 &pcfg_pull_none>;
1984 emmc_bus1: emmc-bus1 {
1986 <1 RK_PA0 2 &pcfg_pull_up_8ma>;
1989 emmc_bus4: emmc-bus4 {
1991 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1992 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1993 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1994 <1 RK_PA3 2 &pcfg_pull_up_8ma>;
1997 emmc_bus8: emmc-bus8 {
1999 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2000 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2001 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2002 <1 RK_PA3 2 &pcfg_pull_up_8ma>,
2003 <1 RK_PA4 2 &pcfg_pull_up_8ma>,
2004 <1 RK_PA5 2 &pcfg_pull_up_8ma>,
2005 <1 RK_PA6 2 &pcfg_pull_up_8ma>,
2006 <1 RK_PA7 2 &pcfg_pull_up_8ma>;
2011 flash_cs0: flash-cs0 {
2013 <1 RK_PB0 1 &pcfg_pull_none>;
2016 flash_rdy: flash-rdy {
2018 <1 RK_PB1 1 &pcfg_pull_none>;
2021 flash_dqs: flash-dqs {
2023 <1 RK_PB2 1 &pcfg_pull_none>;
2026 flash_ale: flash-ale {
2028 <1 RK_PB3 1 &pcfg_pull_none>;
2031 flash_cle: flash-cle {
2033 <1 RK_PB4 1 &pcfg_pull_none>;
2036 flash_wrn: flash-wrn {
2038 <1 RK_PB5 1 &pcfg_pull_none>;
2041 flash_csl: flash-csl {
2043 <1 RK_PB6 1 &pcfg_pull_none>;
2046 flash_rdn: flash-rdn {
2048 <1 RK_PB7 1 &pcfg_pull_none>;
2051 flash_bus8: flash-bus8 {
2053 <1 RK_PA0 1 &pcfg_pull_up_12ma>,
2054 <1 RK_PA1 1 &pcfg_pull_up_12ma>,
2055 <1 RK_PA2 1 &pcfg_pull_up_12ma>,
2056 <1 RK_PA3 1 &pcfg_pull_up_12ma>,
2057 <1 RK_PA4 1 &pcfg_pull_up_12ma>,
2058 <1 RK_PA5 1 &pcfg_pull_up_12ma>,
2059 <1 RK_PA6 1 &pcfg_pull_up_12ma>,
2060 <1 RK_PA7 1 &pcfg_pull_up_12ma>;
2065 sfc_bus4: sfc-bus4 {
2067 <1 RK_PA0 3 &pcfg_pull_none>,
2068 <1 RK_PA1 3 &pcfg_pull_none>,
2069 <1 RK_PA2 3 &pcfg_pull_none>,
2070 <1 RK_PA3 3 &pcfg_pull_none>;
2073 sfc_bus2: sfc-bus2 {
2075 <1 RK_PA0 3 &pcfg_pull_none>,
2076 <1 RK_PA1 3 &pcfg_pull_none>;
2081 <1 RK_PA4 3 &pcfg_pull_none>;
2086 <1 RK_PB1 3 &pcfg_pull_none>;
2091 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2093 <3 RK_PA0 1 &pcfg_pull_none_12ma>;
2096 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2098 <3 RK_PA1 1 &pcfg_pull_none_12ma>;
2101 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2103 <3 RK_PA2 1 &pcfg_pull_none_12ma>;
2106 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2108 <3 RK_PA3 1 &pcfg_pull_none_12ma>;
2111 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2113 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2114 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2115 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2116 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2117 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2118 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2119 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2120 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2121 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2122 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2123 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2124 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2125 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2126 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2127 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2128 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2129 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2130 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2131 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2132 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2133 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2134 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2135 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2136 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2139 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2141 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2142 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2143 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2144 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2145 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2146 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2147 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2148 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2149 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2150 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2151 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2152 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2153 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2154 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2155 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2156 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2157 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2158 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2161 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2163 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2164 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2165 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2166 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2167 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2168 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2169 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2170 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2171 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2172 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2173 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2174 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2175 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2176 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2177 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2178 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2181 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2183 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2184 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2185 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2186 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2187 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2188 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2189 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2190 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2191 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2192 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2193 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2194 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2195 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2196 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2197 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2198 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2199 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2202 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2204 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2205 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2206 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2207 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2208 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2209 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2210 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2211 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2212 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2213 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2214 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2217 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2219 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2220 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2221 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2222 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2223 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2224 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2225 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2226 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2227 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2232 pwm0_pin: pwm0-pin {
2234 <0 RK_PB7 1 &pcfg_pull_none>;
2239 pwm1_pin: pwm1-pin {
2241 <0 RK_PC0 1 &pcfg_pull_none>;
2246 pwm2_pin: pwm2-pin {
2248 <2 RK_PB5 1 &pcfg_pull_none>;
2253 pwm3_pin: pwm3-pin {
2255 <0 RK_PC1 1 &pcfg_pull_none>;
2260 pwm4_pin: pwm4-pin {
2262 <3 RK_PC2 3 &pcfg_pull_none>;
2267 pwm5_pin: pwm5-pin {
2269 <3 RK_PC3 3 &pcfg_pull_none>;
2274 pwm6_pin: pwm6-pin {
2276 <3 RK_PC4 3 &pcfg_pull_none>;
2281 pwm7_pin: pwm7-pin {
2283 <3 RK_PC5 3 &pcfg_pull_none>;
2288 rmii_pins: rmii-pins {
2290 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2291 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2292 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2293 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2294 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2295 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2296 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2297 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2298 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2301 mac_refclk_12ma: mac-refclk-12ma {
2303 <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2306 mac_refclk: mac-refclk {
2308 <2 RK_PB2 2 &pcfg_pull_none>;
2313 cif_clkout_m0: cif-clkout-m0 {
2315 <2 RK_PB3 1 &pcfg_pull_none>;
2318 dvp_d2d9_m0: dvp-d2d9-m0 {
2320 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2321 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2322 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2323 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2324 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2325 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2326 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2327 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2328 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2329 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2330 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2331 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2334 dvp_d0d1_m0: dvp-d0d1-m0 {
2336 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2337 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2340 dvp_d10d11_m0:d10-d11-m0 {
2342 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2343 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2348 cif_clkout_m1: cif-clkout-m1 {
2350 <3 RK_PD0 3 &pcfg_pull_none>;
2353 dvp_d2d9_m1: dvp-d2d9-m1 {
2355 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2356 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2357 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2358 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2359 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2360 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2361 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2362 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2363 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2364 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2365 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2366 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2369 dvp_d0d1_m1: dvp-d0d1-m1 {
2371 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2372 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2375 dvp_d10d11_m1:d10-d11-m1 {
2377 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2378 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2383 isp_prelight: isp-prelight {
2385 <3 RK_PD1 4 &pcfg_pull_none>;