arch/arm/dts/o4-imx6ull-nano.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
   3
   4 /dts-v1/;
   5
   6 #include "imx6ull.dtsi"
   7
   8 / {
   9         model = "O4-iMX6ULL-NANO";
  10         compatible = "out4,o4-imx6ull-nano", "fsl,imx6ull";
  11
  12         aliases {
  13                 mmc0 = &usdhc2;
  14         };
  15
  16         memory@80000000 {
  17                 device_type = "memory";
  18                 reg = <0x80000000 0x20000000>;
  19         };
  20 };
  21
  22 &iomuxc {
  23         pinctrl_usdhc2: usdhc2grp {
  24                 fsl,pins = <
  25                         MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x17059
  26                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x17059
  27                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x17059
  28                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x17059
  29                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x17059
  30                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x17059
  31                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x17059
  32                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x17059
  33                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x17059
  34                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x10069
  35                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x17059
  36                 >;
  37         };
  38
  39         pinctrl_fec1: fec1grp {
  40                 fsl,pins = <
  41                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
  42                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
  43                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
  44                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
  45                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
  46                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
  47                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
  48                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
  49                 >;
  50         };
  51
  52         pinctrl_fec2: fec2grp {
  53                 fsl,pins = <
  54                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
  55                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
  56                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
  57                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
  58                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
  59                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
  60                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
  61                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
  62                 >;
  63         };
  64
  65         pinctrl_phy0_irq: phy0grp {
  66                 fsl,pins = <
  67                         MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x79
  68                 >;
  69         };
  70
  71         pinctrl_phy1_irq: phy1grp {
  72                 fsl,pins = <
  73                         MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x79
  74                 >;
  75         };
  76 };
  77
  78 &usdhc2 {
  79         pinctrl-names = "default";
  80         pinctrl-0 = <&pinctrl_usdhc2>;
  81         no-1-8-v;
  82         non-removable;
  83         keep-power-in-suspend;
  84         wakeup-source;
  85         bus-width = <8>;
  86         status = "okay";
  87 };