arch/arm/dts/nuvoton-npcm750.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
   3 // Copyright 2018 Google, Inc.
   4
   5 #include "nuvoton-common-npcm7xx.dtsi"
   6 #include "nuvoton-npcm7xx-u-boot.dtsi"
   7
   8 / {
   9         #address-cells = <1>;
  10         #size-cells = <1>;
  11         interrupt-parent = <&gic>;
  12
  13         cpus {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16                 enable-method = "nuvoton,npcm750-smp";
  17
  18                 cpu@0 {
  19                         device_type = "cpu";
  20                         compatible = "arm,cortex-a9";
  21                         clocks = <&clk NPCM7XX_CLK_CPU>;
  22                         clock-names = "clk_cpu";
  23                         reg = <0>;
  24                         next-level-cache = <&l2>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a9";
  30                         clocks = <&clk NPCM7XX_CLK_CPU>;
  31                         clock-names = "clk_cpu";
  32                         reg = <1>;
  33                         next-level-cache = <&l2>;
  34                 };
  35         };
  36
  37         soc {
  38                 timer@3fe600 {
  39                         compatible = "arm,cortex-a9-twd-timer";
  40                         reg = <0x3fe600 0x20>;
  41                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  42                                                   IRQ_TYPE_LEVEL_HIGH)>;
  43                         clocks = <&clk NPCM7XX_CLK_AHB>;
  44                 };
  45         };
  46
  47         ahb {
  48                 gmac1: eth@f0804000 {
  49                         device_type = "network";
  50                         compatible = "snps,dwmac";
  51                         reg = <0xf0804000 0x2000>;
  52                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  53                         interrupt-names = "macirq";
  54                         ethernet = <1>;
  55                         clocks  = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>;
  56                         clock-names = "stmmaceth", "clk_gmac";
  57                         pinctrl-names = "default";
  58                         pinctrl-0 = <&rg2_pins
  59                                         &rg2mdio_pins>;
  60                         status = "disabled";
  61                 };
  62         };
  63 };