arch/arm/dts/nuvoton-npcm750-evb.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
   3 // Copyright 2018 Google, Inc.
   4
   5 /dts-v1/;
   6 #include "nuvoton-npcm750.dtsi"
   7 #include "dt-bindings/gpio/gpio.h"
   8 #include "nuvoton-npcm750-pincfg-evb.dtsi"
   9
  10 / {
  11         model = "Nuvoton npcm750 Development Board (Device Tree)";
  12         compatible = "nuvoton,npcm750-evb", "nuvoton,npcm750";
  13
  14         aliases {
  15                 ethernet2 = &gmac0;
  16                 ethernet3 = &gmac1;
  17                 serial0 = &serial0;
  18                 serial1 = &serial1;
  19                 serial2 = &serial2;
  20                 serial3 = &serial3;
  21                 i2c0 = &i2c0;
  22                 i2c1 = &i2c1;
  23                 i2c2 = &i2c2;
  24                 i2c3 = &i2c3;
  25                 i2c4 = &i2c4;
  26                 i2c5 = &i2c5;
  27                 i2c6 = &i2c6;
  28                 i2c7 = &i2c7;
  29                 i2c8 = &i2c8;
  30                 i2c9 = &i2c9;
  31                 i2c10 = &i2c10;
  32                 i2c11 = &i2c11;
  33                 i2c12 = &i2c12;
  34                 i2c13 = &i2c13;
  35                 i2c14 = &i2c14;
  36                 i2c15 = &i2c15;
  37                 spi0 = &spi0;
  38                 spi1 = &spi1;
  39                 fiu0 = &fiu0;
  40                 fiu1 = &fiu3;
  41                 fiu2 = &fiux;
  42         };
  43
  44         chosen {
  45                 stdout-path = &serial0;
  46         };
  47
  48         memory {
  49                 device_type = "memory";
  50                 reg = <0x0 0x20000000>;
  51         };
  52 };
  53
  54 &gmac0 {
  55         phy-mode = "rgmii-id";
  56         status = "okay";
  57 };
  58
  59 &gmac1 {
  60         phy-mode = "rgmii-id";
  61         status = "okay";
  62 };
  63
  64 &ehci1 {
  65         status = "okay";
  66 };
  67
  68 &fiu0 {
  69         status = "okay";
  70         spi-nor@0 {
  71                 compatible = "jedec,spi-nor";
  72                 #address-cells = <1>;
  73                 #size-cells = <1>;
  74                 spi-rx-bus-width = <2>;
  75                 reg = <0>;
  76                 spi-max-frequency = <5000000>;
  77                 partitions@80000000 {
  78                         compatible = "fixed-partitions";
  79                         #address-cells = <1>;
  80                         #size-cells = <1>;
  81                         bbuboot1@0 {
  82                                 label = "bb-uboot-1";
  83                                 reg = <0x0000000 0x80000>;
  84                                 read-only;
  85                                 };
  86                         bbuboot2@80000 {
  87                                 label = "bb-uboot-2";
  88                                 reg = <0x0080000 0x80000>;
  89                                 read-only;
  90                                 };
  91                         envparam@100000 {
  92                                 label = "env-param";
  93                                 reg = <0x0100000 0x40000>;
  94                                 read-only;
  95                                 };
  96                         spare@140000 {
  97                                 label = "spare";
  98                                 reg = <0x0140000 0xC0000>;
  99                                 };
 100                         kernel@200000 {
 101                                 label = "kernel";
 102                                 reg = <0x0200000 0x400000>;
 103                                 };
 104                         rootfs@600000 {
 105                                 label = "rootfs";
 106                                 reg = <0x0600000 0x700000>;
 107                                 };
 108                         spare1@d00000 {
 109                                 label = "spare1";
 110                                 reg = <0x0D00000 0x200000>;
 111                                 };
 112                         spare2@f00000 {
 113                                 label = "spare2";
 114                                 reg = <0x0F00000 0x200000>;
 115                                 };
 116                         spare3@1100000 {
 117                                 label = "spare3";
 118                                 reg = <0x1100000 0x200000>;
 119                                 };
 120                         spare4@1300000 {
 121                                 label = "spare4";
 122                                 reg = <0x1300000 0x0>;
 123                         };
 124                 };
 125         };
 126 };
 127
 128 &fiu3 {
 129         pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
 130         status = "okay";
 131         spi-nor@0 {
 132                 compatible = "jedec,spi-nor";
 133                 #address-cells = <1>;
 134                 #size-cells = <1>;
 135                 spi-rx-bus-width = <2>;
 136                 reg = <0>;
 137                 spi-max-frequency = <5000000>;
 138                 partitions@A0000000 {
 139                         compatible = "fixed-partitions";
 140                         #address-cells = <1>;
 141                         #size-cells = <1>;
 142                         system1@0 {
 143                                 label = "spi3-system1";
 144                                 reg = <0x0 0x0>;
 145                         };
 146                 };
 147         };
 148 };
 149
 150 &fiux {
 151         spix-mode;
 152 };
 153
 154 &watchdog1 {
 155         status = "okay";
 156 };
 157
 158 &rng {
 159         status = "okay";
 160 };
 161
 162 &serial0 {
 163         status = "okay";
 164         clock-frequency = <24000000>;
 165 };
 166
 167 &serial1 {
 168         status = "okay";
 169 };
 170
 171 &serial2 {
 172         status = "okay";
 173 };
 174
 175 &serial3 {
 176         status = "okay";
 177 };
 178
 179 &adc {
 180         status = "okay";
 181 };
 182
 183 &lpc_kcs {
 184         kcs1: kcs1@0 {
 185                 status = "okay";
 186         };
 187
 188         kcs2: kcs2@0 {
 189                 status = "okay";
 190         };
 191
 192         kcs3: kcs3@0 {
 193                 status = "okay";
 194         };
 195 };
 196
 197 /* lm75 on SVB */
 198 &i2c0 {
 199         clock-frequency = <100000>;
 200         status = "okay";
 201         lm75@48 {
 202                 compatible = "lm75";
 203                 reg = <0x48>;
 204                 status = "okay";
 205         };
 206 };
 207
 208 /* lm75 on EB */
 209 &i2c1 {
 210         clock-frequency = <100000>;
 211         status = "okay";
 212         lm75@48 {
 213                 compatible = "lm75";
 214                 reg = <0x48>;
 215                 status = "okay";
 216         };
 217 };
 218
 219 /* tmp100 on EB */
 220 &i2c2 {
 221         clock-frequency = <100000>;
 222         status = "okay";
 223         tmp100@48 {
 224                 compatible = "tmp100";
 225                 reg = <0x48>;
 226                 status = "okay";
 227         };
 228 };
 229
 230 &i2c3 {
 231         clock-frequency = <100000>;
 232         status = "okay";
 233 };
 234
 235 &i2c5 {
 236         clock-frequency = <100000>;
 237         status = "okay";
 238 };
 239
 240 /* tmp100 on SVB */
 241 &i2c6 {
 242         clock-frequency = <100000>;
 243         status = "okay";
 244         tmp100@48 {
 245                 compatible = "tmp100";
 246                 reg = <0x48>;
 247                 status = "okay";
 248         };
 249 };
 250
 251 &i2c7 {
 252         clock-frequency = <100000>;
 253         status = "okay";
 254 };
 255
 256 &i2c8 {
 257         clock-frequency = <100000>;
 258         status = "okay";
 259 };
 260
 261 &i2c9 {
 262         clock-frequency = <100000>;
 263         status = "okay";
 264 };
 265
 266 &i2c10 {
 267         clock-frequency = <100000>;
 268         status = "okay";
 269 };
 270
 271 &i2c11 {
 272         clock-frequency = <100000>;
 273         status = "okay";
 274 };
 275
 276 &i2c14 {
 277         clock-frequency = <100000>;
 278         status = "okay";
 279 };
 280
 281 &pwm_fan {
 282         status = "okay";
 283         fan@0 {
 284                 reg = <0x00>;
 285                 fan-tach-ch = /bits/ 8 <0x00 0x01>;
 286                 cooling-levels = <127 255>;
 287         };
 288         fan@1 {
 289                 reg = <0x01>;
 290                 fan-tach-ch = /bits/ 8 <0x02 0x03>;
 291                 cooling-levels = /bits/ 8 <127 255>;
 292         };
 293         fan@2 {
 294                 reg = <0x02>;
 295                 fan-tach-ch = /bits/ 8 <0x04 0x05>;
 296                 cooling-levels = /bits/ 8 <127 255>;
 297         };
 298         fan@3 {
 299                 reg = <0x03>;
 300                 fan-tach-ch = /bits/ 8 <0x06 0x07>;
 301                 cooling-levels = /bits/ 8 <127 255>;
 302         };
 303         fan@4 {
 304                 reg = <0x04>;
 305                 fan-tach-ch = /bits/ 8 <0x08 0x09>;
 306                 cooling-levels = /bits/ 8 <127 255>;
 307         };
 308         fan@5 {
 309                 reg = <0x05>;
 310                 fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
 311                 cooling-levels = /bits/ 8 <127 255>;
 312         };
 313         fan@6 {
 314                 reg = <0x06>;
 315                 fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
 316                 cooling-levels = /bits/ 8 <127 255>;
 317         };
 318         fan@7 {
 319                 reg = <0x07>;
 320                 fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
 321                 cooling-levels = /bits/ 8 <127 255>;
 322         };
 323 };
 324
 325 &spi0 {
 326         cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 327         status = "okay";
 328         Flash@0 {
 329                 compatible = "winbond,w25q128",
 330                 "jedec,spi-nor";
 331                 reg = <0x0>;
 332                 #address-cells = <1>;
 333                 #size-cells = <1>;
 334                 spi-max-frequency = <5000000>;
 335                 partition@0 {
 336                         label = "spi0_spare1";
 337                         reg = <0x0000000 0x800000>;
 338                 };
 339                 partition@1 {
 340                         label = "spi0_spare2";
 341                         reg = <0x800000 0x0>;
 342                 };
 343         };
 344 };
 345
 346 &spi1 {
 347         cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
 348         status = "okay";
 349         Flash@0 {
 350                 compatible = "winbond,w25q128fw",
 351                 "jedec,spi-nor";
 352                 reg = <0x0>;
 353                 #address-cells = <1>;
 354                 #size-cells = <1>;
 355                 spi-max-frequency = <5000000>;
 356                 partition@0 {
 357                         label = "spi1_spare1";
 358                         reg = <0x0000000 0x800000>;
 359                 };
 360                 partition@1 {
 361                         label = "spi1_spare2";
 362                         reg = <0x800000 0x0>;
 363                 };
 364         };
 365 };
 366
 367 &pinctrl {
 368         pinctrl-names = "default";
 369         pinctrl-0 = <   &iox1_pins
 370                         &pin8_input
 371                         &pin9_output_high
 372                         &pin10_input
 373                         &pin11_output_high
 374                         &pin16_input
 375                         &pin24_output_high
 376                         &pin25_output_low
 377                         &pin32_output_high
 378                         &jtag2_pins
 379                         &pin61_output_high
 380                         &pin62_output_high
 381                         &pin63_output_high
 382                         &lpc_pins
 383                         &pin160_input
 384                         &pin162_input
 385                         &pin168_input
 386                         &pin169_input
 387                         &pin170_input
 388                         &pin187_output_high
 389                         &pin190_input
 390                         &pin191_output_high
 391                         &pin192_output_high
 392                         &pin197_output_low
 393                         &ddc_pins
 394                         &pin218_input
 395                         &pin219_output_low
 396                         &pin220_output_low
 397                         &pin221_output_high
 398                         &pin222_input
 399                         &pin223_output_low
 400                         &spix_pins
 401                         &pin228_output_low
 402                         &pin231_output_high
 403                         &pin255_input>;
 404 };
 405