1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
5 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
10 interrupt-parent = <&gic>;
12 /* external reference clock */
13 clk_refclk: clk_refclk {
14 compatible = "fixed-clock";
16 clock-frequency = <25000000>;
17 clock-output-names = "refclk";
20 /* external reference clock for cpu. float in normal operation */
21 clk_sysbypck: clk_sysbypck {
22 compatible = "fixed-clock";
24 clock-frequency = <800000000>;
25 clock-output-names = "sysbypck";
28 /* external reference clock for MC. float in normal operation */
29 clk_mcbypck: clk_mcbypck {
30 compatible = "fixed-clock";
32 clock-frequency = <800000000>;
33 clock-output-names = "mcbypck";
36 /* external clock signal rg1refck, supplied by the phy */
37 clk_rg1refck: clk_rg1refck {
38 compatible = "fixed-clock";
40 clock-frequency = <125000000>;
41 clock-output-names = "clk_rg1refck";
44 /* external clock signal rg2refck, supplied by the phy */
45 clk_rg2refck: clk_rg2refck {
46 compatible = "fixed-clock";
48 clock-frequency = <125000000>;
49 clock-output-names = "clk_rg2refck";
53 compatible = "fixed-clock";
55 clock-frequency = <50000000>;
56 clock-output-names = "clk_xin";
62 compatible = "simple-bus";
63 interrupt-parent = <&gic>;
64 ranges = <0x0 0xf0000000 0x00900000>;
67 compatible = "arm,cortex-a9-scu";
68 reg = <0x3fe000 0x1000>;
71 l2: cache-controller@3fc000 {
72 compatible = "arm,pl310-cache";
73 reg = <0x3fc000 0x1000>;
74 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&clk NPCM7XX_CLK_AXI>;
81 gic: interrupt-controller@3ff000 {
82 compatible = "arm,cortex-a9-gic";
84 #interrupt-cells = <3>;
85 reg = <0x3ff000 0x1000>,
90 compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
91 reg = <0x800000 0x1000>;
95 compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd";
96 reg = <0x801000 0x6C>;
101 #address-cells = <1>;
103 compatible = "simple-bus";
104 interrupt-parent = <&gic>;
107 rstc: rstc@f0801000 {
108 compatible = "nuvoton,npcm750-reset";
109 reg = <0xf0801000 0x70>;
113 clk: clock-controller@f0801000 {
114 compatible = "nuvoton,npcm750-clk", "syscon";
117 reg = <0xf0801000 0x1000>;
118 clock-names = "refclk", "sysbypck", "mcbypck";
119 clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
122 gmac0: eth@f0802000 {
123 device_type = "network";
124 compatible = "nuvoton,npcm-dwmac";
125 reg = <0xf0802000 0x2000>;
126 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
127 interrupt-names = "macirq";
129 clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
130 clock-names = "stmmaceth", "clk_gmac";
131 pinctrl-names = "default";
132 pinctrl-0 = <&rg1_pins
137 ehci1: usb@f0806000 {
138 compatible = "nuvoton,npcm750-ehci";
139 reg = <0xf0806000 0x1000>;
140 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
145 compatible = "nuvoton,npcm750-fiu";
146 #address-cells = <1>;
148 reg = <0xfb000000 0x1000>;
149 reg-names = "control", "memory";
150 clocks = <&clk NPCM7XX_CLK_SPI0>;
151 clock-names = "clk_spi0";
156 compatible = "nuvoton,npcm750-fiu";
157 #address-cells = <1>;
159 reg = <0xc0000000 0x1000>;
160 reg-names = "control", "memory";
161 clocks = <&clk NPCM7XX_CLK_SPI3>;
162 clock-names = "clk_spi3";
163 pinctrl-names = "default";
164 pinctrl-0 = <&spi3_pins>;
169 compatible = "nuvoton,npcm750-fiu";
170 #address-cells = <1>;
172 reg = <0xfb001000 0x1000>;
173 reg-names = "control", "memory";
174 clocks = <&clk NPCM7XX_CLK_SPIX>;
175 clock-names = "clk_spix";
180 #address-cells = <1>;
182 compatible = "simple-bus";
183 interrupt-parent = <&gic>;
184 ranges = <0x0 0xf0000000 0x00300000>;
186 lpc_kcs: lpc_kcs@7000 {
187 compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
191 #address-cells = <1>;
193 ranges = <0x0 0x7000 0x40>;
196 compatible = "nuvoton,npcm750-kcs-bmc";
198 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
204 compatible = "nuvoton,npcm750-kcs-bmc";
206 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
212 compatible = "nuvoton,npcm750-kcs-bmc";
214 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
221 compatible = "nuvoton,npcm750-pspi";
222 reg = <0x200000 0x1000>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&pspi1_pins>;
225 #address-cells = <1>;
227 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&clk NPCM7XX_CLK_APB5>;
229 clock-names = "clk_apb5";
230 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
235 compatible = "nuvoton,npcm750-pspi";
236 reg = <0x201000 0x1000>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&pspi2_pins>;
239 #address-cells = <1>;
241 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&clk NPCM7XX_CLK_APB5>;
243 clock-names = "clk_apb5";
244 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI2>;
249 compatible = "nuvoton,npcm750-timer";
250 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&clk NPCM7XX_CLK_TIMER>;
255 watchdog0: watchdog@801C {
256 compatible = "nuvoton,npcm750-wdt";
257 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&clk NPCM7XX_CLK_TIMER>;
263 watchdog1: watchdog@901C {
264 compatible = "nuvoton,npcm750-wdt";
265 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&clk NPCM7XX_CLK_TIMER>;
271 watchdog2: watchdog@a01C {
272 compatible = "nuvoton,npcm750-wdt";
273 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&clk NPCM7XX_CLK_TIMER>;
279 serial0: serial@1000 {
280 compatible = "nuvoton,npcm750-uart";
281 reg = <0x1000 0x1000>;
282 clocks = <&clk NPCM7XX_CLK_UART>, <&clk NPCM7XX_CLK_PLL2DIV2>;
283 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
288 serial1: serial@2000 {
289 compatible = "nuvoton,npcm750-uart";
290 reg = <0x2000 0x1000>;
291 clocks = <&clk NPCM7XX_CLK_UART>, <&clk NPCM7XX_CLK_PLL2DIV2>;
292 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
297 serial2: serial@3000 {
298 compatible = "nuvoton,npcm750-uart";
299 reg = <0x3000 0x1000>;
300 clocks = <&clk NPCM7XX_CLK_UART>, <&clk NPCM7XX_CLK_PLL2DIV2>;
301 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
306 serial3: serial@4000 {
307 compatible = "nuvoton,npcm750-uart";
308 reg = <0x4000 0x1000>;
309 clocks = <&clk NPCM7XX_CLK_UART>, <&clk NPCM7XX_CLK_PLL2DIV2>;
310 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
316 compatible = "nuvoton,npcm750-rng";
322 compatible = "nuvoton,npcm750-adc";
324 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&clk NPCM7XX_CLK_ADC>;
326 resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>;
330 pwm_fan: pwm-fan-controller@103000 {
331 #address-cells = <1>;
333 compatible = "nuvoton,npcm750-pwm-fan";
334 reg = <0x103000 0x2000>, <0x180000 0x8000>;
335 reg-names = "pwm", "fan";
336 clocks = <&clk NPCM7XX_CLK_APB3>,
337 <&clk NPCM7XX_CLK_APB4>;
338 clock-names = "pwm","fan";
339 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&pwm0_pins &pwm1_pins
349 &pwm2_pins &pwm3_pins
350 &pwm4_pins &pwm5_pins
351 &pwm6_pins &pwm7_pins
352 &fanin0_pins &fanin1_pins
353 &fanin2_pins &fanin3_pins
354 &fanin4_pins &fanin5_pins
355 &fanin6_pins &fanin7_pins
356 &fanin8_pins &fanin9_pins
357 &fanin10_pins &fanin11_pins
358 &fanin12_pins &fanin13_pins
359 &fanin14_pins &fanin15_pins>;
364 reg = <0x80000 0x1000>;
365 compatible = "nuvoton,npcm750-i2c";
366 #address-cells = <1>;
368 clocks = <&clk NPCM7XX_CLK_APB2>;
369 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&smb0_pins>;
376 reg = <0x81000 0x1000>;
377 compatible = "nuvoton,npcm750-i2c";
378 #address-cells = <1>;
380 clocks = <&clk NPCM7XX_CLK_APB2>;
381 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&smb1_pins>;
388 reg = <0x82000 0x1000>;
389 compatible = "nuvoton,npcm750-i2c";
390 #address-cells = <1>;
392 clocks = <&clk NPCM7XX_CLK_APB2>;
393 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&smb2_pins>;
400 reg = <0x83000 0x1000>;
401 compatible = "nuvoton,npcm750-i2c";
402 #address-cells = <1>;
404 clocks = <&clk NPCM7XX_CLK_APB2>;
405 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&smb3_pins>;
412 reg = <0x84000 0x1000>;
413 compatible = "nuvoton,npcm750-i2c";
414 #address-cells = <1>;
416 clocks = <&clk NPCM7XX_CLK_APB2>;
417 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&smb4_pins>;
424 reg = <0x85000 0x1000>;
425 compatible = "nuvoton,npcm750-i2c";
426 #address-cells = <1>;
428 clocks = <&clk NPCM7XX_CLK_APB2>;
429 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&smb5_pins>;
436 reg = <0x86000 0x1000>;
437 compatible = "nuvoton,npcm750-i2c";
438 #address-cells = <1>;
440 clocks = <&clk NPCM7XX_CLK_APB2>;
441 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&smb6_pins>;
448 reg = <0x87000 0x1000>;
449 compatible = "nuvoton,npcm750-i2c";
450 #address-cells = <1>;
452 clocks = <&clk NPCM7XX_CLK_APB2>;
453 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&smb7_pins>;
460 reg = <0x88000 0x1000>;
461 compatible = "nuvoton,npcm750-i2c";
462 #address-cells = <1>;
464 clocks = <&clk NPCM7XX_CLK_APB2>;
465 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
466 pinctrl-names = "default";
467 pinctrl-0 = <&smb8_pins>;
472 reg = <0x89000 0x1000>;
473 compatible = "nuvoton,npcm750-i2c";
474 #address-cells = <1>;
476 clocks = <&clk NPCM7XX_CLK_APB2>;
477 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&smb9_pins>;
484 reg = <0x8a000 0x1000>;
485 compatible = "nuvoton,npcm750-i2c";
486 #address-cells = <1>;
488 clocks = <&clk NPCM7XX_CLK_APB2>;
489 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&smb10_pins>;
496 reg = <0x8b000 0x1000>;
497 compatible = "nuvoton,npcm750-i2c";
498 #address-cells = <1>;
500 clocks = <&clk NPCM7XX_CLK_APB2>;
501 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&smb11_pins>;
508 reg = <0x8c000 0x1000>;
509 compatible = "nuvoton,npcm750-i2c";
510 #address-cells = <1>;
512 clocks = <&clk NPCM7XX_CLK_APB2>;
513 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&smb12_pins>;
520 reg = <0x8d000 0x1000>;
521 compatible = "nuvoton,npcm750-i2c";
522 #address-cells = <1>;
524 clocks = <&clk NPCM7XX_CLK_APB2>;
525 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
526 pinctrl-names = "default";
527 pinctrl-0 = <&smb13_pins>;
532 reg = <0x8e000 0x1000>;
533 compatible = "nuvoton,npcm750-i2c";
534 #address-cells = <1>;
536 clocks = <&clk NPCM7XX_CLK_APB2>;
537 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&smb14_pins>;
544 reg = <0x8f000 0x1000>;
545 compatible = "nuvoton,npcm750-i2c";
546 #address-cells = <1>;
548 clocks = <&clk NPCM7XX_CLK_APB2>;
549 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&smb15_pins>;
557 pinctrl: pinctrl@f0800000 {
558 #address-cells = <1>;
560 compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd";
561 ranges = <0 0xf0010000 0x8000>;
562 gpio0: gpio@f0010000 {
566 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
567 gpio-ranges = <&pinctrl 0 0 32>;
569 gpio1: gpio@f0011000 {
573 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
574 gpio-ranges = <&pinctrl 0 32 32>;
576 gpio2: gpio@f0012000 {
580 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
581 gpio-ranges = <&pinctrl 0 64 32>;
583 gpio3: gpio@f0013000 {
587 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
588 gpio-ranges = <&pinctrl 0 96 32>;
590 gpio4: gpio@f0014000 {
594 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
595 gpio-ranges = <&pinctrl 0 128 32>;
597 gpio5: gpio@f0015000 {
601 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
602 gpio-ranges = <&pinctrl 0 160 32>;
604 gpio6: gpio@f0016000 {
608 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
609 gpio-ranges = <&pinctrl 0 192 32>;
611 gpio7: gpio@f0017000 {
615 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
616 gpio-ranges = <&pinctrl 0 224 32>;
619 iox1_pins: iox1-pins {
623 iox2_pins: iox2-pins {
627 smb1d_pins: smb1d-pins {
631 smb2d_pins: smb2d-pins {
635 lkgpo1_pins: lkgpo1-pins {
639 lkgpo2_pins: lkgpo2-pins {
643 ioxh_pins: ioxh-pins {
647 gspi_pins: gspi-pins {
651 smb5b_pins: smb5b-pins {
655 smb5c_pins: smb5c-pins {
659 lkgpo0_pins: lkgpo0-pins {
663 pspi2_pins: pspi2-pins {
667 smb4den_pins: smb4den-pins {
669 function = "smb4den";
671 smb4b_pins: smb4b-pins {
675 smb4c_pins: smb4c-pins {
679 smb15_pins: smb15-pins {
683 smb4d_pins: smb4d-pins {
687 smb14_pins: smb14-pins {
691 smb5_pins: smb5-pins {
695 smb4_pins: smb4-pins {
699 smb3_pins: smb3-pins {
703 spi0cs1_pins: spi0cs1-pins {
705 function = "spi0cs1";
707 spi0cs2_pins: spi0cs2-pins {
709 function = "spi0cs2";
711 spi0cs3_pins: spi0cs3-pins {
713 function = "spi0cs3";
715 smb3c_pins: smb3c-pins {
719 smb3b_pins: smb3b-pins {
723 bmcuart0a_pins: bmcuart0a-pins {
724 groups = "bmcuart0a";
725 function = "bmcuart0a";
727 uart1_pins: uart1-pins {
731 jtag2_pins: jtag2-pins {
735 bmcuart1_pins: bmcuart1-pins {
737 function = "bmcuart1";
739 uart2_pins: uart2-pins {
743 bmcuart0b_pins: bmcuart0b-pins {
744 groups = "bmcuart0b";
745 function = "bmcuart0b";
747 r1err_pins: r1err-pins {
751 r1md_pins: r1md-pins {
755 smb3d_pins: smb3d-pins {
759 fanin0_pins: fanin0-pins {
763 fanin1_pins: fanin1-pins {
767 fanin2_pins: fanin2-pins {
771 fanin3_pins: fanin3-pins {
775 fanin4_pins: fanin4-pins {
779 fanin5_pins: fanin5-pins {
783 fanin6_pins: fanin6-pins {
787 fanin7_pins: fanin7-pins {
791 fanin8_pins: fanin8-pins {
795 fanin9_pins: fanin9-pins {
799 fanin10_pins: fanin10-pins {
801 function = "fanin10";
803 fanin11_pins: fanin11-pins {
805 function = "fanin11";
807 fanin12_pins: fanin12-pins {
809 function = "fanin12";
811 fanin13_pins: fanin13-pins {
813 function = "fanin13";
815 fanin14_pins: fanin14-pins {
817 function = "fanin14";
819 fanin15_pins: fanin15-pins {
821 function = "fanin15";
823 pwm0_pins: pwm0-pins {
827 pwm1_pins: pwm1-pins {
831 pwm2_pins: pwm2-pins {
835 pwm3_pins: pwm3-pins {
843 r2err_pins: r2err-pins {
847 r2md_pins: r2md-pins {
851 ga20kbc_pins: ga20kbc-pins {
853 function = "ga20kbc";
855 smb5d_pins: smb5d-pins {
863 espi_pins: espi-pins {
871 rg1mdio_pins: rg1mdio-pins {
873 function = "rg1mdio";
883 smb0_pins: smb0-pins {
887 smb1_pins: smb1-pins {
891 smb2_pins: smb2-pins {
895 smb2c_pins: smb2c-pins {
899 smb2b_pins: smb2b-pins {
903 smb1c_pins: smb1c-pins {
907 smb1b_pins: smb1b-pins {
911 smb8_pins: smb8-pins {
915 smb9_pins: smb9-pins {
919 smb10_pins: smb10-pins {
923 smb11_pins: smb11-pins {
931 sd1pwr_pins: sd1pwr-pins {
935 pwm4_pins: pwm4-pins {
939 pwm5_pins: pwm5-pins {
943 pwm6_pins: pwm6-pins {
947 pwm7_pins: pwm7-pins {
951 mmc8_pins: mmc8-pins {
959 mmcwp_pins: mmcwp-pins {
963 mmccd_pins: mmccd-pins {
967 mmcrst_pins: mmcrst-pins {
971 clkout_pins: clkout-pins {
975 serirq_pins: serirq-pins {
979 lpcclk_pins: lpcclk-pins {
983 scipme_pins: scipme-pins {
991 smb6_pins: smb6-pins {
995 smb7_pins: smb7-pins {
999 pspi1_pins: pspi1-pins {
1003 faninx_pins: faninx-pins {
1005 function = "faninx";
1011 spi3_pins: spi3-pins {
1015 spi3cs1_pins: spi3cs1-pins {
1017 function = "spi3cs1";
1019 spi3quad_pins: spi3quad-pins {
1020 groups = "spi3quad";
1021 function = "spi3quad";
1023 spi3cs2_pins: spi3cs2-pins {
1025 function = "spi3cs2";
1027 spi3cs3_pins: spi3cs3-pins {
1029 function = "spi3cs3";
1031 nprd_smi_pins: nprd-smi-pins {
1032 groups = "nprd_smi";
1033 function = "nprd_smi";
1035 smb0b_pins: smb0b-pins {
1039 smb0c_pins: smb0c-pins {
1043 smb0den_pins: smb0den-pins {
1045 function = "smb0den";
1047 smb0d_pins: smb0d-pins {
1051 ddc_pins: ddc-pins {
1055 rg2mdio_pins: rg2mdio-pins {
1057 function = "rg2mdio";
1059 wdog1_pins: wdog1-pins {
1063 wdog2_pins: wdog2-pins {
1067 smb12_pins: smb12-pins {
1071 smb13_pins: smb13-pins {
1075 spix_pins: spix-pins {
1079 spixcs1_pins: spixcs1-pins {
1081 function = "spixcs1";
1083 clkreq_pins: clkreq-pins {
1085 function = "clkreq";
1087 hgpio0_pins: hgpio0-pins {
1089 function = "hgpio0";
1091 hgpio1_pins: hgpio1-pins {
1093 function = "hgpio1";
1095 hgpio2_pins: hgpio2-pins {
1097 function = "hgpio2";
1099 hgpio3_pins: hgpio3-pins {
1101 function = "hgpio3";
1103 hgpio4_pins: hgpio4-pins {
1105 function = "hgpio4";
1107 hgpio5_pins: hgpio5-pins {
1109 function = "hgpio5";
1111 hgpio6_pins: hgpio6-pins {
1113 function = "hgpio6";
1115 hgpio7_pins: hgpio7-pins {
1117 function = "hgpio7";