1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2019 BayLibre, SAS
4 * Author: Fabien Parent <fparent@baylibre.com>
7 #include <dt-bindings/clock/mt8516-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "mediatek,mt8516";
14 interrupt-parent = <&sysirq>;
21 enable-method = "mediatek,mt8516-smp";
25 compatible = "arm,cortex-a35";
27 clock-frequency = <1300000000>;
32 compatible = "arm,cortex-a35";
34 clock-frequency = <1300000000>;
39 compatible = "arm,cortex-a35";
41 clock-frequency = <1300000000>;
46 compatible = "arm,cortex-a35";
48 clock-frequency = <1300000000>;
52 topckgen: clock-controller@10000000 {
53 compatible = "mediatek,mt8516-topckgen";
54 reg = <0x10000000 0x1000>;
58 topckgen_cg: clock-controller-cg@10000000 {
59 compatible = "mediatek,mt8516-topckgen-cg";
60 reg = <0x10000000 0x1000>;
64 infracfg: clock-controller@10001000 {
65 compatible = "mediatek,mt8516-infracfg";
66 reg = <0x10001000 0x1000>;
70 apmixedsys: clock-controller@10018000 {
71 compatible = "mediatek,mt8516-apmixedsys";
72 reg = <0x10018000 0x710>;
76 gic: interrupt-controller@10310000 {
77 compatible = "arm,gic-400";
79 #interrupt-cells = <3>;
80 interrupt-parent = <&gic>;
81 reg = <0x10310000 0x1000>,
85 interrupts = <GIC_PPI 9
86 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
89 sysirq: interrupt-controller@10200620 {
90 compatible = "mediatek,sysirq";
92 #interrupt-cells = <3>;
93 interrupt-parent = <&gic>;
94 reg = <0x10200620 0x20>;
97 watchdog: watchdog@10007000 {
98 compatible = "mediatek,wdt";
99 reg = <0x10007000 0x1000>;
100 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
105 pinctrl: pinctrl@10005000 {
106 compatible = "mediatek,mt8516-pinctrl";
107 reg = <0x10005000 0x1000>;
109 gpio: gpio-controller {
116 compatible = "mediatek,mt8516-mmc";
117 reg = <0x11120000 0x1000>;
118 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
119 clocks = <&topckgen_cg CLK_TOP_MSDC0>,
120 <&topckgen CLK_TOP_AHB_INFRA_SEL>,
121 <&topckgen_cg CLK_TOP_MSDC0_INFRA>;
122 clock-names = "source", "hclk", "source_cg";
126 uart0: serial@11005000 {
127 compatible = "mediatek,hsuart";
128 reg = <0x11005000 0x1000>;
130 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
131 clocks = <&topckgen CLK_TOP_UART0_SEL>,
132 <&topckgen_cg CLK_TOP_UART0>;
133 clock-names = "baud","bus";