1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2021 MediaTek Inc.
4 * Copyright (C) 2021 BayLibre, SAS
5 * Author: Ben Ho <ben.ho@mediatek.com>
6 * Erin Lo <erin.lo@mediatek.com>
7 * Fabien Parent <fparent@baylibre.com>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/clock/mt8183-clk.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/phy/phy.h>
17 compatible = "mediatek,mt8183";
18 interrupt-parent = <&sysirq>;
60 compatible = "arm,cortex-a53";
62 enable-method = "psci";
63 capacity-dmips-mhz = <741>;
68 compatible = "arm,cortex-a53";
70 enable-method = "psci";
71 capacity-dmips-mhz = <741>;
76 compatible = "arm,cortex-a53";
78 enable-method = "psci";
79 capacity-dmips-mhz = <741>;
84 compatible = "arm,cortex-a53";
86 enable-method = "psci";
87 capacity-dmips-mhz = <741>;
92 compatible = "arm,cortex-a73";
94 enable-method = "psci";
95 capacity-dmips-mhz = <1024>;
100 compatible = "arm,cortex-a73";
102 enable-method = "psci";
103 capacity-dmips-mhz = <1024>;
108 compatible = "arm,cortex-a73";
110 enable-method = "psci";
111 capacity-dmips-mhz = <1024>;
116 compatible = "arm,cortex-a73";
118 enable-method = "psci";
119 capacity-dmips-mhz = <1024>;
124 compatible = "fixed-clock";
126 clock-frequency = <26000000>;
127 clock-output-names = "clk26m";
131 #address-cells = <2>;
133 compatible = "simple-bus";
136 watchdog: watchdog@10007000 {
137 compatible = "mediatek,mt8183-wdt",
139 reg = <0 0x10007000 0 0x100>;
143 gic: interrupt-controller@c000000 {
144 compatible = "arm,gic-v3";
145 #interrupt-cells = <4>;
146 interrupt-parent = <&gic>;
147 interrupt-controller;
148 reg = <0 0x0c000000 0 0x40000>, /* GICD */
149 <0 0x0c100000 0 0x200000>, /* GICR */
150 <0 0x0c400000 0 0x2000>, /* GICC */
151 <0 0x0c410000 0 0x1000>, /* GICH */
152 <0 0x0c420000 0 0x2000>; /* GICV */
154 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
156 ppi_cluster0: interrupt-partition-0 {
157 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
159 ppi_cluster1: interrupt-partition-1 {
160 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
165 sysirq: interrupt-controller@c530a80 {
166 compatible = "mediatek,mt8183-sysirq",
167 "mediatek,mt6577-sysirq";
168 interrupt-controller;
169 #interrupt-cells = <3>;
170 interrupt-parent = <&gic>;
171 reg = <0 0x0c530a80 0 0x50>;
174 topckgen: syscon@10000000 {
175 compatible = "mediatek,mt8183-topckgen", "syscon";
176 reg = <0 0x10000000 0 0x1000>;
180 infracfg: syscon@10001000 {
181 compatible = "mediatek,mt8183-infracfg", "syscon";
182 reg = <0 0x10001000 0 0x1000>;
186 apmixedsys: syscon@1000c000 {
187 compatible = "mediatek,mt8183-apmixedsys", "syscon";
188 reg = <0 0x1000c000 0 0x1000>;
192 uart0: serial@11002000 {
193 compatible = "mediatek,mt8183-uart",
195 reg = <0 0x11002000 0 0x1000>;
196 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
197 clock-frequency = <26000000>;
198 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
199 clock-names = "baud", "bus";
204 compatible = "mediatek,mt8183-mmc";
205 reg = <0 0x11230000 0 0x1000>,
206 <0 0x11f50000 0 0x1000>;
207 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
208 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
209 <&infracfg CLK_INFRA_MSDC0>,
210 <&infracfg CLK_INFRA_MSDC0_SCK>;
211 clock-names = "source", "hclk", "source_cg";
215 u3phy: usb-phy@11f40000 {
216 compatible = "mediatek,generic-tphy-v2";
217 #address-cells = <2>;
222 u2port0: usb-phy2@11f40000 {
223 reg = <0 0x11f40000 0 0x700>;
230 u3port0: usb-phy3@11f40700 {
231 reg = <0 0x11f40700 0 0x900>;
240 compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
241 reg = <0 0x11200000 0 0x3e00>,
242 <0 0x11203e00 0 0x0100>;
243 reg-names = "mac", "ippc";
244 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
245 phys = <&u2port0 PHY_TYPE_USB2>;
246 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
247 <&infracfg CLK_INFRA_USB>;
248 clock-names = "sys_ck", "ref_ck";
249 #address-cells = <2>;
254 ssusb: ssusb@11200000 {
255 compatible = "mediatek,ssusb";
256 reg = <0 0x11200000 0 0x3e00>;
258 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
262 usb_host: xhci@11200000 {
263 compatible = "mediatek,mtk-xhci";
264 reg = <0 0x11200000 0 0x1000>;
266 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
267 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
268 <&infracfg CLK_INFRA_USB>;
269 clock-names = "sys_ck", "ref_ck";