arch/arm/dts/mt7629.dtsi

   1 /*
   2  * Copyright (C) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 #include <dt-bindings/clock/mt7629-clk.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/power/mt7629-power.h>
  13 #include <dt-bindings/reset/mt7629-reset.h>
  14 #include <dt-bindings/phy/phy.h>
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         compatible = "mediatek,mt7629";
  19         interrupt-parent = <&sysirq>;
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26                 enable-method = "mediatek,mt6589-smp";
  27
  28                 cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a7";
  31                         reg = <0x0>;
  32                         clock-frequency = <1250000000>;
  33                 };
  34
  35                 cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a7";
  38                         reg = <0x1>;
  39                         clock-frequency = <1250000000>;
  40                 };
  41         };
  42
  43         clk20m: oscillator@0 {
  44                 compatible = "fixed-clock";
  45                 #clock-cells = <0>;
  46                 clock-frequency = <20000000>;
  47                 clock-output-names = "clk20m";
  48         };
  49
  50         clk40m: oscillator@1 {
  51                 compatible = "fixed-clock";
  52                 #clock-cells = <0>;
  53                 clock-frequency = <40000000>;
  54                 clock-output-names = "clkxtal";
  55         };
  56
  57         timer {
  58                 compatible = "arm,armv7-timer";
  59                 interrupt-parent = <&gic>;
  60                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  61                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  62                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  63                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  64                 clock-frequency = <20000000>;
  65                 arm,cpu-registers-not-fw-configured;
  66         };
  67
  68         infracfg: syscon@10000000 {
  69                 compatible = "mediatek,mt7629-infracfg", "syscon";
  70                 reg = <0x10000000 0x1000>;
  71                 #clock-cells = <1>;
  72         };
  73
  74         pericfg: syscon@10002000 {
  75                 compatible = "mediatek,mt7629-pericfg", "syscon";
  76                 reg = <0x10002000 0x1000>;
  77                 #clock-cells = <1>;
  78         };
  79
  80         timer0: timer@10004000 {
  81                 compatible = "mediatek,timer";
  82                 reg = <0x10004000 0x80>;
  83                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
  84                 clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
  85                          <&topckgen CLK_TOP_10M_SEL>;
  86                 clock-names = "mux", "src";
  87         };
  88
  89         scpsys: scpsys@10006000 {
  90                 compatible = "mediatek,mt7629-scpsys";
  91                 reg = <0x10006000 0x1000>;
  92                 clocks = <&topckgen CLK_TOP_HIF_SEL>;
  93                 clock-names = "hif_sel";
  94                 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
  95                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
  96                 #power-domain-cells = <1>;
  97                 infracfg = <&infracfg>;
  98         };
  99
 100         mcucfg: syscon@10200000 {
 101                 compatible = "mediatek,mt7629-mcucfg", "syscon";
 102                 reg = <0x10200000 0x1000>;
 103                 #clock-cells = <1>;
 104         };
 105
 106         sysirq: interrupt-controller@10200a80 {
 107                 compatible = "mediatek,sysirq";
 108                 reg = <0x10200a80 0x20>;
 109                 interrupt-controller;
 110                 #interrupt-cells = <3>;
 111                 interrupt-parent = <&gic>;
 112         };
 113
 114         dramc: dramc@10203000 {
 115                 compatible = "mediatek,mt7629-dramc";
 116                 reg = <0x10203000 0x600>,       /* EMI */
 117                       <0x10213000 0x1000>,      /* DDRPHY */
 118                       <0x10214000 0xd00>;       /* DRAMC_AO */
 119                 clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>,
 120                          <&topckgen CLK_TOP_SYSPLL1_D8>,
 121                          <&topckgen CLK_TOP_MEM_SEL>,
 122                          <&topckgen CLK_TOP_DMPLL>;
 123                 clock-names = "phy", "phy_mux", "mem", "mem_mux";
 124         };
 125
 126         apmixedsys: clock-controller@10209000 {
 127                 compatible = "mediatek,mt7629-apmixedsys";
 128                 reg = <0x10209000 0x1000>;
 129                 #clock-cells = <1>;
 130         };
 131
 132         topckgen: clock-controller@10210000 {
 133                 compatible = "mediatek,mt7629-topckgen";
 134                 reg = <0x10210000 0x1000>;
 135                 #clock-cells = <1>;
 136         };
 137
 138         watchdog: watchdog@10212000 {
 139                 compatible = "mediatek,wdt";
 140                 reg = <0x10212000 0x600>;
 141                 interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_FALLING>;
 142                 #reset-cells = <1>;
 143                 status = "disabled";
 144         };
 145
 146         wdt-reboot {
 147                 compatible = "wdt-reboot";
 148                 wdt = <&watchdog>;
 149         };
 150
 151         pinctrl: pinctrl@10217000 {
 152                 compatible = "mediatek,mt7629-pinctrl";
 153                 reg = <0x10217000 0x8000>;
 154
 155                 pinctrl-names = "default";
 156                 pinctrl-0 = <&state_default>;
 157
 158                 state_default: pinmux_conf {
 159                 };
 160
 161                 gpio: gpio-controller {
 162                         gpio-controller;
 163                         #gpio-cells = <2>;
 164                 };
 165         };
 166
 167         gic: interrupt-controller@10300000 {
 168                 compatible = "arm,gic-400";
 169                 interrupt-controller;
 170                 #interrupt-cells = <3>;
 171                 interrupt-parent = <&gic>;
 172                 reg = <0x10310000 0x1000>,
 173                       <0x10320000 0x1000>,
 174                       <0x10340000 0x2000>,
 175                       <0x10360000 0x2000>;
 176         };
 177
 178         uart0: serial@11002000 {
 179                 compatible = "mediatek,hsuart";
 180                 reg = <0x11002000 0x400>;
 181                 reg-shift = <2>;
 182                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 183                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 184                          <&pericfg CLK_PERI_UART0_PD>;
 185                 clock-names = "baud", "bus";
 186                 status = "disabled";
 187                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 188                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 189         };
 190
 191         uart1: serial@11003000 {
 192                 compatible = "mediatek,hsuart";
 193                 reg = <0x11003000 0x400>;
 194                 reg-shift = <2>;
 195                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 196                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 197                          <&pericfg CLK_PERI_UART1_PD>;
 198                 clock-names = "baud", "bus";
 199                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 200                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 201                 status = "disabled";
 202         };
 203
 204         uart2: serial@11004000 {
 205                 compatible = "mediatek,hsuart";
 206                 reg = <0x11004000 0x400>;
 207                 reg-shift = <2>;
 208                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 209                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 210                          <&pericfg CLK_PERI_UART2_PD>;
 211                 clock-names = "baud", "bus";
 212                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 213                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 214                 status = "disabled";
 215         };
 216
 217         snfi: snfi@1100d000 {
 218                 compatible = "mediatek,mtk-snfi-spi";
 219                 reg = <0x1100d000 0x2000>;
 220                 clocks = <&pericfg CLK_PERI_NFI_PD>,
 221                          <&pericfg CLK_PERI_SNFI_PD>;
 222                 clock-names = "nfi_clk", "pad_clk";
 223                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
 224                                   <&topckgen CLK_TOP_NFI_INFRA_SEL>;
 225                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
 226                                          <&topckgen CLK_TOP_UNIVPLL2_D8>;
 227                 status = "disabled";
 228                 #address-cells = <1>;
 229                 #size-cells = <0>;
 230         };
 231
 232         snor: snor@11014000 {
 233                 compatible = "mediatek,mtk-snor";
 234                 reg = <0x11014000 0x1000>;
 235                 clocks = <&pericfg CLK_PERI_FLASH_PD>,
 236                          <&topckgen CLK_TOP_FLASH_SEL>;
 237                 clock-names = "spi", "sf";
 238                 status = "disabled";
 239                 #address-cells = <1>;
 240                 #size-cells = <0>;
 241         };
 242
 243         ssusbsys: ssusbsys@1a000000 {
 244                 compatible = "mediatek,mt7629-ssusbsys", "syscon";
 245                 reg = <0x1a000000 0x1000>;
 246                 #clock-cells = <1>;
 247         };
 248
 249         xhci: usb@1a0c0000 {
 250                 compatible = "mediatek,mt7629-xhci", "mediatek,mtk-xhci";
 251                 reg = <0x1a0c0000 0x1000>, <0x1a0c3e00 0x0100>;
 252                 reg-names = "mac", "ippc";
 253                 power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
 254                 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
 255                          <&ssusbsys CLK_SSUSB_REF_EN>,
 256                          <&ssusbsys CLK_SSUSB_MCU_EN>,
 257                          <&ssusbsys CLK_SSUSB_DMA_EN>;
 258                 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
 259                 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 260                 status = "disabled";
 261         };
 262
 263         u3phy: usb-phy@1a0c4000 {
 264                 compatible = "mediatek,mt7629-tphy", "mediatek,generic-tphy-v2";
 265                 #address-cells = <1>;
 266                 #size-cells = <1>;
 267                 ranges = <0 0x1a0c4000 0x1000>;
 268                 status = "disabled";
 269
 270                 u2port0: usb-phy@0 {
 271                         reg = <0x0 0x0700>;
 272                         #phy-cells = <1>;
 273                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
 274                         clock-names = "ref";
 275                 };
 276
 277                 u3port0: usb-phy@700 {
 278                         reg = <0x0700 0x0700>;
 279                         #phy-cells = <1>;
 280                 };
 281         };
 282
 283         ethsys: syscon@1b000000 {
 284                 compatible = "mediatek,mt7629-ethsys", "syscon";
 285                 reg = <0x1b000000 0x1000>;
 286                 #clock-cells = <1>;
 287                 #reset-cells = <1>;
 288         };
 289
 290         eth: ethernet@1b100000 {
 291                 compatible = "mediatek,mt7629-eth", "syscon";
 292                 reg = <0x1b100000 0x20000>;
 293                 clocks = <&topckgen CLK_TOP_ETH_SEL>,
 294                         <&topckgen CLK_TOP_F10M_REF_SEL>,
 295                         <&ethsys CLK_ETH_ESW_EN>,
 296                         <&ethsys CLK_ETH_GP0_EN>,
 297                         <&ethsys CLK_ETH_GP1_EN>,
 298                         <&ethsys CLK_ETH_GP2_EN>,
 299                         <&ethsys CLK_ETH_FE_EN>,
 300                         <&sgmiisys0 CLK_SGMII_TX_EN>,
 301                         <&sgmiisys0 CLK_SGMII_RX_EN>,
 302                         <&sgmiisys0 CLK_SGMII_CDR_REF>,
 303                         <&sgmiisys0 CLK_SGMII_CDR_FB>,
 304                         <&sgmiisys1 CLK_SGMII_TX_EN>,
 305                         <&sgmiisys1 CLK_SGMII_RX_EN>,
 306                         <&sgmiisys1 CLK_SGMII_CDR_REF>,
 307                         <&sgmiisys1 CLK_SGMII_CDR_FB>,
 308                         <&apmixedsys CLK_APMIXED_SGMIPLL>,
 309                         <&apmixedsys CLK_APMIXED_ETH2PLL>;
 310                 clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2",
 311                                 "fe", "sgmii_tx250m", "sgmii_rx250m",
 312                                 "sgmii_cdr_ref", "sgmii_cdr_fb",
 313                                 "sgmii2_tx250m", "sgmii2_rx250m",
 314                                 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
 315                                 "sgmii_ck", "eth2pll";
 316                 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
 317                                   <&topckgen CLK_TOP_F10M_REF_SEL>;
 318                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
 319                                          <&topckgen CLK_TOP_SGMIIPLL_D2>;
 320                 power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
 321                 resets = <&ethsys ETHSYS_FE_RST>;
 322                 reset-names = "fe";
 323                 mediatek,ethsys = <&ethsys>;
 324                 mediatek,sgmiisys = <&sgmiisys0>;
 325                 mediatek,infracfg = <&infracfg>;
 326                 #address-cells = <1>;
 327                 #size-cells = <0>;
 328                 status = "disabled";
 329         };
 330
 331         sgmiisys0: syscon@1b128000 {
 332                 compatible = "mediatek,mt7629-sgmiisys", "syscon";
 333                 reg = <0x1b128000 0x1000>;
 334                 #clock-cells = <1>;
 335         };
 336
 337         sgmiisys1: syscon@1b130000 {
 338                 compatible = "mediatek,mt7629-sgmiisys", "syscon";
 339                 reg = <0x1b130000 0x1000>;
 340                 #clock-cells = <1>;
 341         };
 342
 343         pwm: pwm@11006000 {
 344                 compatible = "mediatek,mt7629-pwm";
 345                 reg = <0x11006000 0x1000>;
 346                 #clock-cells = <1>;
 347                 #pwm-cells = <2>;
 348                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 349                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 350                          <&pericfg CLK_PERI_PWM_PD>,
 351                          <&pericfg CLK_PERI_PWM1_PD>;
 352                 clock-names = "top", "main", "pwm1";
 353                 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
 354                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>;
 355                 status = "disabled";
 356         };
 357
 358 };