2 * Copyright (C) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt7623-clk.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7623-power.h>
14 #include <dt-bindings/reset/mt7623-reset.h>
15 #include "skeleton.dtsi"
18 compatible = "mediatek,mt7623";
19 interrupt-parent = <&sysirq>;
26 enable-method = "mediatek,mt6589-smp";
30 compatible = "arm,cortex-a7";
32 clocks = <&infracfg CLK_INFRA_CPUSEL>,
33 <&apmixedsys CLK_APMIXED_MAINPLL>;
34 clock-names = "cpu", "intermediate";
35 clock-frequency = <1300000000>;
40 compatible = "arm,cortex-a7";
42 clocks = <&infracfg CLK_INFRA_CPUSEL>,
43 <&apmixedsys CLK_APMIXED_MAINPLL>;
44 clock-names = "cpu", "intermediate";
45 clock-frequency = <1300000000>;
50 compatible = "arm,cortex-a7";
52 clocks = <&infracfg CLK_INFRA_CPUSEL>,
53 <&apmixedsys CLK_APMIXED_MAINPLL>;
54 clock-names = "cpu", "intermediate";
55 clock-frequency = <1300000000>;
60 compatible = "arm,cortex-a7";
62 clocks = <&infracfg CLK_INFRA_CPUSEL>,
63 <&apmixedsys CLK_APMIXED_MAINPLL>;
64 clock-names = "cpu", "intermediate";
65 clock-frequency = <1300000000>;
69 system_clk: dummy13m {
70 compatible = "fixed-clock";
71 clock-frequency = <13000000>;
75 rtc32k: oscillator-1 {
76 compatible = "fixed-clock";
78 clock-frequency = <32000>;
79 clock-output-names = "rtc32k";
82 clk26m: oscillator-0 {
83 compatible = "fixed-clock";
85 clock-frequency = <26000000>;
86 clock-output-names = "clk26m";
90 compatible = "arm,armv7-timer";
91 interrupt-parent = <&gic>;
92 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
93 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
94 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
95 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
96 clock-frequency = <13000000>;
97 arm,cpu-registers-not-fw-configured;
100 topckgen: clock-controller@10000000 {
101 compatible = "mediatek,mt7623-topckgen";
102 reg = <0x10000000 0x1000>;
106 infracfg: syscon@10001000 {
107 compatible = "mediatek,mt7623-infracfg", "syscon";
108 reg = <0x10001000 0x1000>;
112 pericfg: syscon@10003000 {
113 compatible = "mediatek,mt7623-pericfg", "syscon";
114 reg = <0x10003000 0x1000>;
118 pinctrl: pinctrl@10005000 {
119 compatible = "mediatek,mt7623-pinctrl";
120 reg = <0x10005000 0x1000>;
122 gpio: gpio-controller {
128 scpsys: scpsys@10006000 {
129 compatible = "mediatek,mt7623-scpsys";
130 #power-domain-cells = <1>;
131 reg = <0x10006000 0x1000>;
132 infracfg = <&infracfg>;
133 clocks = <&topckgen CLK_TOP_MM_SEL>,
134 <&topckgen CLK_TOP_MFG_SEL>,
135 <&topckgen CLK_TOP_ETHIF_SEL>;
136 clock-names = "mm", "mfg", "ethif";
139 watchdog: watchdog@10007000 {
140 compatible = "mediatek,wdt";
141 reg = <0x10007000 0x100>;
145 compatible = "wdt-reboot";
149 timer0: timer@10008000 {
150 compatible = "mediatek,timer";
151 reg = <0x10008000 0x80>;
152 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
153 clocks = <&system_clk>;
154 clock-names = "system-clk";
157 sysirq: interrupt-controller@10200100 {
158 compatible = "mediatek,sysirq";
159 interrupt-controller;
160 #interrupt-cells = <3>;
161 interrupt-parent = <&gic>;
162 reg = <0x10200100 0x1c>;
165 apmixedsys: clock-controller@10209000 {
166 compatible = "mediatek,mt7623-apmixedsys";
167 reg = <0x10209000 0x1000>;
171 gic: interrupt-controller@10211000 {
172 compatible = "arm,cortex-a7-gic";
173 interrupt-controller;
174 #interrupt-cells = <3>;
175 interrupt-parent = <&gic>;
176 reg = <0x10211000 0x1000>,
182 uart0: serial@11002000 {
183 compatible = "mediatek,hsuart";
184 reg = <0x11002000 0x400>;
186 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
187 clocks = <&topckgen CLK_TOP_UART_SEL>,
188 <&pericfg CLK_PERI_UART0>;
189 clock-names = "baud", "bus";
193 uart1: serial@11003000 {
194 compatible = "mediatek,hsuart";
195 reg = <0x11003000 0x400>;
197 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
198 clocks = <&topckgen CLK_TOP_UART_SEL>,
199 <&pericfg CLK_PERI_UART1>;
200 clock-names = "baud", "bus";
204 uart2: serial@11004000 {
205 compatible = "mediatek,hsuart";
206 reg = <0x11004000 0x400>;
208 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
209 clocks = <&topckgen CLK_TOP_UART_SEL>,
210 <&pericfg CLK_PERI_UART2>;
211 clock-names = "baud", "bus";
215 uart3: serial@11005000 {
216 compatible = "mediatek,hsuart";
217 reg = <0x11005000 0x400>;
219 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
220 clocks = <&topckgen CLK_TOP_UART_SEL>,
221 <&pericfg CLK_PERI_UART3>;
222 clock-names = "baud", "bus";
227 compatible = "mediatek,mt7623-mmc";
228 reg = <0x11230000 0x1000>;
229 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
230 clocks = <&pericfg CLK_PERI_MSDC30_0>,
231 <&topckgen CLK_TOP_MSDC30_0_SEL>;
232 clock-names = "source", "hclk";
237 compatible = "mediatek,mt7623-mmc";
238 reg = <0x11240000 0x1000>;
239 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
240 clocks = <&pericfg CLK_PERI_MSDC30_1>,
241 <&topckgen CLK_TOP_MSDC30_1_SEL>;
242 clock-names = "source", "hclk";
246 hifsys: syscon@1a000000 {
247 compatible = "mediatek,mt7623-hifsys", "syscon";
248 reg = <0x1a000000 0x1000>;
253 pcie: pcie@1a140000 {
254 compatible = "mediatek,mt7623-pcie";
256 reg = <0x1a140000 0x1000>, /* PCIe shared registers */
257 <0x1a142000 0x1000>, /* Port0 registers */
258 <0x1a143000 0x1000>, /* Port1 registers */
259 <0x1a144000 0x1000>; /* Port2 registers */
260 reg-names = "subsys", "port0", "port1", "port2";
261 #address-cells = <3>;
263 #interrupt-cells = <1>;
264 interrupt-map-mask = <0xf800 0 0 0>;
265 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
266 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
267 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
268 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
269 <&hifsys CLK_HIFSYS_PCIE0>,
270 <&hifsys CLK_HIFSYS_PCIE1>,
271 <&hifsys CLK_HIFSYS_PCIE2>;
272 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
273 resets = <&hifsys HIFSYS_PCIE0_RST>,
274 <&hifsys HIFSYS_PCIE1_RST>,
275 <&hifsys HIFSYS_PCIE2_RST>;
276 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
277 phys = <&pcie0_port PHY_TYPE_PCIE>,
278 <&pcie1_port PHY_TYPE_PCIE>,
279 <&u3port1 PHY_TYPE_PCIE>;
280 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
281 power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
282 bus-range = <0x00 0xff>;
284 ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000
285 0x83000000 0 0x60000000 0x60000000 0 0x10000000>;
288 reg = <0x0000 0 0 0 0>;
289 #address-cells = <3>;
291 #interrupt-cells = <1>;
292 interrupt-map-mask = <0 0 0 0>;
293 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
299 reg = <0x0800 0 0 0 0>;
300 #address-cells = <3>;
302 #interrupt-cells = <1>;
303 interrupt-map-mask = <0 0 0 0>;
304 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
310 reg = <0x1000 0 0 0 0>;
311 #address-cells = <3>;
313 #interrupt-cells = <1>;
314 interrupt-map-mask = <0 0 0 0>;
315 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
321 pcie0_phy: pcie-phy@1a149000 {
322 compatible = "mediatek,generic-tphy-v1";
323 reg = <0x1a149000 0x0700>;
324 #address-cells = <1>;
329 pcie0_port: pcie-phy@1a149900 {
330 reg = <0x1a149900 0x0700>;
338 pcie1_phy: pcie-phy@1a14a000 {
339 compatible = "mediatek,generic-tphy-v1";
340 reg = <0x1a14a000 0x0700>;
341 #address-cells = <1>;
346 pcie1_port: pcie-phy@1a14a900 {
347 reg = <0x1a14a900 0x0700>;
355 u3phy2: usb-phy@1a244000 {
356 compatible = "mediatek,generic-tphy-v1";
357 reg = <0x1a244000 0x0700>;
358 #address-cells = <1>;
363 u2port1: usb-phy@1a244800 {
364 reg = <0x1a244800 0x0100>;
365 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
371 u3port1: usb-phy@1a244900 {
372 reg = <0x1a244900 0x0700>;
380 ethsys: syscon@1b000000 {
381 compatible = "mediatek,mt7623-ethsys", "syscon";
382 reg = <0x1b000000 0x1000>;
387 eth: ethernet@1b100000 {
388 compatible = "mediatek,mt7623-eth", "syscon";
389 reg = <0x1b100000 0x20000>;
390 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
391 <ðsys CLK_ETHSYS_ESW>,
392 <ðsys CLK_ETHSYS_GP1>,
393 <ðsys CLK_ETHSYS_GP2>,
394 <&apmixedsys CLK_APMIXED_TRGPLL>;
395 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
396 power-domains = <&scpsys MT7623_POWER_DOMAIN_ETH>;
397 resets = <ðsys ETHSYS_FE_RST>,
398 <ðsys ETHSYS_MCM_RST>;
399 reset-names = "fe", "mcm";
400 mediatek,ethsys = <ðsys>;
405 compatible = "mediatek,mt7623-pwm";
406 reg = <0x11006000 0x1000>;
409 clocks = <&topckgen CLK_TOP_PWM_SEL>,
410 <&pericfg CLK_PERI_PWM>,
411 <&pericfg CLK_PERI_PWM1>,
412 <&pericfg CLK_PERI_PWM2>,
413 <&pericfg CLK_PERI_PWM3>,
414 <&pericfg CLK_PERI_PWM4>,
415 <&pericfg CLK_PERI_PWM5>;
416 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",