arch/arm/dts/mt7622.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019 MediaTek Inc.
   4  * Author: Sam Shih <sam.shih@mediatek.com>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/mt7622-clk.h>
  10 #include <dt-bindings/power/mt7629-power.h>
  11 #include <dt-bindings/reset/mt7629-reset.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14 / {
  15         compatible = "mediatek,mt7622";
  16         interrupt-parent = <&sysirq>;
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a53";
  27                         reg = <0x0>;
  28                         clock-frequency = <1300000000>;
  29                 };
  30
  31                 cpu1: cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a53";
  34                         reg = <0x1>;
  35                         clock-frequency = <1300000000>;
  36                 };
  37         };
  38
  39         snfi: snfi@1100d000 {
  40                 compatible = "mediatek,mtk-snfi-spi";
  41                 reg = <0x1100d000 0x2000>;
  42                 clocks = <&pericfg CLK_PERI_NFI_PD>,
  43                          <&pericfg CLK_PERI_SNFI_PD>;
  44                 clock-names = "nfi_clk", "pad_clk";
  45                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
  46                                   <&topckgen CLK_TOP_NFI_INFRA_SEL>;
  47
  48                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
  49                                          <&topckgen CLK_TOP_UNIVPLL2_D8>;
  50                 status = "disabled";
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53         };
  54
  55         timer {
  56                 compatible = "arm,armv8-timer";
  57                 interrupt-parent = <&gic>;
  58                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  59                               IRQ_TYPE_LEVEL_HIGH)>,
  60                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  61                               IRQ_TYPE_LEVEL_HIGH)>,
  62                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
  63                               IRQ_TYPE_LEVEL_HIGH)>,
  64                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  65                               IRQ_TYPE_LEVEL_HIGH)>;
  66                 arm,cpu-registers-not-fw-configured;
  67         };
  68
  69         timer0: timer@10004000 {
  70                 compatible = "mediatek,timer";
  71                 reg = <0x10004000 0x80>;
  72                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
  73                 clocks = <&system_clk>;
  74                 clock-names = "system-clk";
  75         };
  76
  77         system_clk: dummy13m {
  78                 compatible = "fixed-clock";
  79                 clock-frequency = <13000000>;
  80                 #clock-cells = <0>;
  81         };
  82
  83         infracfg: infracfg@10000000 {
  84                 compatible = "mediatek,mt7622-infracfg",
  85                              "syscon";
  86                 reg = <0x10000000 0x1000>;
  87                 #clock-cells = <1>;
  88                 #reset-cells = <1>;
  89         };
  90
  91         pericfg: pericfg@10002000 {
  92                 compatible = "mediatek,mt7622-pericfg", "syscon";
  93                 reg = <0x10002000 0x1000>;
  94                 #clock-cells = <1>;
  95         };
  96
  97         scpsys: scpsys@10006000 {
  98                 compatible = "mediatek,mt7622-scpsys",
  99                              "syscon";
 100                 #power-domain-cells = <1>;
 101                 reg = <0x10006000 0x1000>;
 102                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
 103                              <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
 104                              <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
 105                              <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
 106                 infracfg = <&infracfg>;
 107                 clocks = <&topckgen CLK_TOP_HIF_SEL>;
 108                 clock-names = "hif_sel";
 109         };
 110
 111         sysirq: interrupt-controller@10200620 {
 112                 compatible = "mediatek,sysirq";
 113                 reg = <0x10200620 0x20>;
 114                 interrupt-controller;
 115                 #interrupt-cells = <3>;
 116                 interrupt-parent = <&gic>;
 117         };
 118
 119         apmixedsys: apmixedsys@10209000 {
 120                 compatible = "mediatek,mt7622-apmixedsys";
 121                 reg = <0x10209000 0x1000>;
 122                 #clock-cells = <1>;
 123         };
 124
 125         topckgen: topckgen@10210000 {
 126                 compatible = "mediatek,mt7622-topckgen";
 127                 reg = <0x10210000 0x1000>;
 128                 #clock-cells = <1>;
 129         };
 130
 131         pinctrl: pinctrl@10211000 {
 132                 compatible = "mediatek,mt7622-pinctrl";
 133                 reg = <0x10211000 0x1000>;
 134                 gpio: gpio-controller {
 135                         gpio-controller;
 136                         #gpio-cells = <2>;
 137                 };
 138         };
 139
 140         watchdog: watchdog@10212000 {
 141                 compatible = "mediatek,wdt";
 142                 reg = <0x10212000 0x800>;
 143         };
 144
 145         gic: interrupt-controller@10300000 {
 146                 compatible = "arm,gic-400";
 147                 interrupt-controller;
 148                 #interrupt-cells = <3>;
 149                 interrupt-parent = <&gic>;
 150                 reg = <0x10310000 0x1000>,
 151                       <0x10320000 0x1000>,
 152                       <0x10340000 0x2000>,
 153                       <0x10360000 0x2000>;
 154         };
 155
 156         uart0: serial@11002000 {
 157                 compatible = "mediatek,hsuart";
 158                 reg = <0x11002000 0x400>;
 159                 reg-shift = <2>;
 160                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 161                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 162                          <&pericfg CLK_PERI_UART0_PD>;
 163                 clock-names = "baud", "bus";
 164                 status = "disabled";
 165                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 166                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 167         };
 168
 169         mmc0: mmc@11230000 {
 170                 compatible = "mediatek,mt7622-mmc";
 171                 reg = <0x11230000 0x1000>;
 172                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 173                 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
 174                          <&topckgen CLK_TOP_MSDC50_0_SEL>;
 175                 clock-names = "source", "hclk";
 176                 status = "disabled";
 177         };
 178
 179         mmc1: mmc@11240000 {
 180                 compatible = "mediatek,mt7622-mmc";
 181                 reg = <0x11240000 0x1000>;
 182                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 183                 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
 184                          <&topckgen CLK_TOP_AXI_SEL>;
 185                 clock-names = "source", "hclk";
 186                 status = "disabled";
 187         };
 188
 189         ethsys: syscon@1b000000 {
 190                 compatible = "mediatek,mt7622-ethsys", "syscon";
 191                 reg = <0x1b000000 0x1000>;
 192                 #clock-cells = <1>;
 193                 #reset-cells = <1>;
 194         };
 195
 196         eth: ethernet@1b100000 {
 197                 compatible = "mediatek,mt7622-eth", "syscon";
 198                 reg = <0x1b100000 0x20000>;
 199                 clocks = <&topckgen CLK_TOP_ETH_SEL>,
 200                          <&ethsys CLK_ETH_ESW_EN>,
 201                          <&ethsys CLK_ETH_GP0_EN>,
 202                          <&ethsys CLK_ETH_GP1_EN>,
 203                          <&ethsys CLK_ETH_GP2_EN>,
 204                          <&sgmiisys CLK_SGMII_TX250M_EN>,
 205                          <&sgmiisys CLK_SGMII_RX250M_EN>,
 206                          <&sgmiisys CLK_SGMII_CDR_REF>,
 207                          <&sgmiisys CLK_SGMII_CDR_FB>,
 208                          <&topckgen CLK_TOP_SGMIIPLL>,
 209                          <&apmixedsys CLK_APMIXED_ETH2PLL>;
 210                 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
 211                               "sgmii_tx250m", "sgmii_rx250m",
 212                               "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
 213                               "eth2pll";
 214                 power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
 215                 resets = <&ethsys ETHSYS_FE_RST>;
 216                 reset-names = "fe";
 217                 mediatek,ethsys = <&ethsys>;
 218                 mediatek,sgmiisys = <&sgmiisys>;
 219                 #address-cells = <1>;
 220                 #size-cells = <0>;
 221                 status = "disabled";
 222         };
 223
 224         sgmiisys: sgmiisys@1b128000 {
 225                 compatible = "mediatek,mt7622-sgmiisys", "syscon";
 226                 reg = <0x1b128000 0x3000>;
 227                 #clock-cells = <1>;
 228         };
 229
 230         pwm: pwm@11006000 {
 231                 compatible = "mediatek,mt7622-pwm";
 232                 reg = <0x11006000 0x1000>;
 233                 #clock-cells = <1>;
 234                 #pwm-cells = <2>;
 235                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 236                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 237                          <&pericfg CLK_PERI_PWM_PD>,
 238                          <&pericfg CLK_PERI_PWM1_PD>,
 239                          <&pericfg CLK_PERI_PWM2_PD>,
 240                          <&pericfg CLK_PERI_PWM3_PD>,
 241                          <&pericfg CLK_PERI_PWM4_PD>,
 242                          <&pericfg CLK_PERI_PWM5_PD>,
 243                          <&pericfg CLK_PERI_PWM6_PD>;
 244                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
 245                               "pwm5", "pwm6";
 246                 status = "disabled";
 247         };
 248
 249 };