arch/arm/dts/mt7622.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019 MediaTek Inc.
   4  * Author: Sam Shih <sam.shih@mediatek.com>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/mt7622-clk.h>
  10
  11 / {
  12         compatible = "mediatek,mt7622";
  13         interrupt-parent = <&sysirq>;
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a53";
  24                         reg = <0x0>;
  25                         clock-frequency = <1300000000>;
  26                 };
  27
  28                 cpu1: cpu@1 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a53";
  31                         reg = <0x1>;
  32                         clock-frequency = <1300000000>;
  33                 };
  34         };
  35
  36         snfi: snfi@1100d000 {
  37                 compatible = "mediatek,mtk-snfi-spi";
  38                 reg = <0x1100d000 0x2000>;
  39                 clocks = <&pericfg CLK_PERI_NFI_PD>,
  40                          <&pericfg CLK_PERI_SNFI_PD>;
  41                 clock-names = "nfi_clk", "pad_clk";
  42                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
  43                                   <&topckgen CLK_TOP_NFI_INFRA_SEL>;
  44
  45                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
  46                                          <&topckgen CLK_TOP_UNIVPLL2_D8>;
  47                 status = "disabled";
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50         };
  51
  52         timer {
  53                 compatible = "arm,armv8-timer";
  54                 interrupt-parent = <&gic>;
  55                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  56                               IRQ_TYPE_LEVEL_HIGH)>,
  57                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  58                               IRQ_TYPE_LEVEL_HIGH)>,
  59                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
  60                               IRQ_TYPE_LEVEL_HIGH)>,
  61                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  62                               IRQ_TYPE_LEVEL_HIGH)>;
  63                 arm,cpu-registers-not-fw-configured;
  64         };
  65
  66         timer0: timer@10004000 {
  67                 compatible = "mediatek,timer";
  68                 reg = <0x10004000 0x80>;
  69                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
  70                 clocks = <&system_clk>;
  71                 clock-names = "system-clk";
  72         };
  73
  74         system_clk: dummy13m {
  75                 compatible = "fixed-clock";
  76                 clock-frequency = <13000000>;
  77                 #clock-cells = <0>;
  78         };
  79
  80         infracfg: infracfg@10000000 {
  81                 compatible = "mediatek,mt7622-infracfg",
  82                              "syscon";
  83                 reg = <0x10000000 0x1000>;
  84                 #clock-cells = <1>;
  85                 #reset-cells = <1>;
  86         };
  87
  88         pericfg: pericfg@10002000 {
  89                 compatible = "mediatek,mt7622-pericfg", "syscon";
  90                 reg = <0x10002000 0x1000>;
  91                 #clock-cells = <1>;
  92         };
  93
  94         scpsys: scpsys@10006000 {
  95                 compatible = "mediatek,mt7622-scpsys",
  96                              "syscon";
  97                 #power-domain-cells = <1>;
  98                 reg = <0x10006000 0x1000>;
  99                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
 100                              <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
 101                              <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
 102                              <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
 103                 infracfg = <&infracfg>;
 104                 clocks = <&topckgen CLK_TOP_HIF_SEL>;
 105                 clock-names = "hif_sel";
 106         };
 107
 108         sysirq: interrupt-controller@10200620 {
 109                 compatible = "mediatek,sysirq";
 110                 reg = <0x10200620 0x20>;
 111                 interrupt-controller;
 112                 #interrupt-cells = <3>;
 113                 interrupt-parent = <&gic>;
 114         };
 115
 116         apmixedsys: apmixedsys@10209000 {
 117                 compatible = "mediatek,mt7622-apmixedsys";
 118                 reg = <0x10209000 0x1000>;
 119                 #clock-cells = <1>;
 120         };
 121
 122         topckgen: topckgen@10210000 {
 123                 compatible = "mediatek,mt7622-topckgen";
 124                 reg = <0x10210000 0x1000>;
 125                 #clock-cells = <1>;
 126         };
 127
 128         pinctrl: pinctrl@10211000 {
 129                 compatible = "mediatek,mt7622-pinctrl";
 130                 reg = <0x10211000 0x1000>;
 131                 gpio: gpio-controller {
 132                         gpio-controller;
 133                         #gpio-cells = <2>;
 134                 };
 135         };
 136
 137         watchdog: watchdog@10212000 {
 138                 compatible = "mediatek,wdt";
 139                 reg = <0x10212000 0x800>;
 140         };
 141
 142         gic: interrupt-controller@10300000 {
 143                 compatible = "arm,gic-400";
 144                 interrupt-controller;
 145                 #interrupt-cells = <3>;
 146                 interrupt-parent = <&gic>;
 147                 reg = <0x10310000 0x1000>,
 148                       <0x10320000 0x1000>,
 149                       <0x10340000 0x2000>,
 150                       <0x10360000 0x2000>;
 151         };
 152
 153         uart0: serial@11002000 {
 154                 compatible = "mediatek,hsuart";
 155                 reg = <0x11002000 0x400>;
 156                 reg-shift = <2>;
 157                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 158                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 159                          <&pericfg CLK_PERI_UART0_PD>;
 160                 clock-names = "baud", "bus";
 161                 status = "disabled";
 162                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 163                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 164         };
 165
 166         mmc0: mmc@11230000 {
 167                 compatible = "mediatek,mt7622-mmc";
 168                 reg = <0x11230000 0x1000>;
 169                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 170                 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
 171                          <&topckgen CLK_TOP_MSDC50_0_SEL>;
 172                 clock-names = "source", "hclk";
 173                 status = "disabled";
 174         };
 175
 176         mmc1: mmc@11240000 {
 177                 compatible = "mediatek,mt7622-mmc";
 178                 reg = <0x11240000 0x1000>;
 179                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 180                 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
 181                          <&topckgen CLK_TOP_AXI_SEL>;
 182                 clock-names = "source", "hclk";
 183                 status = "disabled";
 184         };
 185 };