arch/arm/dts/mt7622.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019 MediaTek Inc.
   4  * Author: Sam Shih <sam.shih@mediatek.com>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/mt7622-clk.h>
  10 #include <dt-bindings/power/mt7629-power.h>
  11 #include <dt-bindings/reset/mt7629-reset.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/phy/phy.h>
  14
  15 / {
  16         compatible = "mediatek,mt7622";
  17         interrupt-parent = <&sysirq>;
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu0: cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a53";
  28                         reg = <0x0>;
  29                         clock-frequency = <1300000000>;
  30                 };
  31
  32                 cpu1: cpu@1 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a53";
  35                         reg = <0x1>;
  36                         clock-frequency = <1300000000>;
  37                 };
  38         };
  39
  40         snfi: snfi@1100d000 {
  41                 compatible = "mediatek,mtk-snfi-spi";
  42                 reg = <0x1100d000 0x2000>;
  43                 clocks = <&pericfg CLK_PERI_NFI_PD>,
  44                          <&pericfg CLK_PERI_SNFI_PD>;
  45                 clock-names = "nfi_clk", "pad_clk";
  46                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
  47                                   <&topckgen CLK_TOP_NFI_INFRA_SEL>;
  48
  49                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
  50                                          <&topckgen CLK_TOP_UNIVPLL2_D8>;
  51                 status = "disabled";
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54         };
  55
  56         snor: snor@11014000 {
  57                 compatible = "mediatek,mtk-snor";
  58                 reg = <0x11014000 0x1000>;
  59                 clocks = <&pericfg CLK_PERI_FLASH_PD>,
  60                          <&topckgen CLK_TOP_FLASH_SEL>;
  61                 clock-names = "spi", "sf";
  62                 status = "disabled";
  63                 #address-cells = <1>;
  64                 #size-cells = <0>;
  65         };
  66
  67         timer {
  68                 compatible = "arm,armv8-timer";
  69                 interrupt-parent = <&gic>;
  70                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  71                               IRQ_TYPE_LEVEL_HIGH)>,
  72                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  73                               IRQ_TYPE_LEVEL_HIGH)>,
  74                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
  75                               IRQ_TYPE_LEVEL_HIGH)>,
  76                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  77                               IRQ_TYPE_LEVEL_HIGH)>;
  78                 arm,cpu-registers-not-fw-configured;
  79         };
  80
  81         timer0: timer@10004000 {
  82                 compatible = "mediatek,timer";
  83                 reg = <0x10004000 0x80>;
  84                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
  85                 clocks = <&infracfg CLK_INFRA_APXGPT_PD>;
  86                 clock-names = "system-clk";
  87         };
  88
  89         infracfg: infracfg@10000000 {
  90                 compatible = "mediatek,mt7622-infracfg",
  91                              "syscon";
  92                 reg = <0x10000000 0x1000>;
  93                 #clock-cells = <1>;
  94                 #reset-cells = <1>;
  95         };
  96
  97         pericfg: pericfg@10002000 {
  98                 compatible = "mediatek,mt7622-pericfg", "syscon";
  99                 reg = <0x10002000 0x1000>;
 100                 #clock-cells = <1>;
 101         };
 102
 103         scpsys: scpsys@10006000 {
 104                 compatible = "mediatek,mt7622-scpsys",
 105                              "syscon";
 106                 #power-domain-cells = <1>;
 107                 reg = <0x10006000 0x1000>;
 108                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
 109                              <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
 110                              <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
 111                              <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
 112                 infracfg = <&infracfg>;
 113                 clocks = <&topckgen CLK_TOP_HIF_SEL>;
 114                 clock-names = "hif_sel";
 115         };
 116
 117         sysirq: interrupt-controller@10200620 {
 118                 compatible = "mediatek,sysirq";
 119                 reg = <0x10200620 0x20>;
 120                 interrupt-controller;
 121                 #interrupt-cells = <3>;
 122                 interrupt-parent = <&gic>;
 123         };
 124
 125         apmixedsys: apmixedsys@10209000 {
 126                 compatible = "mediatek,mt7622-apmixedsys";
 127                 reg = <0x10209000 0x1000>;
 128                 #clock-cells = <1>;
 129         };
 130
 131         topckgen: topckgen@10210000 {
 132                 compatible = "mediatek,mt7622-topckgen";
 133                 reg = <0x10210000 0x1000>;
 134                 #clock-cells = <1>;
 135         };
 136
 137         pinctrl: pinctrl@10211000 {
 138                 compatible = "mediatek,mt7622-pinctrl";
 139                 reg = <0x10211000 0x1000>;
 140                 gpio: gpio-controller {
 141                         gpio-controller;
 142                         #gpio-cells = <2>;
 143                 };
 144         };
 145
 146         watchdog: watchdog@10212000 {
 147                 compatible = "mediatek,wdt";
 148                 reg = <0x10212000 0x800>;
 149         };
 150
 151         wdt-reboot {
 152                 compatible = "wdt-reboot";
 153                 wdt = <&watchdog>;
 154         };
 155
 156         gic: interrupt-controller@10300000 {
 157                 compatible = "arm,gic-400";
 158                 interrupt-controller;
 159                 #interrupt-cells = <3>;
 160                 interrupt-parent = <&gic>;
 161                 reg = <0x10310000 0x1000>,
 162                       <0x10320000 0x1000>,
 163                       <0x10340000 0x2000>,
 164                       <0x10360000 0x2000>;
 165         };
 166
 167         uart0: serial@11002000 {
 168                 compatible = "mediatek,hsuart";
 169                 reg = <0x11002000 0x400>;
 170                 reg-shift = <2>;
 171                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 172                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 173                          <&pericfg CLK_PERI_UART0_PD>;
 174                 clock-names = "baud", "bus";
 175                 status = "disabled";
 176                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 177                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 178         };
 179
 180         mmc0: mmc@11230000 {
 181                 compatible = "mediatek,mt7622-mmc";
 182                 reg = <0x11230000 0x1000>;
 183                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 184                 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
 185                          <&topckgen CLK_TOP_MSDC50_0_SEL>;
 186                 clock-names = "source", "hclk";
 187                 status = "disabled";
 188         };
 189
 190         mmc1: mmc@11240000 {
 191                 compatible = "mediatek,mt7622-mmc";
 192                 reg = <0x11240000 0x1000>;
 193                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 194                 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
 195                          <&topckgen CLK_TOP_AXI_SEL>;
 196                 clock-names = "source", "hclk";
 197                 status = "disabled";
 198         };
 199
 200         ssusbsys: ssusbsys@1a000000 {
 201                 compatible = "mediatek,mt7622-ssusbsys",
 202                              "syscon";
 203                 reg = <0x1a000000 0x1000>;
 204                 #clock-cells = <1>;
 205                 #reset-cells = <1>;
 206         };
 207
 208         pciesys: pciesys@1a100800 {
 209                 compatible = "mediatek,mt7622-pciesys", "syscon";
 210                 reg = <0x1a100800 0x1000>;
 211                 #clock-cells = <1>;
 212                 #reset-cells = <1>;
 213         };
 214
 215         pcie: pcie@1a140000 {
 216                 compatible = "mediatek,mt7622-pcie";
 217                 device_type = "pci";
 218                 reg = <0x1a140000 0x1000>,
 219                       <0x1a143000 0x1000>,
 220                       <0x1a145000 0x1000>;
 221                 reg-names = "subsys", "port0", "port1";
 222                 #address-cells = <3>;
 223                 #size-cells = <2>;
 224                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
 225                              <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 226                 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
 227                          <&pciesys CLK_PCIE_P1_MAC_EN>,
 228                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 229                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 230                          <&pciesys CLK_PCIE_P0_AUX_EN>,
 231                          <&pciesys CLK_PCIE_P1_AUX_EN>,
 232                          <&pciesys CLK_PCIE_P0_AXI_EN>,
 233                          <&pciesys CLK_PCIE_P1_AXI_EN>,
 234                          <&pciesys CLK_PCIE_P0_OBFF_EN>,
 235                          <&pciesys CLK_PCIE_P1_OBFF_EN>,
 236                          <&pciesys CLK_PCIE_P0_PIPE_EN>,
 237                          <&pciesys CLK_PCIE_P1_PIPE_EN>;
 238                 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
 239                               "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
 240                               "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
 241                 power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF0>;
 242                 bus-range = <0x00 0xff>;
 243                 ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
 244                 status = "disabled";
 245
 246                 pcie0: pcie@0,0 {
 247                         reg = <0x0000 0 0 0 0>;
 248                         #address-cells = <3>;
 249                         #size-cells = <2>;
 250                         #interrupt-cells = <1>;
 251                         ranges;
 252                         status = "disabled";
 253
 254                         interrupt-map-mask = <0 0 0 7>;
 255                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 256                                         <0 0 0 2 &pcie_intc0 1>,
 257                                         <0 0 0 3 &pcie_intc0 2>,
 258                                         <0 0 0 4 &pcie_intc0 3>;
 259                         pcie_intc0: interrupt-controller {
 260                                 interrupt-controller;
 261                                 #address-cells = <0>;
 262                                 #interrupt-cells = <1>;
 263                         };
 264                 };
 265
 266                 pcie1: pcie@1,0 {
 267                         reg = <0x0800 0 0 0 0>;
 268                         #address-cells = <3>;
 269                         #size-cells = <2>;
 270                         #interrupt-cells = <1>;
 271                         ranges;
 272                         status = "disabled";
 273
 274                         interrupt-map-mask = <0 0 0 7>;
 275                         interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 276                                         <0 0 0 2 &pcie_intc1 1>,
 277                                         <0 0 0 3 &pcie_intc1 2>,
 278                                         <0 0 0 4 &pcie_intc1 3>;
 279                         pcie_intc1: interrupt-controller {
 280                                 interrupt-controller;
 281                                 #address-cells = <0>;
 282                                 #interrupt-cells = <1>;
 283                         };
 284                 };
 285         };
 286
 287         sata: sata@1a200000 {
 288                 compatible = "mediatek,mtk-ahci";
 289                 reg = <0x1a200000 0x1100>;
 290                 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
 291                         <&pciesys MT7622_SATA_PHY_SW_RST>,
 292                         <&pciesys MT7622_SATA_PHY_REG_RST>;
 293                 reset-names = "axi", "sw", "reg";
 294                 mediatek,phy-mode = <&pciesys>;
 295                 ports-implemented = <0x1>;
 296                 phys = <&sata_port PHY_TYPE_SATA>;
 297                 phy-names = "sata-phy";
 298                 status = "okay";
 299         };
 300
 301         sata_phy: sata-phy@1a243000 {
 302                 compatible = "mediatek,generic-tphy-v1";
 303                 reg = <0x1a243000 0x0100>;
 304                 #address-cells = <1>;
 305                 #size-cells = <1>;
 306                 ranges;
 307                 status = "okay";
 308
 309                 sata_port: sata-phy@1a243000 {
 310                         reg = <0x1a243000 0x0100>;
 311                         clocks = <&topckgen CLK_TOP_ETH_500M>;
 312                         clock-names = "ref";
 313                         #phy-cells = <1>;
 314                         status = "okay";
 315                 };
 316         };
 317
 318         ssusb: usb@1a0c0000 {
 319                 compatible = "mediatek,mt7622-xhci",
 320                              "mediatek,mtk-xhci";
 321                 reg = <0x1a0c0000 0x01000>,
 322                       <0x1a0c4700 0x0100>;
 323                 reg-names = "mac", "ippc";
 324                 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
 325                 power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
 326                 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
 327                          <&ssusbsys CLK_SSUSB_REF_EN>,
 328                          <&ssusbsys CLK_SSUSB_MCU_EN>,
 329                          <&ssusbsys CLK_SSUSB_DMA_EN>;
 330                 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
 331                 phys = <&u2port0 PHY_TYPE_USB2>,
 332                        <&u3port0 PHY_TYPE_USB3>,
 333                        <&u2port1 PHY_TYPE_USB2>;
 334                 status = "disabled";
 335         };
 336
 337         u3phy: usb-phy@1a0c4000 {
 338                 compatible = "mediatek,mt7622-u3phy",
 339                              "mediatek,generic-tphy-v1";
 340                 reg = <0x1a0c4000 0x700>;
 341                 #address-cells = <1>;
 342                 #size-cells = <1>;
 343                 ranges;
 344                 status = "disabled";
 345
 346                 u2port0: usb-phy@1a0c4800 {
 347                         reg = <0x1a0c4800 0x0100>;
 348                         #phy-cells = <1>;
 349                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
 350                         clock-names = "ref";
 351                 };
 352
 353                 u3port0: usb-phy@1a0c4900 {
 354                         reg = <0x1a0c4900 0x0700>;
 355                         #phy-cells = <1>;
 356                 };
 357
 358                 u2port1: usb-phy@1a0c5000 {
 359                         reg = <0x1a0c5000 0x0100>;
 360                         #phy-cells = <1>;
 361                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
 362                         clock-names = "ref";
 363                 };
 364         };
 365
 366         ethsys: syscon@1b000000 {
 367                 compatible = "mediatek,mt7622-ethsys", "syscon";
 368                 reg = <0x1b000000 0x1000>;
 369                 #clock-cells = <1>;
 370                 #reset-cells = <1>;
 371         };
 372
 373         eth: ethernet@1b100000 {
 374                 compatible = "mediatek,mt7622-eth", "syscon";
 375                 reg = <0x1b100000 0x20000>;
 376                 clocks = <&topckgen CLK_TOP_ETH_SEL>,
 377                          <&ethsys CLK_ETH_ESW_EN>,
 378                          <&ethsys CLK_ETH_GP0_EN>,
 379                          <&ethsys CLK_ETH_GP1_EN>,
 380                          <&ethsys CLK_ETH_GP2_EN>,
 381                          <&sgmiisys CLK_SGMII_TX250M_EN>,
 382                          <&sgmiisys CLK_SGMII_RX250M_EN>,
 383                          <&sgmiisys CLK_SGMII_CDR_REF>,
 384                          <&sgmiisys CLK_SGMII_CDR_FB>,
 385                          <&topckgen CLK_TOP_SGMIIPLL>,
 386                          <&apmixedsys CLK_APMIXED_ETH2PLL>;
 387                 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
 388                               "sgmii_tx250m", "sgmii_rx250m",
 389                               "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
 390                               "eth2pll";
 391                 power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
 392                 resets = <&ethsys ETHSYS_FE_RST>;
 393                 reset-names = "fe";
 394                 mediatek,ethsys = <&ethsys>;
 395                 mediatek,sgmiisys = <&sgmiisys>;
 396                 #address-cells = <1>;
 397                 #size-cells = <0>;
 398                 status = "disabled";
 399         };
 400
 401         sgmiisys: sgmiisys@1b128000 {
 402                 compatible = "mediatek,mt7622-sgmiisys", "syscon";
 403                 reg = <0x1b128000 0x3000>;
 404                 #clock-cells = <1>;
 405         };
 406
 407         pwm: pwm@11006000 {
 408                 compatible = "mediatek,mt7622-pwm";
 409                 reg = <0x11006000 0x1000>;
 410                 #clock-cells = <1>;
 411                 #pwm-cells = <2>;
 412                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 413                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 414                          <&pericfg CLK_PERI_PWM_PD>,
 415                          <&pericfg CLK_PERI_PWM1_PD>,
 416                          <&pericfg CLK_PERI_PWM2_PD>,
 417                          <&pericfg CLK_PERI_PWM3_PD>,
 418                          <&pericfg CLK_PERI_PWM4_PD>,
 419                          <&pericfg CLK_PERI_PWM5_PD>,
 420                          <&pericfg CLK_PERI_PWM6_PD>;
 421                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
 422                               "pwm5", "pwm6";
 423                 status = "disabled";
 424         };
 425
 426 };