arch/arm/dts/mt7622-rfb.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019 MediaTek Inc.
   4  * Author: Sam Shih <sam.shih@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "mt7622.dtsi"
   9 #include "mt7622-u-boot.dtsi"
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         model = "mt7622-rfb";
  15         compatible = "mediatek,mt7622", "mediatek,mt7622-rfb";
  16         chosen {
  17                 stdout-path = &uart0;
  18                 tick-timer = &timer0;
  19         };
  20
  21         aliases {
  22                 spi0 = &snor;
  23         };
  24
  25         memory@40000000 {
  26                 device_type = "memory";
  27                 reg = <0x40000000 0x10000000>;
  28         };
  29
  30         reg_1p8v: regulator-1p8v {
  31                 compatible = "regulator-fixed";
  32                 regulator-name = "fixed-1.8V";
  33                 regulator-min-microvolt = <1800000>;
  34                 regulator-max-microvolt = <1800000>;
  35                 regulator-boot-on;
  36                 regulator-always-on;
  37         };
  38
  39         reg_3p3v: regulator-3p3v {
  40                 compatible = "regulator-fixed";
  41                 regulator-name = "fixed-3.3V";
  42                 regulator-min-microvolt = <3300000>;
  43                 regulator-max-microvolt = <3300000>;
  44                 regulator-boot-on;
  45                 regulator-always-on;
  46         };
  47 };
  48
  49 &pcie {
  50         pinctrl-names = "default";
  51         pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
  52         status = "okay";
  53
  54         pcie@0,0 {
  55                 status = "okay";
  56         };
  57
  58         pcie@1,0 {
  59                 status = "okay";
  60         };
  61 };
  62
  63 &pinctrl {
  64         pcie0_pins: pcie0-pins {
  65                 mux {
  66                         function = "pcie";
  67                         groups = "pcie0_pad_perst",
  68                                  "pcie0_1_waken",
  69                                  "pcie0_1_clkreq";
  70                 };
  71         };
  72
  73         pcie1_pins: pcie1-pins {
  74                 mux {
  75                         function = "pcie";
  76                         groups = "pcie1_pad_perst",
  77                                  "pcie1_0_waken",
  78                                  "pcie1_0_clkreq";
  79                 };
  80         };
  81
  82         snfi_pins: snfi-pins {
  83                 mux {
  84                         function = "flash";
  85                         groups = "snfi";
  86                 };
  87         };
  88
  89         snor_pins: snor-pins {
  90                 mux {
  91                         function = "flash";
  92                         groups = "spi_nor";
  93                 };
  94         };
  95
  96         uart0_pins: uart0 {
  97                 mux {
  98                         function = "uart";
  99                         groups = "uart0_0_tx_rx" ;
 100                 };
 101         };
 102
 103         watchdog_pins: watchdog-default {
 104                 mux {
 105                         function = "watchdog";
 106                         groups = "watchdog";
 107                 };
 108         };
 109
 110         mmc0_pins_default: mmc0default {
 111                 mux {
 112                         function = "emmc";
 113                         groups =  "emmc";
 114                 };
 115
 116                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 117                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 118                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 119                  */
 120                 conf-cmd-dat {
 121                         pins = "NDL0", "NDL1", "NDL2",
 122                                "NDL3", "NDL4", "NDL5",
 123                                "NDL6", "NDL7", "NRB";
 124                         input-enable;
 125                         bias-pull-up;
 126                 };
 127
 128                 conf-clk {
 129                         pins = "NCLE";
 130                         bias-pull-down;
 131                 };
 132
 133         };
 134
 135         mmc1_pins_default: mmc1default {
 136                 mux {
 137                         function = "sd";
 138                         groups =  "sd_0";
 139                 };
 140                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 141                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 142                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 143                  */
 144                 conf-cmd-data {
 145                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 146                                "I2S2_IN","I2S4_OUT";
 147                         input-enable;
 148                         drive-strength = <8>;
 149                         bias-pull-up;
 150                 };
 151                 conf-clk {
 152                         pins = "I2S3_OUT";
 153                         drive-strength = <12>;
 154                         bias-pull-down;
 155                 };
 156                 conf-cd {
 157                         pins = "TXD3";
 158                         bias-pull-up;
 159                 };
 160
 161         };
 162
 163         i2c1_pins_default: i2c1-default {
 164                 mux {
 165                         function = "i2c";
 166                         groups = "i2c1_0";
 167                 };
 168         };
 169
 170 };
 171
 172 &snfi {
 173         pinctrl-names = "default", "snfi";
 174         pinctrl-0 = <&snor_pins>;
 175         pinctrl-1 = <&snfi_pins>;
 176         status = "disabled";
 177
 178         spi-flash@0{
 179                 compatible = "jedec,spi-nor";
 180                 reg = <0>;
 181                 bootph-all;
 182         };
 183 };
 184
 185 &snor {
 186         pinctrl-names = "default";
 187         pinctrl-0 = <&snor_pins>;
 188         status = "okay";
 189
 190         spi-flash@0{
 191                 compatible = "jedec,spi-nor";
 192                 reg = <0>;
 193                 spi-tx-bus-width = <1>;
 194                 spi-rx-bus-width = <4>;
 195                 bootph-all;
 196         };
 197 };
 198
 199 &uart0 {
 200         status = "okay";
 201 };
 202
 203 &mmc0 {
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&mmc0_pins_default>;
 206         status = "okay";
 207         bus-width = <8>;
 208         max-frequency = <50000000>;
 209         cap-sd-highspeed;
 210         vmmc-supply = <&reg_3p3v>;
 211         vqmmc-supply = <&reg_3p3v>;
 212         non-removable;
 213 };
 214
 215 &mmc1 {
 216         pinctrl-names = "default";
 217         pinctrl-0 = <&mmc1_pins_default>;
 218         status = "okay";
 219         bus-width = <4>;
 220         max-frequency = <50000000>;
 221         cap-sd-highspeed;
 222         r_smpl = <1>;
 223         vmmc-supply = <&reg_3p3v>;
 224         vqmmc-supply = <&reg_3p3v>;
 225 };
 226
 227 &watchdog {
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&watchdog_pins>;
 230         status = "okay";
 231 };
 232
 233 &eth {
 234         status = "okay";
 235         mediatek,gmac-id = <0>;
 236         phy-mode = "2500base-x";
 237         mediatek,switch = "mt7531";
 238         reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
 239
 240         fixed-link {
 241                 speed = <2500>;
 242                 full-duplex;
 243         };
 244 };
 245
 246 &ssusb {
 247         status = "okay";
 248 };
 249
 250 &u3phy {
 251        status = "okay";
 252 };
 253
 254 &soft_i2c {
 255         status = "disabled";
 256 };
 257
 258 &i2c1 {
 259         pinctrl-names = "default";
 260         pinctrl-0 = <&i2c1_pins_default>;
 261         status = "okay";
 262 };