arch/arm/dts/mt7622-rfb.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019 MediaTek Inc.
   4  * Author: Sam Shih <sam.shih@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "mt7622.dtsi"
   9 #include "mt7622-u-boot.dtsi"
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         model = "mt7622-rfb";
  15         compatible = "mediatek,mt7622", "mediatek,mt7622-rfb";
  16         chosen {
  17                 stdout-path = &uart0;
  18                 tick-timer = &timer0;
  19         };
  20
  21         aliases {
  22                 spi0 = &snfi;
  23         };
  24
  25         memory@40000000 {
  26                 device_type = "memory";
  27                 reg = <0x40000000 0x10000000>;
  28         };
  29
  30         reg_1p8v: regulator-1p8v {
  31                 compatible = "regulator-fixed";
  32                 regulator-name = "fixed-1.8V";
  33                 regulator-min-microvolt = <1800000>;
  34                 regulator-max-microvolt = <1800000>;
  35                 regulator-boot-on;
  36                 regulator-always-on;
  37         };
  38
  39         reg_3p3v: regulator-3p3v {
  40                 compatible = "regulator-fixed";
  41                 regulator-name = "fixed-3.3V";
  42                 regulator-min-microvolt = <3300000>;
  43                 regulator-max-microvolt = <3300000>;
  44                 regulator-boot-on;
  45                 regulator-always-on;
  46         };
  47 };
  48
  49
  50 &pinctrl {
  51         snfi_pins: snfi-pins {
  52                 mux {
  53                         function = "flash";
  54                         groups = "snfi";
  55                 };
  56         };
  57
  58         snor_pins: snor-pins {
  59                 mux {
  60                         function = "flash";
  61                         groups = "spi_nor";
  62                 };
  63         };
  64
  65         uart0_pins: uart0 {
  66                 mux {
  67                         function = "uart";
  68                         groups = "uart0_0_tx_rx" ;
  69                 };
  70         };
  71
  72         watchdog_pins: watchdog-default {
  73                 mux {
  74                         function = "watchdog";
  75                         groups = "watchdog";
  76                 };
  77         };
  78
  79         mmc0_pins_default: mmc0default {
  80                 mux {
  81                         function = "emmc";
  82                         groups =  "emmc";
  83                 };
  84
  85                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
  86                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
  87                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
  88                  */
  89                 conf-cmd-dat {
  90                         pins = "NDL0", "NDL1", "NDL2",
  91                                "NDL3", "NDL4", "NDL5",
  92                                "NDL6", "NDL7", "NRB";
  93                         input-enable;
  94                         bias-pull-up;
  95                 };
  96
  97                 conf-clk {
  98                         pins = "NCLE";
  99                         bias-pull-down;
 100                 };
 101
 102         };
 103
 104         mmc1_pins_default: mmc1default {
 105                 mux {
 106                         function = "sd";
 107                         groups =  "sd_0";
 108                 };
 109                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 110                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 111                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 112                  */
 113                 conf-cmd-data {
 114                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 115                                "I2S2_IN","I2S4_OUT";
 116                         input-enable;
 117                         drive-strength = <8>;
 118                         bias-pull-up;
 119                 };
 120                 conf-clk {
 121                         pins = "I2S3_OUT";
 122                         drive-strength = <12>;
 123                         bias-pull-down;
 124                 };
 125                 conf-cd {
 126                         pins = "TXD3";
 127                         bias-pull-up;
 128                 };
 129
 130         };
 131 };
 132
 133 &snfi {
 134         pinctrl-names = "default", "snfi";
 135         pinctrl-0 = <&snor_pins>;
 136         pinctrl-1 = <&snfi_pins>;
 137         status = "okay";
 138
 139         spi-flash@0{
 140                 compatible = "jedec,spi-nor";
 141                 reg = <0>;
 142                 u-boot,dm-pre-reloc;
 143         };
 144 };
 145
 146 &uart0 {
 147         pinctrl-names = "default";
 148         pinctrl-0 = <&uart0_pins>;
 149         status = "okay";
 150 };
 151
 152 &mmc0 {
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&mmc0_pins_default>;
 155         status = "okay";
 156         bus-width = <8>;
 157         max-frequency = <50000000>;
 158         cap-sd-highspeed;
 159         vmmc-supply = <&reg_3p3v>;
 160         vqmmc-supply = <&reg_3p3v>;
 161         non-removable;
 162 };
 163
 164 &mmc1 {
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&mmc1_pins_default>;
 167         status = "okay";
 168         bus-width = <4>;
 169         max-frequency = <50000000>;
 170         cap-sd-highspeed;
 171         r_smpl = <1>;
 172         vmmc-supply = <&reg_3p3v>;
 173         vqmmc-supply = <&reg_3p3v>;
 174 };
 175
 176 &watchdog {
 177         pinctrl-names = "default";
 178         pinctrl-0 = <&watchdog_pins>;
 179         status = "okay";
 180 };
 181
 182 &eth {
 183         status = "okay";
 184         mediatek,gmac-id = <0>;
 185         phy-mode = "sgmii";
 186         mediatek,switch = "mt7531";
 187         reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
 188
 189         fixed-link {
 190                 speed = <1000>;
 191                 full-duplex;
 192         };
 193 };