arch/arm/dts/mt7622-bananapi-bpi-r64.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019 MediaTek Inc.
   4  * Author: Sam Shih <sam.shih@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "mt7622.dtsi"
   9 #include "mt7622-u-boot.dtsi"
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         model = "mt7622-bpi-r64";
  15         compatible = "mediatek,mt7622", "mediatek,mt7622-rfb";
  16         chosen {
  17                 stdout-path = &uart0;
  18                 tick-timer = &timer0;
  19         };
  20
  21         aliases {
  22                 spi0 = &snfi;
  23         };
  24
  25         memory@40000000 {
  26                 device_type = "memory";
  27                 reg = <0x40000000 0x40000000>;
  28         };
  29
  30         reg_1p8v: regulator-1p8v {
  31                 compatible = "regulator-fixed";
  32                 regulator-name = "fixed-1.8V";
  33                 regulator-min-microvolt = <1800000>;
  34                 regulator-max-microvolt = <1800000>;
  35                 regulator-boot-on;
  36                 regulator-always-on;
  37         };
  38
  39         reg_3p3v: regulator-3p3v {
  40                 compatible = "regulator-fixed";
  41                 regulator-name = "fixed-3.3V";
  42                 regulator-min-microvolt = <3300000>;
  43                 regulator-max-microvolt = <3300000>;
  44                 regulator-boot-on;
  45                 regulator-always-on;
  46         };
  47 };
  48
  49 &pcie {
  50         pinctrl-names = "default";
  51         pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
  52         status = "okay";
  53
  54         pcie@0,0 {
  55                 status = "okay";
  56         };
  57
  58         pcie@1,0 {
  59                 status = "okay";
  60         };
  61 };
  62
  63 &pinctrl {
  64         pcie0_pins: pcie0-pins {
  65                 mux {
  66                         function = "pcie";
  67                         groups = "pcie0_pad_perst",
  68                                  "pcie0_1_waken",
  69                                  "pcie0_1_clkreq";
  70                 };
  71         };
  72
  73         pcie1_pins: pcie1-pins {
  74                 mux {
  75                         function = "pcie";
  76                         groups = "pcie1_pad_perst",
  77                                  "pcie1_0_waken",
  78                                  "pcie1_0_clkreq";
  79                 };
  80         };
  81
  82         snfi_pins: snfi-pins {
  83                 mux {
  84                         function = "flash";
  85                         groups = "snfi";
  86                 };
  87         };
  88
  89         snor_pins: snor-pins {
  90                 mux {
  91                         function = "flash";
  92                         groups = "spi_nor";
  93                 };
  94         };
  95
  96         uart0_pins: uart0 {
  97                 mux {
  98                         function = "uart";
  99                         groups = "uart0_0_tx_rx" ;
 100                 };
 101         };
 102
 103         pwm_pins: pwm1 {
 104                 mux {
 105                         function = "pwm";
 106                         groups = "pwm_ch1_0" ;
 107                 };
 108         };
 109
 110         watchdog_pins: watchdog-default {
 111                 mux {
 112                         function = "watchdog";
 113                         groups = "watchdog";
 114                 };
 115         };
 116
 117         mmc0_pins_default: mmc0default {
 118                 mux {
 119                         function = "emmc";
 120                         groups =  "emmc";
 121                 };
 122
 123                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 124                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 125                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 126                  */
 127                 conf-cmd-dat {
 128                         pins = "NDL0", "NDL1", "NDL2",
 129                                "NDL3", "NDL4", "NDL5",
 130                                "NDL6", "NDL7", "NRB";
 131                         input-enable;
 132                         bias-pull-up;
 133                 };
 134
 135                 conf-clk {
 136                         pins = "NCLE";
 137                         bias-pull-down;
 138                 };
 139
 140         };
 141
 142         mmc1_pins_default: mmc1default {
 143                 mux {
 144                         function = "sd";
 145                         groups =  "sd_0";
 146                 };
 147                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 148                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 149                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 150                  */
 151                 conf-cmd-data {
 152                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 153                                "I2S2_IN","I2S4_OUT";
 154                         input-enable;
 155                         drive-strength = <8>;
 156                         bias-pull-up;
 157                 };
 158                 conf-clk {
 159                         pins = "I2S3_OUT";
 160                         drive-strength = <12>;
 161                         bias-pull-down;
 162                 };
 163                 conf-cd {
 164                         pins = "TXD3";
 165                         bias-pull-up;
 166                 };
 167
 168         };
 169 };
 170
 171 &snfi {
 172         pinctrl-names = "default", "snfi";
 173         pinctrl-0 = <&snor_pins>;
 174         pinctrl-1 = <&snfi_pins>;
 175         status = "okay";
 176
 177         spi-flash@0{
 178                 compatible = "jedec,spi-nor";
 179                 reg = <0>;
 180                 u-boot,dm-pre-reloc;
 181         };
 182 };
 183
 184 &uart0 {
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&uart0_pins>;
 187         status = "okay";
 188 };
 189
 190 &pwm {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pwm_pins>;
 193         status = "okay";
 194 };
 195
 196 &mmc0 {
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&mmc0_pins_default>;
 199         status = "okay";
 200         bus-width = <8>;
 201         max-frequency = <50000000>;
 202         cap-sd-highspeed;
 203         vmmc-supply = <&reg_3p3v>;
 204         vqmmc-supply = <&reg_3p3v>;
 205         non-removable;
 206 };
 207
 208 &mmc1 {
 209         pinctrl-names = "default";
 210         pinctrl-0 = <&mmc1_pins_default>;
 211         status = "okay";
 212         bus-width = <4>;
 213         max-frequency = <50000000>;
 214         cap-sd-highspeed;
 215         r_smpl = <1>;
 216         vmmc-supply = <&reg_3p3v>;
 217         vqmmc-supply = <&reg_3p3v>;
 218 };
 219
 220 &watchdog {
 221         pinctrl-names = "default";
 222         pinctrl-0 = <&watchdog_pins>;
 223         status = "okay";
 224 };
 225
 226 &eth {
 227         status = "okay";
 228         mediatek,gmac-id = <0>;
 229         phy-mode = "sgmii";
 230         mediatek,switch = "mt7531";
 231         reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
 232
 233         fixed-link {
 234                 speed = <1000>;
 235                 full-duplex;
 236         };
 237 };
 238
 239 &gpio {
 240         /*gpio 90 for setting mode to sata*/
 241         asm_sel {
 242                 gpio-hog;
 243                 gpios = <90 GPIO_ACTIVE_HIGH>;
 244                 output-low;
 245         };
 246 };
 247
 248 &ssusb {
 249         status = "okay";
 250 };
 251
 252 &u3phy {
 253         status = "okay";
 254 };